JP2000293134A - Picture display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display a picture in which the color slippage is not present even while shortening the transfer time of modulated signals in the case of performing a color display. SOLUTION: A display panel P2000 has surface conduction type emission elements P20001 wired to row-direction wirings P2002 and column-direction wirings P2003 with a matrix and it displays a picture by the application of a voltage from a scanning signal circuit part P1000 to the row-direction wirings P2002 and the application of luminance signals from a modulated signal part P1001 to the column-direction wirings P2003. The modulated signal part P1001 has X drivers P1002, P1003. The X drives have plural pairs of memories making memories equivalent to three primary colors one pair and plural shift registers which are provided corresponding to respective pairs and which outputs luminance signals which are respectively inputted from memories of respective colors to the column-direction wirings P2003 in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an image display device having a display panel for displaying a color image by emitting electrons from a large number of electron-emitting devices wired in a matrix.

[0002]

2. Description of the Related Art Conventionally, two types of electron emitting devices, a hot cathode device and a cold cathode device, are known. Among these, among the cold cathode devices, for example, a surface conduction type emission device, a field emission type device (hereinafter referred to as FE type), a metal / insulating layer / metal type emission device (hereinafter referred to as MIM type), and the like are known. I have.

[0003] As a surface conduction type emission element, for example, M.
I. Elinson, Radio Eng. ElectronPhys., 10, 1290 (19
65) and other examples described below.

The surface conduction electron-emitting device utilizes a phenomenon in which an electron is emitted when a current flows in a small-area thin film formed on a substrate in parallel with the film surface. As this surface conduction type emission element, Sn described by Elinson et al.
In addition to those using O ₂ thin films, those using Au thin films [G.
Dittmer: "Thin Solid Films", 9, 317 (1972)]
n ₂ O ₃ / SnO ₂ thin film [M. Hartwell and C.
G. Fonstad: "IEEE Trans. ED Conf.", 519 (1975)]
Or carbon thin film [Hisashi Araki et al .: Vacuum, 2nd
6, No. 1, 22 (1983)].

[0005] As a typical example of the device configuration of these surface conduction electron-emitting devices, FIG. 23 is a plan view of the device by M. Hartwell et al. Described above. In the figure, a conductive thin film 3004 made of a metal oxide is formed on a substrate 3001 by sputtering in an H-shaped planar shape. An electron emission portion 3005 is formed on the conductive thin film 3004 by performing an energization process called energization forming described below. The interval L in the figure is 0.5 to 1 [mm], and the width W is
It is set to 0.1 [mm]. In addition, for convenience of illustration, the electron emitting portion 3005 is shown in a rectangular shape at the center of the conductive thin film 3004, but this is a schematic one, and the position and shape of the actual electron emitting portion are faithfully represented. Not necessarily.

In the above-described surface conduction electron-emitting device including the device by M. Hartwell et al., An electron emission portion 3005 is formed by performing an energization process called energization forming on the conductive thin film 3004 before electron emission. Was common. That is, energization forming is
A constant DC voltage or a DC voltage which is boosted at a very slow rate of, for example, about 1 V / min is applied to both ends of the conductive thin film 3004 to energize the conductive thin film 304.
04 is locally destroyed or deformed or altered,
This is to form the electron-emitting portion 3005 in a state of being electrically high in resistance. Note that a crack is generated in a part of the conductive thin film 3004 that is locally broken, deformed, or altered.
When an appropriate voltage is applied to the conductive thin film 3004 after the energization forming, electrons are emitted in the vicinity of the crack.

As an example of the FE type, for example, WP Dyke
& WW Dolan, "Field emission", Advance in Elect
ron Physics, 8, 89 (1956) or CA Spindt, "P
hysical properties of thin-film field emission cat
hodes with molybdenium cones ", J. Appl. Phys., 47,
5248 (1976) and the like are known.

FIG. 24 shows a cross-sectional view of a device by CA Spindt et al. Described above as a typical example of this FE type device configuration. In the figure, 3010 is a substrate, 3011 is an emitter wiring made of a conductive material, 3012 is an emitter cone, 3013 is an insulating layer, and 3014 is a gate electrode. This device comprises an emitter cone 3012 and a gate electrode 3
By applying an appropriate voltage during 014, field emission is caused from the tip of the emitter cone 3012.

As another element structure of the FE type, FIG.
There is also an example in which the emitter and the gate electrode are arranged on the substrate almost in parallel with the substrate plane, instead of the laminated structure as shown in FIG.

Examples of the MIM type include, for example, C.I.
A. Mead, "Operation of tunnel-emission Devices",
J. Appl. Phys., 32, 646 (1961) and the like are known.

FIG. 25 shows a typical example of an MIM type element configuration.
Shown in The figure is a sectional view, in which 3020 is a substrate, 3021 is a lower electrode made of metal, 3022 is a thin insulating layer having a thickness of about 100 °, and 3023 is a thickness of 80 to 3
The upper electrode is made of a metal of about 00 °. In the MIM type, electrons are emitted from the surface of the upper electrode 3023 by applying an appropriate voltage between the upper electrode 3023 and the lower electrode 3021.

The above-described cold cathode device can obtain electrons at a lower temperature than the hot cathode device, and therefore does not require a heater for heating. Therefore, the structure is simpler than that of the hot cathode element, and a fine element can be produced. Further, even when a large number of elements are arranged on a substrate at a high density, problems such as thermal melting of the substrate hardly occur. Also, unlike the response speed is slow because the hot cathode element operates by heating the heater,
In the case of a cold cathode device, there is also an advantage that the response speed is high.

For this reason, research for applying the cold cathode device has been actively conducted.

For example, the surface conduction electron-emitting device has the advantage that a large number of devices can be formed over a large area because the structure is particularly simple and the production is easy among the cold cathode devices. Therefore, for example, Japanese Patent Application Laid-Open No.
As disclosed in JP-A-332-332, a method for arranging and driving a large number of elements has been studied.

As for the application of the surface conduction electron-emitting device, for example, an image forming apparatus such as an image display device and an image recording device, and an electron beam device such as a charged beam source have been studied.

In particular, as an application to an image display apparatus, for example, US Pat. No. 5,066,883, Japanese Patent Laid-Open No. 2-257551, and Japanese Patent Laid-Open No. 4-28137 by the present applicant.
As disclosed in Japanese Patent Application Laid-Open Publication No. H10-157, an image display device using a combination of a surface conduction electron-emitting device and a phosphor that emits light by collision of electrons has been studied. An image display device using a combination of a surface conduction electron-emitting device and a phosphor is expected to have better characteristics than other conventional image display devices. For example, compared to a liquid crystal display device that has become widespread in recent years, it is superior in that it is a self-luminous type and does not require a backlight and has a wide viewing angle.

A method of driving a large number of FE types is disclosed in US Pat. No. 4,904,8, filed by the present applicant.
No. 95. As an example of applying the FE type to an image display device, for example, a flat display device reported by R. Mayer et al. Is known [R. Meyer: "Rec".
ent Development on Microtips Display at LETI ", Tec
h. Digest of 4th Int. Vacuum Microelectronics Con
f., Nagahama, pp. 6-9 (1991)].

An example in which a number of MIM types are arranged and applied to an image display device is disclosed in, for example, Japanese Patent Application Laid-Open No.
No. 5,557,838.

FIG. 26 is a schematic block diagram of an image display device having a display panel in which electron-emitting devices are wired in a simple matrix.

In FIG. 26, a display panel 4006 is
A plurality of cold cathode elements 4001 are two-dimensionally arranged in a matrix and connected to the row wiring 4002 and the column wiring 4003, respectively. Such a simple wiring method is called a matrix wiring method. This matrix wiring method is easy to manufacture because of its simple structure.

Each column wiring 4002 is connected to a scanning circuit 4008 for generating a scanning signal.
Is connected to a modulation circuit 4007 which receives video data and generates a modulation signal for driving the display panel 4006.

[0022]

SUMMARY OF THE INVENTION However, HDT
In V, the number of horizontal video signals is 2556, the number of vertical scanning lines is 480, and the shift clock is 86 MHz in order to distribute the video signals with only one shift register.
This is necessary and has been an obstacle to design. In order to solve this, it is conceivable to divide one line into a plurality of units and to simultaneously perform data transfer using a shift register for each of the divided units.

However, in this method, when the display image is a single color, even if the write position of the data to the shift register shifts, the brightness simply changes by that amount, so that it does not cause a big problem. In the case of color, the color itself changes, and in some cases, the image becomes unsightly.

An object of the present invention is to provide an image display device capable of displaying an image without color shift while shortening the transfer time of a modulation signal in the case of color display.

[0025]

In order to achieve the above object, an image display apparatus according to the present invention comprises a plurality of electron-emitting devices arranged in a matrix with a plurality of row-direction wirings and a plurality of column-direction wirings. A display panel provided corresponding to the electron-emitting device and provided with phosphors of three primary colors that emit light by irradiation of electrons from each of the electron-emitting devices; and a scanning signal applying means for selectively applying a voltage to each of the row-direction wirings And a modulation signal applying means for applying a series of luminance signals to the respective column direction wirings for causing the phosphors corresponding to the electron-emitting devices connected to the same row direction wiring among the phosphors to emit light. A modulating signal applying unit configured to divide the series of luminance signals into a plurality of pieces, store each of the three primary colors, and store each of the divided units, and serially output the divided signals; The luminance signal of the three primary colors outputted from said memory provided with a plurality of shift register for outputting in parallel to the column direction wirings.

In the image display device of the present invention configured as described above, a series of luminance signals is divided into a plurality of signals, and a memory is provided for each of the divided units and for each of the three primary colors (R, G, B). Since a shift register is provided for each of the divided units, writing of a luminance signal to the shift register is performed for each color.

[0027]

Next, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram of a display panel of an image display device according to a first embodiment of the present invention and a drive circuit section thereof. FIG. 2 is a block diagram of the analog processing unit, FIG. 3 is a block diagram of the decoder unit, and FIG. 4 is a block diagram of the timing generation unit.

As shown in FIGS. 1 to 4, the image display device of the present embodiment comprises a display panel P2000 for displaying an image,
A driving circuit unit for driving the display panel P2000;
A decoder that decodes an external image signal, a timing generator that generates a timing signal required to convert an analog signal decoded by the decoder into a digital signal, and a drive that converts the analog signal into a digital signal And an analog processing unit for outputting to the circuit unit.

In the present embodiment, the display panel P2000 has a matrix wiring composed of 480 rows of row wirings P2002 and 2556 columns of column wirings P2003.
It has 80 × 2556 surface conduction type devices P2001.

Here, the configuration of the display panel P2000 will be described with reference to FIG. FIG. 5 shows the display panel P2.
000 is a perspective view showing an example of 000, in which a part of the panel is cut away to show the internal structure.

In the figure, P2015 is a rear plate, P20
Reference numeral 16 denotes a side wall, and P2017 denotes a face plate. The rear plate P2015, the side wall P2016, and the fuse plate P20117 form an envelope (airtight container) for maintaining the inside of the display panel P2000 at a vacuum. The rear plate P2015 has a substrate P2011
Are fixed, but the above-mentioned 480 × 2556 surface conduction type elements P2001 and each surface conduction type element P20
01, the row direction wiring P2002 and the column direction wiring P
2003 is formed on the substrate P2011.
The portion constituted by the substrate P2011, the surface conduction element P2001, the row-direction wiring P2002, and the column-direction wiring P2003 is called a multi-electron beam source. In addition, an insulating layer (not shown) is formed at least at a portion where the row wiring P2002 and the column wiring P2003 intersect, so that electrical insulation is maintained.

Each row-direction wiring P2002 is connected to a scanning signal circuit P1000 (FIG. 1) via an electrical connection terminal or a flexible cable while maintaining the hermetic structure of the envelope.
Reference). Each column direction wiring P2003
Similarly, is electrically connected to the modulation signal circuit unit P1001 (see FIG. 1).

On the lower surface of the face plate P2017,
A phosphor film P2018 made of a phosphor is formed, and a metal back P2019 made of Al or the like is formed on the surface of the phosphor film P2018 on the rear plate P2015 side. The metal back P2019 is electrically connected to the high-voltage power supply unit P30 (see FIG. 1). As shown in FIG. 6, the phosphor film P2018 has three primary color phosphors P2018R, P2 of red (R), green (G), and blue (B).
018G and P1018B are painted in vertical stripes. Further, a black conductor P2018a is provided between the respective color phosphors P2018R, P2018G, and P2018B constituting the phosphor film P2018.

The inside of the airtight container is 10 ⁻⁶ To.
As the display area of the image display device is maintained at a vacuum of about rr and as the display area of the image display device increases, a means for preventing deformation or destruction of the rear plate P2015 and the face plate P2017 due to a pressure difference between the inside and the outside of the airtight container is required. . The method by increasing the thickness of the rear plate P2015 and the face plate P2016 not only increases the weight of the image display device, but also causes image distortion and parallax when viewed from an oblique direction. Therefore, in the present embodiment, a structural support P2020 made of a relatively thin glass plate and supporting the atmospheric pressure is provided. Thus, the substrate P on which the multi-beam electron source is formed
Normally, the distance between the 2011 and the face plate P2016 on which the fluorescent film P2018 is formed is kept at a sub-millimeter to several millimeters.

In the display panel P2000 described above, when a voltage is applied to each surface conduction type element P2001 through the row direction wiring P2002 and the column direction wiring P2003, electrons are emitted from each surface conduction type element P2001. At the same time, a high voltage of several hundred [V] to several [kV] is applied to the metal back P2019 by the high voltage power supply unit P30 to accelerate the emitted electrons and collide with the inner surface of the face plate P2017. As a result, the phosphors of each color forming the phosphor film P2018 are excited and emit light, and an image is displayed.

In this embodiment, an application example of displaying a TV image equivalent to HDTV on the display panel P2000 having the number of pixels of 852 (RGB trio) in the horizontal direction × 480 lines in the vertical direction as described above is described. Not limited to this, it is possible to easily cope with image signals having different resolutions and frame rates, such as output images of an NTSC or a computer, with almost the same configuration.

Next, returning to FIGS. 1 to 4, each circuit section of this embodiment will be described.

The decoder section P1 shown in FIG. 3 outputs HDTV RGB signals. The synchronization signal (SYN) superimposed on the input video signal in this unit
C) is separated and output, and a sampling CLK signal (CLK
1) is generated and output.

The timing generator P2 shown in FIG. 4 is necessary for converting the analog RGB signals decoded by the decoder P1 into digital gradation signals for luminance modulation of the display panel P2000. The following timing signals are generated. (1) Clamp pulse: R • G • from the decoder unit P1
A signal for DC reproduction of the B analog signal by the analog processing unit P3 shown in FIG. (2) Blank pulse (BLK pulse): Decoder section P
The analog processing unit P3 converts the R, G, B analog signals from
A signal for adding a blank period. (3) Detection pulse: A signal for detecting the level of an RGB analog signal by the video detection unit 4 shown in FIG. (4) Sample CLK (CLK2): analog RGB
A signal for converting the B signal into a digital signal at the A / D section P6 shown in FIG. 2. When a synchronization signal (SYNC) is input, CLK1 is sampled CLK (CLK2).
When the synchronization signal (SYNC) is not input, the self-running CLK signal (not shown) is output as the sample CLK.
By outputting the signal as (CLK2), the sample CLK (CLK2) can be output even when there is no input video signal. (5) RAM controller control signal: RAM shown in FIG.
Signals required for the controller P12 to control the RAM (P8). (6) Self-running CLK signal (not shown): timing generator P
2, when the synchronization signal (SYNC) is not input, the free-running CLK signal is used as the sample CLK.
A signal output as (CLK2). (7) Synchronous signal (SYNC2): Synchronous signal (SYNC)
Is input, the synchronization signal (SYNC) is output as the synchronization signal (SYNC2), and the synchronization signal (SYNC) is output.
Is generated based on a free-running CLK signal (not shown) in the timing generator P2 when is not input.

As described above, the timing generator P2
Has a means for generating a free-running CLK signal (not shown), and can generate the reference signals CLK2 and SYNC2 even when there is no input video signal.
An image can be displayed by reading the image data of AM (P8).

The analog processing section P3 shown in FIG. 2 is an analog processing section provided for each output primary color signal from the decoder section P1, and mainly performs the following operation. (1) Receiving a clamp pulse from the timing generator P2, DC regeneration is performed. (2) A blanking period is added by receiving a BLK pulse from the timing generator P2. (3) Receiving the gain adjustment signal of the D / A section P14, which is one of the control outputs of the system control section mainly composed of the MPU (P11), and controlling the amplitude of the primary color signal input from the decoder section P1. . (4) Upon receiving the offset adjustment signal of the D / A unit P14, the black level control of the primary color signal input from the decoder unit P1 is performed.

The video detecting section P4 is for detecting an input video signal level or a video signal level after being controlled by the analog processing section P3.
Upon receiving a detection pulse from the timing generator P2, the MPU
The detection result is read by the A / D unit P15, which is one of the control inputs of the system control unit configured around (P11).

The detection pulse from the timing generator P2 is composed of, for example, a gate pulse, a reset pulse, and a sample and hold (hereinafter, S / H) pulse (not shown). The video detector P4 is, for example, an integrating circuit (not shown). And S /
It consists of H circuits.

For example, during the valid period of the input video signal by the gate pulse, the video signal is integrated by the above-mentioned integration circuit, and the S / H pulse generated by the S / H pulse generated during the vertical blanking period.
The circuit samples the output of the integration circuit. After the detection result is read by the A / D section P15 during the vertical flyback period, the reset circuit initializes the integration circuit and the S / H circuit.
With such an operation, the average video level for each field can be detected.

The LPF (P5) is a pre-filter means placed before the A / D section P6. The A / D unit P6 receives the sample CLK signal (CLK) from the timing generation unit P2.
2), the analog primary color signal that has passed through the LPF (P5) is quantized by the required number of gradations.

The RAM (P8) is an image memory provided for each R / G / B processing circuit.
(In this case, horizontal 852 × vertical 480 lines × 3). In this memory, the luminance data to be emitted by each picture element of the display panel P2000 is stored, and the luminance data is read out in a dot-sequential manner to display the image stored in the memory on the display panel P2000.

The output of the luminance data stored in the RAM (P8) is performed under the address control from the RAM controller P12.

On the other hand, the writing of data to the RAM (P8) is performed under the management of a system control unit mainly composed of the MPU (P11). For simple test patterns, MPU (P11) is RAM (P8)
Calculate and generate and write the luminance data to be stored at each address. If the pattern is a natural still image, for example, an image file stored in an external computer
The serial communication I / F (P1), which is one of the input / output units of the system control unit configured around the U (P11)
6) and write it to the RAM (P8).

The data selector P9 converts the output image data into data from the RAM (P8),
Whether the data from the / D unit P6 (input video signal system) is used is determined by the I / O control unit P which is one of the control inputs and outputs of the system control unit mainly composed of the MPU (P11).
13 is determined.

In addition to the input selection of these two systems, a mode for generating a fixed value from the data selector P9 is provided.
This mode can be selected and output by the control unit P13. In this mode, for example, an adjustment signal such as an all-white pattern can be displayed at high speed without an external input.

The inverse γ table P7 is a gradation characteristic conversion means provided for converting the input video signal into the light emission characteristics of the display panel P2000. In the case of expressing a luminance gradation by pulse width modulation as in the present embodiment,
It often shows a linear characteristic in which the light emission amount is almost proportional to the size of the luminance data. On the other hand, since the video signal is intended for a TV receiver using a CRT, the video signal is subjected to γ processing in order to correct the nonlinear light emission characteristics of the CRT. Therefore, when a TV image is displayed on the display panel P2000 having linear light emission characteristics as in the present embodiment, it is necessary to cancel the effect of the γ processing by the gradation characteristic conversion means such as the inverse γ table P7. Note that the issuance characteristics of the display panel P2000 can be changed as desired by switching the table data based on the output of the I / O control unit P13.

First and second line memories P22, P2
Reference numeral 3 denotes a horizontal one-line memory means provided for each primary color signal, and the RD of the line memory control unit P21 shown in FIG.
By the control signal, the luminance data of each of R, G, B
The signals of the two systems are converted to output simultaneously two signals before and after the time, and the signals of the luminance data 1 and the luminance data 2 of the two systems of R, G, and B are respectively latched by the latch means P24 and P25 in FIG. X driver 1 (P1002) and X driver 2 (P1003) of modulation signal circuit section P1001 shown
Output to Thereby, the data transfer time can be doubled.

The system control section mainly includes an MPU
(P11), a serial communication I / F (P16), an I / O control unit P13, a D / A unit P14, an A / D unit P15, a data memory P17, and a user SW (P18).

The system control section includes a user switch
(P18) or a user request from the serial communication I / F (P16), and sends a corresponding control signal to the I / O control unit P1.
3 and the output from the D / A unit P14 realizes the request. Further, a control signal corresponding to the system monitoring signal from the A / D unit P15 is transmitted to the I / O control unit P13 and the D / A
Optimal automatic control is performed by outputting from the section P14.

Further, display control such as test pattern generation, variable gradation, brightness, and color control can be realized according to a user request. Also, as described above, the A / D section P15 can monitor the average video level from the video detection section P4 to automatically control ABL and the like.
Further, by providing the data memory P17, the user adjustment amount can be stored.

As shown in FIG. 4, the driver timing generation circuit has a Y driver control timing generator P19 and an X driver control timing generator P20. Both receive the CLK1, CLK2, and SYNC2 signals and generate a Y driver control signal and an X driver control signal, respectively.

The line memory control unit P21 is a control unit for controlling the timing of each of the line memories P22 and P23. The line memory control unit P21 receives the signals CLK1, CLK2 and SYNC2, and writes R and R for writing luminance data to the line memory. G, B WRT control signals and R
R, G, and B Rs for converting the luminance data of each of G and B so as to simultaneously output signals of two systems before and after in time, and reading the luminance data of each of R, G, and B.
Generate a D control signal.

The scanning signal circuit portion P1000 shown in FIG.
Upon receiving a control signal from the above-described Y driver control timing generation section P19, the control section outputs a signal for selecting the row direction wiring P2002. An example of a row-direction wiring drive waveform is shown at T112 in FIG. Further, the scanning voltage −Vss at the time of selecting the row direction wiring can be controlled by the D / A unit P14. Similarly, the high-voltage power supply unit P30 is also controlled by the D / A unit P14, which is one of the control inputs and outputs of the system control unit.

The modulation signal circuit portion P1001 includes an X driver 1 (P1002), an X driver 2 (P1003), and a Vmax regulator P100 formed on the same substrate.
4

In this embodiment, the X driver 1 (P
1002) and the X driver 2 (P1003) are synthesized on the same substrate and have different functions according to the substrate select signal from the MPU (P11).

Here, the X driver 1 (P1002) and the X driver 2 (P1003) will be described with reference to FIGS.

The X driver 1 (P1002) and the X driver 2 (P1003) have the same configuration,
1005, a driver section P1006, and an X driver timing generation section P1007 (P1008).
The memory unit P1005 includes a luminance signal line memory P1009 to temporarily record luminance data of each of R, G, and B.
P1032 and a correction memory P1 for recording correction data
033 to P1040.

<Write Operation> Latch means P2 shown in FIG.
4, RGB divided into two layers output from P25
Each of the luminance data is converted to a luminance signal line memory P1009 to P1032 by a line memory control signal (write enable signal, write reset signal, write clock signal of T114 in FIGS. 11 to 14) from the X driver timing generators P1007 and P1008. Figure 11
The luminance data (line memory input data) of T115 of 14 is written. However, the input luminance data includes invalid data for keeping the number of data strings that do not contribute to light emission constant.

At this time, the luminance data of each of the two layers R, G, and B is further divided into four layers as shown at T113 in FIG. Then, in order to divide the data into four layers, 109 × 2 pieces of data for two lines in the scanning direction of each of R, G, and B are first transmitted to the line memory control signal T114 (write enable signal, write reset signal , The write clock signal), the luminance signal line memories P1009 to
P1011, P1021 to P1023 are written, and thereafter, the luminance signal line memories P1012 to P1014, P1 are sequentially output by the line memory control signal T114 in FIG.
024 to P1026, the line memory control signals T114 in FIG.
At 1017, P1027 to P1029, the luminance signal line memories P1018 to P1020, P1030 to P1032 are written by the line memory control signal T114 of FIG. Here, the luminance signal line memories P1009 to P1009 to
P1032 is a clock synchronous line memory.

The write enable signal, write reset signal, and write clock signal of the line memory control signal T114 shown in FIGS. 11 to 14 of the X driver 1 (P1002) and the X driver 2 (P1003) are MPU (P
By selecting a signal prepared in two systems in advance, delaying one signal, or changing a decode value of a signal generated by decoding a clock in accordance with the substrate select signal from 11), the driver Different signals are output every time.

<Read Operation> Thereafter, the luminance data is stored in the luminance signal line memories P1009 to P1011 and P102.
1 to P1023, shown at T116 in FIG.
The line memory control signals read enable signal, read reset signal, and read clock signal from the X driver timing generators P1007 and P1008 are used to read the luminance signal line memories P1012 to P1014 and P1024.
16 to P1026, the line memory control signal T116 in FIG.
In P1017, P1027 to P1029, FIG.
Line memory control signals T116, the luminance signal line memories P1018 to P1020, P1030 to P1
032, the line memory control signal T11 of FIG.
According to 6, the luminance data of each of R, G, B is rearranged in an order according to the phosphor color of the panel connected by the column wiring P2003, and is converted into a serial signal.

Then, the luminance signal line memory P100
9 to P1011 and P1021 to P1023 are stored in the shift registers P1041 and P1045, and the luminance signal line memories P1012 to P1014 and P1024 to
The luminance data of P1026 is transferred to the shift register P1042,
P1046 has a line memory for luminance signal P1015 to P1046.
1017, the luminance data of P1027 to P1029 are stored in the shift registers P1043, P1047, and the line memories for luminance signals P1018 to P1020, P1030 to P10.
32 luminance data in shift registers P1043, P10
47.

The read enable signal, the read reset signal, and the read clock signal of the line memory control signal T116 shown in FIGS. 15 to 18 of the X driver 1 (P1002) and the X driver 2 (P1003) are MPU (P
By selecting a signal prepared in two systems in advance, delaying one signal, or changing a decode value of a signal generated by decoding a clock in accordance with the substrate select signal from 11), the driver Different signals are output every time.

Then, as shown in FIGS.
320-pulse shift clock (SFTCLK) T1 from driver timing generators P1007, P1008
07, the luminance signal line memories P1009-P1
011, P1012 to P1014, P1015 to P10
17, P1018 to P1020, P1021 to P102
3, P1024 to P1026, P1027 to P102
9, 320 pieces of luminance data among the respective pieces of luminance data output from P1030 to P1032 are simultaneously transferred to shift registers P1041, P1042, P1043, and P1.
044, P1045, P1046, P1047, P10
48, respectively.

The correction setting data output from the I / O control unit P13 is transferred to the X driver timing generation unit P1007,
The memory write signal of the memory control signal from P1008
Write to the correction memories P1033 to P1040 at the time of startup or during the flyback period by the address signal.
It outputs to the shift registers P1049 to P1056 according to the memory read signal and the address signal of the memory control signal from the X driver timing generators P1007 and P1008. A memory write signal, a memory read signal, and an address signal of the memory control signal are the X driver 1 (P1002)
And the X driver 2 (P1003), the MPU (P1
By judging the substrate select signal from 1), a signal having a different address value is output.

The driver section P1006 includes shift registers P1041 to P1048 for luminance data, shift registers P1049 to P1056 for amplitude data, and a PWM generator section P1057 provided for each column direction wiring.
, A D / A unit P1058, a switch means P1059 composed of a transistor or the like, and a diode means P10
60.

The PWM generator unit P1057 provided for each column wiring includes shift registers P1041 to P1
048, and generates a pulse signal having a pulse width proportional to the data size in each horizontal cycle. The D / A unit P1058 is a current-output digital-to-analog converter, and each of the shift registers P1049 to P105
6, and generates a drive current having a current amplitude proportional to the size of the data in each horizontal cycle.

The diode means P1060 provided for each column direction wiring has a Vmax regulator P10 on the common side.
04. The Vmax regulator P1004 is a constant voltage source capable of sinking current, and together with the diode means P1060, the 255 of the display panel P2000.
A protection circuit for preventing an overvoltage from being applied to each of the 6 × 480 surface conduction type devices P2001 is formed. The protection voltage (Vmax and the potential defined by −Vss applied when scanning of the row wiring P2002 is selected) is MPU (P
11) is provided by the D / A unit P14, which is one of the control inputs and outputs of the system control unit configured mainly. Therefore, in addition to the element overvoltage prevention, V
It is also possible to change the max potential (or -Vss potential). In this embodiment, the Vmax regulator P1004 is connected to the X driver 1 (P1002) and the X driver 1 (P1002).
Although the example in which the driver 2 (P1003) is provided as a common component is shown, the X driver 1 (P1002) and the X driver 2 (P1003) are provided separately,
max may be controlled independently for each driver.

X driver timing generator P1007
Receives a board select signal from the MPU (P11), an X driver control signal from the X driver control timing generator P20, a correction address and correction setting data from the I / O control unit P13, and The signal of is output.

(1) R from latch means P24, P25
Memory write control which is a line memory control signal T114 (write enable signal, write reset signal, write clock signal) which is a memory write control signal for writing each of G and B luminance data into the luminance signal line memories P1009 to P1032. Signals and R, G, and G signals from the luminance signal line memories P1009 to P1032.
B is rearranged in the order according to the panel color arrangement, and converted into a serial signal.
A memory read control signal which is a line memory control signal T116 (read enable signal, read reset signal, read clock signal) to be output to 41 to P1048. The memory write control signal (T114) and the memory read control signal (T116) are different from the MPU (P11) in the X driver 1 (P10
02) and X driver 2 (P1003)
By selecting a signal prepared in two systems in advance, delaying one signal, or changing a decode value of a signal generated by decoding a clock, a different signal is output for each driver. .

(2) A memory write control signal for receiving a correction address and correction setting data from the I / O control unit P13 and writing the correction setting data to the correction memories P1033 to P1040, and an address signal and correction data for correcting Shift registers P10 from memories P1033 to P1040
49 to P1056 Memory read control signals to be output.

(3) Line memory P1009 for luminance signal
Shift clock signal T107 as a PWM data shift signal for reading the luminance data T117 from .about.P1032 into the shift registers P1041 to P1048.

(4) Correction memories P1033 to P104
The correction data from 0 is transferred to the shift registers P1049 to P1
056, a shift clock signal as an amplitude data shift signal to be read.

(5) Shift registers P1041 to P10
48, the data read into P1049 to P1056
For fetching to a memory unit (not shown) in the WM generator unit P1057 and the D / A unit P1058,
P to generator P1057 and D / A P1058
A load start pulse that acts as a horizontal period trigger and a PWM start trigger as a WM control signal and a D / A control signal.

FIG. 9 is a timing chart showing the operation of each unit described above. The signal T104 is a waveform of a color sample data string written using one of R, G, and B colors as an example, and is composed of 852 data strings in one horizontal period. This data string is output for one horizontal period by the control signal.
426 and 427 to 852 are written in the line memories P22 and P23. In the next horizontal period, the line memories P22 and P23 for each color are enabled to be read at half the frequency in the case of writing, so that T10
5, a two-layer luminance data string (luminance data 1 and luminance data 2) of 426 color samples per one horizontal period is obtained. The color sample luminance data 1 (T105) is transmitted to the X driver 1 (P1002) by the color sample luminance data 2 (T1).
05) is input to the X driver 2 (P1003).

Each of the luminance signal line memories P1009-P
From 1032, the R, G, and B luminance data are rearranged in an order according to the panel color arrangement, and the current value data T106 corresponding to the luminance signal of every 320 effective data converted into a serial signal is generated by X driver timing generation. Part P1007
Are transferred to the shift registers P1041 to P1048 by the shift clock T107 synchronized with the luminance data from. The current value data of the shift registers P1041 to P1048 is transferred to the PWM generator unit P1057 at a time according to the "L" level of the load start pulse T108. Similarly, the amplitude data of the shift registers P1049 to P1056 is converted into D / A by the "L" level of the load start pulse T108.
Data for one horizontal row of 2556 is transferred to the unit P1058 at a time. Here, the correction data is controlled by the current amplitude, but of course, the circuit may be controlled by the voltage amplitude.

The PWM generator section P1057 provided for each column direction wiring is provided with a load start pulse T108
Shift register P1041 to P104
8 and receives the load start pulse T1
After the rising edge of 08, a pulse signal having a pulse width proportional to the data size is generated for each horizontal cycle, such as the waveform shown at T110.

D / A section P1 provided for each column direction wiring
Reference numeral 058 denotes a current-output digital-to-analog converter which receives current amplitude value data from the shift registers P1049 to P1056, and generates a current amplitude value as shown in a waveform T109 in FIG.
A drive current having a current amplitude proportional to the data size is generated for each horizontal cycle. An example of the column-direction wiring drive waveform of the output of the switching means P1060 is shown at T111 in FIG.

As described above, the luminance signal line memories P1009 to P1032 are provided for each of the R, G, and B colors, and the luminance data shift registers P1041 to P10
Since data is written to the shift registers P1041 to P1048, address shifts are prevented when writing data to the shift registers P1041 to P1048. As a result, a good image without color shift can be displayed. . In addition, since data is simultaneously written from the luminance signal line memories P1009 to P1032 to the corresponding shift registers P1041 to P1048, the time required for data transfer is also reduced.

In the present embodiment, as described above, the modulation signal circuit section P1001 includes the driver section P1006, the memory section P1005, and the X driver timing generation section P1007.
(P1008), and has a function of outputting different signals as control signals inside the board in accordance with the board select signal. Since a circuit can be formed on the same substrate, it is advantageous in terms of cost.

In this embodiment, the substrate select signal is set to MPU
Although output is performed from (P11), the present invention is not limited to this, and it may be as simple as connecting one of the substrate select signal terminals to GND and the other to 5V.

In the present embodiment, the circuit is constituted by two identical substrates. However, the present invention is not limited to this, and if a substrate select signal corresponding to the substrate is prepared, even a configuration having more than two substrates is possible. I don't care.

As described above, the display panel P20
00 and the modulation signal circuit portion P1001 (specifically, the X driver 1 (P1002) and the X driver 2 (P1003)) are electrically connected via an electric connection terminal or a flexible cable. Here, when both are connected by a flexible cable, the flexible cable has a structure in which the wiring is fixed by a resin film, and the degree of expansion or contraction due to the temperature of the resin film depends on the display panel P20.
Different from that of 00. Therefore, the display panel P200
1 having the same number of wires as the number of column-direction wires P2003 of 0
If two flexible cables are used, the difference in pitch between the wirings at both ends may be large, resulting in poor contact. Therefore, when a flexible cable is used, it is preferable to use a plurality of flexible cables in parallel in order to avoid accumulation of the pitch shift.

At this time, if one flexible cable is to be connected across a plurality of drivers, it is necessary to branch the flexible cable, which is not preferable from the viewpoint of the routing of the flexible cable and the length of the electrical path. Therefore, it is preferable that one flexible cable be connected to one driver without straddling a plurality of drivers. In particular, it is more preferable that the driver supplies a signal from the shift register to each wiring of the flexible cable.

(Second Embodiment) FIG. 19 is a block diagram of a display panel of an image display device and a drive circuit thereof according to a second embodiment of the present invention. FIG. 20 is a block diagram of the analog processing unit, and FIG. 21 is a block diagram of an X driver of the modulation signal circuit unit shown in FIG.
FIG. 22 is a diagram showing the correspondence between the display panel shown in FIG. 19 and the signal lines of the X driver.

In this embodiment, the basic configuration is the same as that of the first embodiment. However, as shown in FIG. 19, in this embodiment, the modulation signal circuit section P1001 has one X driver P1.
002, and one line of luminance data is sent to the X driver P1002 for each color. Accordingly, in the analog processing section, as shown in FIG. 20, one line memory P22 and one latch means P24 are provided for each color. Further, as shown in FIG. 21, in the first embodiment, all the components divided into two X drivers are included in one X driver P1002.

Further, as shown in FIGS. 21 and 22,
Shift the luminance data and the correction data by 320 each 8
Shift registers P1041 to P1048, P104
9 to P1056, the number of shifts is 320 × 8 = 2560, and the PWM generator P1057, the D / A P1058, and the switch P
1059 and diode means P1060 are also 25
There are 60 of them. In contrast, the display panel P20
There are 2556 columns of column wiring P2003 of 00, and four output terminals of the X driver P1002 are left. Therefore, 256
Out of the zero output terminals, two lines on each of the left and right sides are not connected to the column wiring P2003. Note that, even in the configuration having two X drivers as in the first embodiment, if the number of output terminals does not match the number of column wirings P2003, the remainder is output as in the present embodiment. It can be located at the end of the array of terminals.

The other configuration is the same as that of the first embodiment, and the detailed description is omitted.

Next, signal reading / reading in the present embodiment will be described.
The write operation will be described.

<Write Operation> The luminance data 1 of each of R, G, and B output from the latch means P24 is converted into a write enable signal of the line memory control signal T114 (FIGS. 11 to 14) from the X driver timing generator P1007, By write reset signal and write clock signal,
Writing is performed to the luminance signal line memories P1009 to P1032 (T115 in FIGS. 11 to 14). However, the input luminance data includes invalid data for keeping the number of data strings that do not contribute to light emission constant.

At this time, the luminance data of each of R, G, and B is further divided into four layers as shown in FIG. And 4
First, in order to divide the data into layers, 109 × 2 pieces of data of two lines in the scanning direction of the data of R, G, and B are first shown in FIG.
1 according to the write enable signal, the write reset signal, and the write clock signal of the line memory control signal T114.
12 to P1023, and then sequentially in accordance with the line memory control signal T114 in FIG. 12 for the luminance signal line memories P1012 to P1014, P1024 to P102.
6, the line memory control signals T114 shown in FIG.
27 to P1029, the line memory control signal T shown in FIG.
114, the luminance signal line memories P1018 to P1
020, write to P1030 to P1032. here,
The luminance signal line memories P1009 to P1032 are clock synchronous line memories.

<Read Operation> The luminance data is stored in the luminance signal line memories P1009 to P1011 and P1021 to P1.
023, the X driver timing generator P10
07 to the following line memory control signals (read enable signal, read reset signal, read clock signal)
To output serial luminance data to the shift register.

(1) In response to the first line memory control signal 1 shown at T116 in FIG. 15, the luminance signal line memories P1010 (G1), P1011 (B1), and P100
By controlling the output in the order of 9 (R1),..., The serial luminance data is output to the shift register P1041 in the order of G → B → R → G → B → R. here,
The first G data and the second B data are output from the column wiring P of the display panel P2000 as the final signal output end.
In some cases, it is not connected to 2003, and the data is “0” data.

(2) The line memories P1012 (R2), P1013 (G2), and P101 for luminance signals are generated by the second line memory control signal 2 shown at T116 in FIG.
4 (B2),..., To output serial luminance data to the shift register P1042 in the order of R → G → B → R → G → B.

(3) In response to the third line memory control signal 3 shown at T116 in FIG. 17, the luminance signal line memories P1017 (B3), P1015 (R3), P101
6 (G3),..., To output serial luminance data to the shift register P1043 in the order of B → R → G → B → R → G.

(4) In response to the fourth line memory control signal 4 shown at T116 in FIG. 18, the luminance signal line memories P1019 (G4), P1020 (B4), and P101
8 (R4),..., To output serial luminance data to the shift register P1044 in the order of G → B → R → G → B → R.

(5) In response to the fifth line memory control signal 5 shown at T116 in FIG. 15, the luminance signal line memories P1021 (R5), P1022 (G5), and P102
3 (B5),..., To output serial luminance data to the shift register P1045 in the order of R → G → B → R → G → B.

(6) The luminance signal line memories P1026 (B6), P1024 (R6), and P102 are generated by the sixth line memory control signal 6 shown at T116 in FIG.
5 (G6),..., To output serial luminance data to the shift register P1046 in the order of B → R → G → B → R → G.

(7) The luminance signal line memories P1028 (G7), P1029 (B7), and P102 according to the seventh line memory control signal 7 shown at T116 in FIG.
7 (R7),..., To output serial luminance data to the shift register P1047 in the order of G → B → R → G → B → R.

(8) The luminance signal line memories P1030 (R8), P1031 (G8), and P103 are generated by the eighth line memory control signal 8 shown at T116 in FIG.
By controlling the output in the order of 2 (B8),..., The serial luminance data is output to the shift register P1048 in the order of R → G → B → R → G → B.

Then, as shown in FIGS. 15 to 18, X
The luminance signal line memories P1009 to P1011 and P1012 to P101 are generated by the 320-pulse shift clock T107 from the driver timing generator P1007.
4, P1015 to P1017, P1018 to P102
0, P1021 to P1023, P1024 to P102
6, P1027 to P1029, P1030 to P1032
Out of the luminance data output from the shift registers P1041 and P1
042, P1043, P1044, P1045, P10
46, P1047 and P1048.

As described above, in the present embodiment, FIG.
2, eight shift registers P1041 to P1048 for shifting the luminance data by 320 for the column direction wiring P2003 of 2556 horizontal rows, and outputting the luminance data to the shift register. According to the read enable signal, read reset signal, and read clock signal of the line memory control signal T116 of the line memories P1009 to P1032, the order of R, G, and B of the parallel-to-serial converted luminance data is determined according to the position of the shift register to be output. Control.

In the present embodiment, the number of shift registers is eight, and 8 = 3 × 3-1. Therefore, since the first data of the first shift register is G, the second shift register Is the first data of R, the first data of the third shift register is B, the first data of the fourth shift register is G, the first data of the fifth shift register is R, and the first data of the sixth shift register is Is B, the first data of the seventh shift register is G, and the first data of the eighth shift register is R.

The correction setting data output from the I / O control unit P13 is transferred to the correction memory P1 at the time of startup or during the retrace period by the memory write signal / address signal of the memory control signal from the X driver timing generation unit P1007.
033 to P1040, and thereafter, based on the memory read signal / address signal of the memory control signal from the X driver timing generator P1007, the shift register P10
49 to P1056.

The subsequent operation is the same as in the first embodiment.

In general, one of three luminance signals of R, G and B
When the luminance signal is multilayered in order to reduce the sampling frequency of the luminance signal to form one pixel, the number of shifts of the shift register is a multiple of three, and therefore the number of output channels of the driver is also a multiple of three. However, by controlling the luminance signal as in this embodiment, the number of shifts of the shift register need not be a multiple of three. Thus, an image display device can be manufactured without limiting the number of outputs of the driver.

[0113]

As described above, according to the present invention, a memory for storing a luminance signal is provided for each of R, G, and B colors.
By performing writing to the shift register for each color, a favorable image without color shift can be displayed.
Moreover, since a plurality of memories and shift registers are provided for each unit obtained by dividing a series of luminance signals into a plurality,
The signal transfer time can also be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a display panel of an image display device according to a first embodiment of the present invention and a drive circuit thereof.

FIG. 2 is a block diagram of an analog processing unit of the image display device according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a decoder unit of the image display device according to the first embodiment of the present invention.

FIG. 4 is a block diagram of a timing generator of the image display device according to the first embodiment of the present invention.

5 is a perspective view showing an example of the display panel shown in FIG.

6 is a diagram showing an arrangement of phosphors of each color in a phosphor film of the display panel shown in FIG.

FIG. 7 is a block diagram of the X driver 1 shown in FIG.

FIG. 8 is a block diagram of an X driver 2 shown in FIG.

FIG. 9 is a timing chart of each part of a drive circuit of the display panel.

FIG. 10 is a timing chart of luminance data and line memory input data.

FIG. 11 is a timing chart of a line memory control signal.

FIG. 12 is a timing chart of a line memory control signal.

FIG. 13 is a timing chart of a line memory control signal.

FIG. 14 is a timing chart of a line memory control signal.

FIG. 15 is a timing chart of a line memory control signal.

FIG. 16 is a timing chart of a line memory control signal.

FIG. 17 is a timing chart of a line memory control signal.

FIG. 18 is a timing chart of a line memory control signal.

FIG. 19 is a block diagram of a display panel of an image display device and a driving circuit thereof according to a second embodiment of the present invention.

FIG. 20 is a block diagram of an analog processing unit of the image display device according to the second embodiment of the present invention.

21 is a block diagram of the X driver shown in FIG.

22 is a diagram showing a correspondence relationship between the display panel shown in FIG. 19 and signal lines of an X driver.

FIG. 23 is a plan view of a conventional typical surface conduction electron-emitting device.

FIG. 24 is a cross-sectional view of a conventional field emission device.

FIG. 25 is a sectional view of a conventional MIM element.

FIG. 26 is a block diagram of a conventional image display device.

[Explanation of symbols]

P1 Decoder section P2 Timing generation section P3 Analog processing section P4 Video detection section P5 LPF P6, P15 A / D section P7 Reverse γ table P8 RAM P9 Selector P11 MPU P13 I / O control section P14, P1058 D / A section P19 Y driver Control timing generator P20 X driver control timing generator P21 Line memory controller P22, P23 Line memory P24, P25 Latch means P30 High voltage power supply P1000 Scan signal circuit P1001 Modulation signal circuit P1002, P1003 X driver P1004 Vmax regulator P1005 Memory Unit P1006 Driver unit P1007, P1008 X driver timing generation unit P1033 to P1040 Correction memory P1009 to P1032 Luminance signal line memory P 041 to P1056 Shift register P1057 PWM generator P1059 Switching means P1060 Diode means P2000 Display panel P2001 Surface conduction type element P2002 Row direction wiring P2003 Column direction wiring P2011 Substrate P2015 Rear plate P2016 Side wall P2017 Face plate P2018 Fluorescent film P2018R, P2018G, P2018B Fluorescence Body P2019 metal back

Claims (5)

[Claims] A plurality of electron-emitting devices arranged in a matrix on a plurality of row-direction wirings and a plurality of column-direction wirings; and a plurality of electron-emitting devices provided in correspondence with the electron-emitting devices. A display panel including phosphors of three primary colors that emit light upon irradiation; a scanning signal applying unit that selectively applies a voltage to each of the row-direction wirings; and an electron emission connected to the same row-direction wiring among the phosphors Modulation signal applying means for applying a series of luminance signals for causing the phosphors corresponding to the elements to emit light to the respective column direction wirings, wherein the modulation signal applying means divides the series of luminance signals into a plurality of pieces. A plurality of memories for storing the colors of the three primary colors and for each of the divided units and outputting serially, and a luminance signal of the three primary colors output from the memory provided in correspondence with the divided unit. An image display device comprising: a plurality of shift registers that output data in parallel to the column wiring. 2. The image display device according to claim 1, further comprising means for determining an input order of luminance signals from said memory to said shift register. 3. The image display device according to claim 2, wherein the input order is an order in which the three primary colors are repeated. 4. The image display device according to claim 3, wherein the order in which the three primary colors are repeated differs depending on each of the shift registers. 5. The image according to claim 1, wherein said modulation signal applying means has a plurality of drivers, and said drivers and said memories and said shift registers are allocated to said drivers. Display device.