JP2003249498A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device

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Publication number
JP2003249498A
JP2003249498A JP2002047333A JP2002047333A JP2003249498A JP 2003249498 A JP2003249498 A JP 2003249498A JP 2002047333 A JP2002047333 A JP 2002047333A JP 2002047333 A JP2002047333 A JP 2002047333A JP 2003249498 A JP2003249498 A JP 2003249498A
Authority
JP
Japan
Prior art keywords
film
opening
pad electrode
forming
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002047333A
Other languages
Japanese (ja)
Inventor
Masahiro Miyata
雅弘 宮田
Hirokazu Ezawa
弘和 江澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2002047333A priority Critical patent/JP2003249498A/en
Publication of JP2003249498A publication Critical patent/JP2003249498A/en
Pending legal-status Critical Current

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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for fabricating a semiconductor device in which the fabrication process can be simplified and the cost can be reduced. <P>SOLUTION: Following to formation of an uppermost trench interconnect layer 13 filled with Cu, a Cu antioxidation layer (SiN) 14, and a passivation film 17 are formed sequentially. The passivation film 17 above a Cu pad electrode part 13a is then opened up to the Cu antioxidation layer 14. Subsequently, the periphery of the opening is coated with a photosensitive polyimide film 19 for relaxing stress at the time of packaging. Following to final cure of the polyimide film, the Cu antioxidation layer 14 is removed by etching while using the polyimide film 19 itself as a mask to expose the Cu pad electrode part 13a and then a metal bump is formed thereat. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
方法に関し、特にＣｕ配線のパッド電極部にボール状の
半田バンプが形成された半導体装置の製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which ball-shaped solder bumps are formed on pad electrode portions of Cu wiring.

【０００２】[0002]

【従来の技術】近年、電子機器の小型化に伴い、半導体
装置においては、フリップチップ型ＢＧＡ（ＦＣ−ＢＧ
Ａ：Ｆｌｉｐ Ｃｈｉｐ−Ｂａｌｌ Ｇｒｉｄ Ａｒｒａ
ｙ）と呼ばれ、チップに所定のアレイ状に配列された配
線層のパッド電極部上に半田ボールバンプを形成して、
チップを直接プリント基板に実装する構造のものが盛ん
に研究・開発されている。2. Description of the Related Art In recent years, with the miniaturization of electronic equipment, flip chip type BGA (FC-BG) has been used in semiconductor devices.
A: Flip Chip-Ball Grid Arra
y), a solder ball bump is formed on the pad electrode portion of the wiring layer arranged in a predetermined array on the chip,
Research and development has been actively conducted on a structure in which a chip is directly mounted on a printed circuit board.

【０００３】また、電子機器の高速化に伴い、配線材料
としてＡｌ（アルミニウム）の代わりに、Ｃｕ（銅）が
用いられるようになってきた。With the increase in speed of electronic equipment, Cu (copper) has come to be used as a wiring material instead of Al (aluminum).

【０００４】そして、このような半導体装置において
は、実装時に、チップに加わる外部からの応力は、今ま
でになく厳しいものになっている。そこで、チップに加
わる応力を緩和するため、チップのパッシベーション膜
上にポリイミド樹脂を塗布し、これを３５０℃の温度で
キュアーして熱硬化させてポリイミド樹脂膜を形成して
いるが、このポリイミド樹脂膜の熱硬化時にＣｕパッド
電極部表面が酸化し、パッド電極部と半田ボールバンプ
との密着性強度や電気的コンタクト特性の劣化を招くた
め、Ｃｕパッド電極部上に酸化防止用のＡｌパッド電極
をキャップしている。In such a semiconductor device, the external stress applied to the chip during mounting is more severe than ever. Therefore, in order to relieve the stress applied to the chip, a polyimide resin is applied onto the passivation film of the chip, and the polyimide resin film is cured by curing at a temperature of 350 ° C. to form a polyimide resin film. The surface of the Cu pad electrode is oxidized when the film is cured by heat, and the adhesion strength between the pad electrode and the solder ball bump and the electrical contact characteristics are deteriorated. Therefore, an Al pad electrode for preventing oxidation is formed on the Cu pad electrode. Is capped.

【０００５】以下、このようなＡｌパッド電極キャップ
を使用した従来の半田ボールバンプの製造方法を、図１
５乃至図２２を用いて説明する。図１５（ａ）は、パッ
ド電極部の平面図、図１５（ｂ）は図１５（ａ）のＡ−
Ａ線に沿う工程断面図、図１６乃至図２２はいずれも工
程断面図である。A conventional method for manufacturing solder ball bumps using such an Al pad electrode cap will be described below with reference to FIG.
This will be described with reference to FIGS. FIG. 15A is a plan view of the pad electrode portion, and FIG. 15B is A- of FIG. 15A.
16A to 22 are process cross-sectional views along the line A, and FIGS.

【０００６】まず、半導体基板上の第１の層間絶縁膜１
００に配線溝１０１を形成し、この配線溝１０１内にバ
リアメタル膜１０２、例えば窒化タンタル（ＴａＮ）膜
を介してＣｕを主材料とするＣｕパッド電極部１０３ａ
を有するＣｕ配線層１０３を形成した後、このＣｕ配線
層１０３を含む前記第１の層間絶縁膜１００上にＣｕ配
線層の酸化を防止するための酸化防止膜１０４、例えば
窒化シリコン（ＳｉＮ）膜を成膜する（図１５（ａ）、
（ｂ））。First, the first interlayer insulating film 1 on the semiconductor substrate
Wiring groove 101 is formed in the wiring groove 101, and a Cu pad electrode portion 103a mainly made of Cu is formed in the wiring groove 101 via a barrier metal film 102, for example, a tantalum nitride (TaN) film.
After forming the Cu wiring layer 103 having Cu, an antioxidant film 104 for preventing oxidation of the Cu wiring layer, for example, a silicon nitride (SiN) film, is formed on the first interlayer insulating film 100 including the Cu wiring layer 103. Is formed (FIG. 15A),
(B)).

【０００７】次に、前記酸化防止膜１０４上の全面に、
第２の層間絶縁膜１０５、例えばＴＥＯＳ膜を成膜する
（図１６）。Next, on the entire surface of the antioxidant film 104,
A second interlayer insulating film 105, for example, a TEOS film is formed (FIG. 16).

【０００８】しかる後、通常のリソグラフィー技術によ
り、レジスト膜１０６をマスクにして前記パッド電極部
１０３ａ上の前記第２の層間絶縁膜１０５部分に第１の
開口部１０５ａを形成する（図１７）。この際、前記酸
化防止膜１０４が開口し、前記パッド電極部１０３ａが
露出しないようにエッチング時間をコントロールする。Thereafter, the first opening 105a is formed in the portion of the second interlayer insulating film 105 on the pad electrode portion 103a by using the resist film 106 as a mask by the ordinary lithography technique (FIG. 17). At this time, the etching time is controlled so that the antioxidant film 104 is opened and the pad electrode portion 103a is not exposed.

【０００９】次に、前記レジスト膜１０６を除去した
後、通常のドライエッチング技術により、前記第２の層
間絶縁膜１０５における第１の開口部１０５ａ内の前記
酸化防止膜１０４をエッチング除去して前記パッド電極
部１０３ａの一部を露出させる（図１８）。Next, after removing the resist film 106, the antioxidant film 104 in the first opening 105a in the second interlayer insulating film 105 is removed by etching by a normal dry etching technique. A part of the pad electrode portion 103a is exposed (FIG. 18).

【００１０】次に、通常のスパッタ成膜技術とリソグラ
フィー技術により、前記パッド電極部１０３ａ上に、Ｃ
ｕパッド電極部の酸化を防止するためのTaN系バリアメ
タルを介してＡｌパッド電極１０７を形成する（図１
９）。Next, C is formed on the pad electrode portion 103a by the usual sputter film forming technique and lithography technique.
The Al pad electrode 107 is formed through a TaN-based barrier metal for preventing the oxidation of the u pad electrode portion (FIG. 1).
9).

【００１１】次に、前記Ａｌパッド電極１０７を含む前
記第２の層間絶縁膜１０５上の全面にパッシベーション
膜１１０、例えば下層がＴＥＯＳ膜１０８、上層がＳｉ
Ｎ膜１０９の多層膜を、順次、成膜した後、通常のリソ
グラフィー技術により、前記第１の開口部１０５ａ上の
前記パッシベーション膜１１０部分を開口して前記Ａｌ
パッド電極１０７の一部を露出させる（図２０）。Next, a passivation film 110 is formed on the entire surface of the second interlayer insulating film 105 including the Al pad electrode 107, for example, a lower layer is a TEOS film 108 and an upper layer is Si.
After sequentially forming a multi-layered film of the N film 109, the passivation film 110 portion on the first opening 105a is opened by an ordinary lithography technique to form the Al film.
A part of the pad electrode 107 is exposed (FIG. 20).

【００１２】続いて、実装時に発生する応力を緩和する
ために、前記Ａｌパッド電極１０７部分を含む前記パッ
シベーション膜１１０上の全面に感光性ポリイミド樹脂
を塗布し、通常のリソグラフィー技術により、パターニ
ングして前記第１の開口部１０５ａ上にこれよりも広面
積の第２の開口部１１１ａを有するポリイミド樹脂膜１
１１を形成する（図２１）。この後、感光性ポリイミド
樹脂を約３５０℃の温度でキュアーして熱硬化させる。Subsequently, in order to relieve the stress generated at the time of mounting, a photosensitive polyimide resin is applied on the entire surface of the passivation film 110 including the Al pad electrode 107 portion and patterned by a usual lithography technique. A polyimide resin film 1 having a second opening portion 111a having a wider area than the first opening portion 105a.
11 is formed (FIG. 21). Then, the photosensitive polyimide resin is cured at a temperature of about 350 ° C. to be thermally cured.

【００１３】最後に、前記第２の開口部１１１ａ内のＡ
ｌパッド電極１０７、前記パッシベーション膜１１０、
前記ポリイミド樹脂膜１１１及び前記第２の開口部１１
１ａ周辺の前記ポリイミド樹脂膜１１１上面部にバリア
メタル膜１１２を形成した後、電解メッキ法、又は印刷
法等の半田バンプ形成工程を経て前記Ａｌパッド電極１
０７上に半田ボールバンプ１１３が形成されている半導
体装置を製作する（図２２）。Finally, A in the second opening 111a
l pad electrode 107, the passivation film 110,
The polyimide resin film 111 and the second opening 11
After forming a barrier metal film 112 on the upper surface of the polyimide resin film 111 around 1a, the Al pad electrode 1 is subjected to a solder bump forming process such as an electrolytic plating method or a printing method.
A semiconductor device having solder ball bumps 113 formed on 07 is manufactured (FIG. 22).

【００１４】[0014]

【発明が解決しようとする課題】ところで、上記従来の
半導体装置の製造方法では、製造工程が長くなるばかり
でなく、Ｃｕパッド電極部の酸化防止用キャップとして
のＡｌパッド電極を形成するために、Ａｌ蒸着及びＡｌ
のドライエッチング設備等を別途用意する必要が生じ、
初期投資額の増大を招き、製造コストの上昇を招くこと
になる。By the way, in the above-mentioned conventional method for manufacturing a semiconductor device, not only the manufacturing process is lengthened, but also the Al pad electrode as the oxidation preventing cap of the Cu pad electrode portion is formed. Al vapor deposition and Al
It is necessary to separately prepare the dry etching equipment of
This leads to an increase in initial investment amount and a rise in manufacturing cost.

【００１５】本発明は、上記課題に鑑みなされたもの
で、その目的とするところは、工程数の簡略化及び低コ
スト化が可能な半導体装置の製造方法を提供することに
ある。The present invention has been made in view of the above problems, and an object thereof is to provide a method of manufacturing a semiconductor device capable of simplifying the number of steps and reducing the cost.

【００１６】[0016]

【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体装置の製造方法は、半導体基板上の
層間絶縁膜にＣｕを主材料とし、パッド電極部を有する
埋め込み配線層を形成する工程と、前記埋め込み配線層
を含む前記層間絶縁膜上に配線層の酸化防止膜及びパッ
シベーション膜を、順次、成膜する工程と、前記パッド
電極部上の前記パッシベーション膜部に第１の開口部を
設けて前記酸化防止膜の一部を露出させる工程と、前記
第１の開口部の形成工程後に、前記第１の開口部と連接
する第２の開口部を有する熱硬化型の有機樹脂膜を前記
パッシベーション膜上に形成する工程と、前記有機樹脂
膜を熱硬化させる工程と、前記有機樹脂膜の熱硬化工程
後に、前記第１の開口部内の前記酸化防止膜をエッチン
グ除去して前記パッド電極部を露出させる工程と、前記
第１及び第２の開口部を介して前記パッド電極部に金属
バンプを形成する工程とを含むことを特徴としている。In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is directed to an interlayer insulating film on a semiconductor substrate, in which a main material is Cu and an embedded wiring layer having a pad electrode portion is formed. A step of forming an oxidation prevention film and a passivation film of a wiring layer on the interlayer insulating film including the embedded wiring layer, and a first step of forming a passivation film portion on the pad electrode portion. A thermosetting organic material having a second opening that is connected to the first opening after the step of providing the opening to expose a part of the antioxidant film and the step of forming the first opening. After the step of forming a resin film on the passivation film, the step of thermally curing the organic resin film, and the step of thermally curing the organic resin film, the antioxidant film in the first opening is removed by etching. The above A step of exposing the cathode electrode portion, and characterized in that it comprises a step of forming a metal bump to the pad electrode portion through the first and second openings.

【００１７】なお、上記発明において、前記第２の開口
部は第１の開口部より広面積で、且つ前記第１の開口部
上にこれと連接して設けることが好ましい。In the above invention, it is preferable that the second opening has a larger area than the first opening and is provided on the first opening so as to be connected to the second opening.

【００１８】また、上記発明において、前記有機樹脂膜
は、ポリイミド樹脂からなることが好ましい。In the above invention, the organic resin film is preferably made of polyimide resin.

【００１９】また、前記配線層の酸化防止膜は、ＳｉＮ
膜もしくはＳｉＣ膜からなることが好ましい。The antioxidant film of the wiring layer is made of SiN.
It is preferably made of a film or a SiC film.

【００２０】また、前記パッシベーション膜がＴＥＯＳ
膜の単層又は下層がＴＥＯＳ膜、上層がＳｉＮ膜、若し
くはＳｉＣ膜の多層からなることが好ましい。The passivation film is TEOS.
It is preferable that the single layer or the lower layer of the film is a TEOS film and the upper layer is a multilayer of a SiN film or a SiC film.

【００２１】また、上記目的を達成するために、本発明
の半導体装置の製造方法は、半導体基板上の層間絶縁膜
に形成した配線溝内にバリアメタル膜を介して、Ｃｕを
主材料とし、パッド電極部を有する埋め込み配線層を形
成する工程と、前記埋め込み配線層を含む前記層間絶縁
膜上にＳｉＮ膜及びパッシベーション膜を、順次、成膜
する工程と、前記パッド電極部上の前記パッシベーショ
ン膜部に第１の開口部を設けて前記ＳｉＮ膜の一部を露
出させる工程と、前記第１の開口部の形成工程後に、前
記第１の開口部上にこの第１の開口部より広面積の第２
の開口部を有する熱硬化型のポリイミド樹脂膜を前記パ
ッシベーション膜上に形成する工程と、前記ポリイミド
樹脂膜を熱硬化させる工程と、前記ポリイミド樹脂膜の
熱硬化工程後に、前記ポリイミド樹脂膜をマスクにして
前記第１の開口部内の前記ＳｉＮ膜をエッチング除去し
て前記パッド電極部を露出させる工程と、前記第１及び
第２の開口部を介して前記パッド電極部にバリアメタル
膜を介して半田バンプを形成する工程とを含むことを特
徴としている。In order to achieve the above object, in the method for manufacturing a semiconductor device of the present invention, Cu is used as a main material through a barrier metal film in a wiring groove formed in an interlayer insulating film on a semiconductor substrate, A step of forming a buried wiring layer having a pad electrode portion, a step of sequentially forming a SiN film and a passivation film on the interlayer insulating film including the buried wiring layer, and the passivation film on the pad electrode portion. A first opening on the first part to expose a part of the SiN film, and after the step of forming the first opening, an area larger than the first opening is formed on the first opening. Second
A step of forming a thermosetting polyimide resin film having an opening on the passivation film, a step of thermosetting the polyimide resin film, and a step of thermosetting the polyimide resin film, and then masking the polyimide resin film. And exposing the pad electrode portion by etching away the SiN film in the first opening, and through the barrier metal film to the pad electrode portion through the first and second openings. And a step of forming solder bumps.

【００２２】上記発明によれば、工程数が簡略化でき、
また低コスト化ができる。According to the above invention, the number of steps can be simplified,
Further, the cost can be reduced.

【００２３】[0023]

【発明の実施の形態】以下、図面を参照しながら本発明
の実施の形態に係わる半導体装置の製造方法ついて説明
する。 （第１の実施の形態）まず、本発明の第１の実施の形態
に係わる半導体装置の製造方法について、図１乃至図７
を参照して説明する。図１（ａ）はパッド電極部の平面
図、図１（ｂ）は図１（ａ）のＢ−Ｂ線に沿う断面図、
図２乃至図７は工程断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. (First Embodiment) First, a method of manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.
Will be described with reference to. 1A is a plan view of the pad electrode portion, FIG. 1B is a cross-sectional view taken along the line BB of FIG.
2 to 7 are process cross-sectional views.

【００２４】半導体基板上の層間絶縁膜１０に配線溝１
１を形成し、この配線溝１１内にバリアメタル膜１２、
例えば窒化タンタル（ＴａＮ）膜を介してＣｕを主材料
とするＣｕパッド電極部１３ａを有するＣｕ配線層１３
を形成した後、このＣｕ配線層１３を含む前記層間絶縁
膜１０上に通常のＣＶＤ（ＣＶＤ：Ｃhemical Vapor De
position）技術により、Ｃｕ配線層の酸化を防止するた
めの酸化防止膜１４、例えば窒化シリコン（ＳｉＮ）膜
を成膜する（図１（ａ）、（ｂ））。A wiring groove 1 is formed in the interlayer insulating film 10 on the semiconductor substrate.
1 is formed, and the barrier metal film 12,
For example, a Cu wiring layer 13 having a Cu pad electrode portion 13a containing Cu as a main material through a tantalum nitride (TaN) film.
Then, a normal CVD (CVD: Chemical Vapor Deposition) is formed on the interlayer insulating film 10 including the Cu wiring layer 13.
position) technique, an anti-oxidation film 14 for preventing oxidation of the Cu wiring layer, for example, a silicon nitride (SiN) film is formed (FIGS. 1A and 1B).

【００２５】次に、前記酸化防止膜１４上の全面に、通
常のＣＶＤ技術により、パッシベーション膜１７、例え
ば下層がＴＥＯＳ膜１５、上層がＳｉＮ膜１６の多層膜
を成膜する（図２）。Next, a passivation film 17, for example, a multi-layer film of a TEOS film 15 as a lower layer and a SiN film 16 as an upper layer is formed on the entire surface of the antioxidant film 14 by a normal CVD technique (FIG. 2).

【００２６】しかる後、通常のリソグラフィー技術によ
り、レジスト膜１８をマスクにして前記パッド電極部１
３ａ上の前記パッシベーション膜１７部分に第１の開口
部１７ａを形成する（図３）。ここでは、通常のドライ
エッチング技術により、まず、前記ＳｉＮ膜１６を選択
的に除去した後、次に、前記ＴＥＯＳ膜１５を選択的に
除去する。この際、前記酸化防止膜１４が開口し、前記
パッド電極部１３ａが露出しないようにエッチング時間
をコントロールする。Thereafter, the pad electrode portion 1 is formed by using the resist film 18 as a mask by a usual lithography technique.
A first opening 17a is formed in the passivation film 17 portion on 3a (FIG. 3). Here, the SiN film 16 is first selectively removed by a normal dry etching technique, and then the TEOS film 15 is selectively removed. At this time, the etching time is controlled so that the antioxidant film 14 is opened and the pad electrode portion 13a is not exposed.

【００２７】次に、前記レジスト膜１８を除去（図４）
した後、実装時に発生する応力を緩和するための有機樹
脂膜１９、例えば熱硬化性のポリイミド樹脂膜を前記第
１の開口部１７ａの周辺部における前記パッシベーショ
ン膜１７上に形成する（図５）。Next, the resist film 18 is removed (FIG. 4).
After that, an organic resin film 19 for relaxing the stress generated at the time of mounting, for example, a thermosetting polyimide resin film is formed on the passivation film 17 in the peripheral portion of the first opening 17a (FIG. 5). .

【００２８】ここでは、まず前記第１の開口部１７ａを
含む前記パッシベーション膜１７上の全面に感光性ポリ
イミド樹脂を塗布し、通常のリソグラフィー技術によ
り、パターニングして前記第１の開口部１７ａ上にこれ
よりも広面積の第２の開口部１９ａを有するポリイミド
樹脂膜１８を形成した後、ポリイミド樹脂のイミド化を
促進させるために、窒素雰囲気中で３００〜３５０℃の
温度でキュアー処理して熱硬化させる。Here, first, a photosensitive polyimide resin is applied to the entire surface of the passivation film 17 including the first opening 17a, and is patterned by a normal lithography technique to form a pattern on the first opening 17a. After forming the polyimide resin film 18 having the second opening 19a having a wider area than this, in order to promote imidization of the polyimide resin, a curing treatment is performed at a temperature of 300 to 350 ° C. in a nitrogen atmosphere and heat treatment is performed. Let it harden.

【００２９】このポリイミド樹脂のキュアー処理時に
は、前記Ｃｕパッド電極部１３ａ表面は、酸化防止膜１
４で覆われているため、酸化されることはない。During the curing process of the polyimide resin, the surface of the Cu pad electrode portion 13a is covered with the antioxidant film 1
As it is covered with 4, it is not oxidized.

【００３０】本実施の形態では、応力緩和用バッファー
材としてポリイミドを挙げたが、ＢＣＢ等半田リフロー
時の熱履歴に耐性のある、例えばＢＣＢ（ベンゾシクロ
ブタン：Benzo Cyclo Butane）等の有機樹脂膜に置き換
えても問題はない。In the present embodiment, polyimide is used as the buffer material for stress relaxation, but an organic resin film such as BCB (benzocyclobutane) having resistance to thermal history during solder reflow such as BCB is used. There is no problem if you replace it.

【００３１】次に、このポリイミド樹脂膜１９をマスク
にして、通常のドライエッチング技術により、前記第２
の開口部１９ａ内の前記酸化防止膜１４をエッチング除
去して前記パッド電極部１３ａの一部を露出させる（図
６）。Next, using the polyimide resin film 19 as a mask, the second dry etching technique is performed by a normal dry etching technique.
The antioxidant film 14 in the opening 19a is removed by etching to expose a part of the pad electrode portion 13a (FIG. 6).

【００３２】最後に、前記第２の開口部１９ａ内のＣｕ
パッド電極部１３ａ、前記パッシベーション膜１７、前
記ポリイミド樹脂膜１９及び前記第２の開口部１９ａ周
辺の前記ポリイミド樹脂膜１９上面部にバリアメタル膜
２０、例えばＰｄ／Ｎｉ／Ｔｉを形成した後、電解メッ
キ法、又は印刷法等の半田バンプ形成工程を経て前記Ｃ
ｕパッド電極部部１３ａ上に半田ボールバンプ２１が形
成されている半導体装置を製作する（図７）。Finally, Cu in the second opening 19a
After forming a barrier metal film 20, for example, Pd / Ni / Ti on the pad electrode portion 13a, the passivation film 17, the polyimide resin film 19, and the upper surface of the polyimide resin film 19 around the second opening 19a, electrolysis is performed. After the solder bump forming process such as the plating method or the printing method, the C
A semiconductor device in which the solder ball bumps 21 are formed on the u pad electrode portion 13a is manufactured (FIG. 7).

【００３３】この第１の実施の形態によれば、次のよう
な効果がある。即ち、従来の半導体装置の製造方法で
は、酸化防止膜としてのＳｉＮ膜を除去した後、Ｃｕパ
ッド電極部上を酸化防止用のＡｌパット電極でキャップ
し、その後、ポリイミド樹脂を塗布し、イミド化のため
のキュアー処理をしているが、本実施の形態では、パッ
シベーション膜に開口部を形成した後、ＳｉＮ膜を除去
せずに、前記パッシベーション膜上にポリイミド樹脂を
塗布しパターニングした後、キュアー処理を施して、こ
のポリイミド樹脂をマスクにＳｉＮ膜を除去してＣｕパ
ッド電極部を露出している。According to the first embodiment, there are the following effects. That is, in the conventional method of manufacturing a semiconductor device, after removing the SiN film as the anti-oxidation film, the Cu pad electrode portion is capped with an Al pad electrode for anti-oxidation, and then a polyimide resin is applied to imidize the film. In the present embodiment, after forming the opening in the passivation film, the polyimide resin is applied and patterned on the passivation film without removing the SiN film. By performing the treatment, the SiN film is removed using the polyimide resin as a mask to expose the Cu pad electrode portion.

【００３４】従って、本実施の形態では、Ａｌの蒸着及
びドライエッチング処理装置等を格別必要とせず、しか
も従来に比べて工程数も少なく、低コストで製造できる
という特徴がある。 （第２の実施形態）以下、本発明の第２の実施の形態に
係わる半導体装置の製造方法について、図８乃至図１３
を参照して説明する。図８（ａ）はパッド電極部の平面
図、図８（ｂ）は図８（ａ）のＣ−Ｃ線に沿う断面図、
図９乃至図１３は工程断面図である。Therefore, the present embodiment is characterized in that it does not require an apparatus for vapor deposition of Al and dry etching, etc., and has a smaller number of steps as compared with the conventional method and can be manufactured at low cost. (Second Embodiment) A method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described below with reference to FIGS.
Will be described with reference to. 8A is a plan view of the pad electrode portion, FIG. 8B is a cross-sectional view taken along line CC of FIG. 8A,
9 to 13 are process cross-sectional views.

【００３５】半導体基板上の層間絶縁膜４０に配線溝４
１を形成し、この配線溝４１内にバリアメタル膜４２、
例えば窒化タンタル（ＴａＮ）膜を介してＣｕを主材料
とするＣｕパッド電極部４３ａを有するＣｕ配線層４３
を形成した後、このＣｕ配線層４３を含む前記層間絶縁
膜４０上にＣｕ配線層の酸化を防止するための酸化防止
膜４４、例えば窒化シリコン（ＳｉＮ）膜を成膜する
（図８（ａ）、（ｂ））。A wiring groove 4 is formed in the interlayer insulating film 40 on the semiconductor substrate.
1 is formed, and the barrier metal film 42,
For example, a Cu wiring layer 43 having a Cu pad electrode portion 43a mainly composed of Cu via a tantalum nitride (TaN) film.
Then, an anti-oxidation film 44, for example, a silicon nitride (SiN) film for preventing the oxidation of the Cu wiring layer is formed on the interlayer insulating film 40 including the Cu wiring layer 43 (FIG. 8A). ), (B)).

【００３６】次に、通常のＣＶＤ技術により前記酸化防
止膜４４上の全面に、パッシベーション膜４７、例えば
ＴＥＯＳ膜の単層膜を成膜する（図９）。Next, a passivation film 47, for example, a single layer film of a TEOS film is formed on the entire surface of the antioxidant film 44 by the usual CVD technique (FIG. 9).

【００３７】しかる後、通常のリソグラフィー技術によ
り、レジスト膜４８をマスクにして前記パッド電極部４
３ａ上の前記パッシベーション膜４７部分に第１の開口
部４７ａを形成する（図１０）。ここでは、通常のドラ
イエッチング技術により、前記ＴＥＯＳ膜４７を選択的
に除去する。この際、前記酸化防止膜４４が開口し、前
記パッド電極部４３ａが露出しないようにエッチング時
間をコントロールする。After that, the pad electrode portion 4 is formed by using the resist film 48 as a mask by an ordinary lithography technique.
A first opening 47a is formed in the passivation film 47 portion on 3a (FIG. 10). Here, the TEOS film 47 is selectively removed by a normal dry etching technique. At this time, the etching time is controlled so that the antioxidant film 44 is opened and the pad electrode part 43a is not exposed.

【００３８】次に、前記レジスト膜４８を除去した後
（図１１）、実装時に発生する応力を緩和するための有
機樹脂膜４９、例えば熱硬化性のポリイミド樹脂膜を前
記第１の開口部４７ａの周辺部における前記パッシベー
ション膜４７上に形成する（図１２）。ここでは、まず
前記第１の開口部４７ａを含む前記パッシベーション膜
４７上の全面に感光性ポリイミド樹脂を塗布し、通常の
リソグラフィー技術により、パターニングして前記第１
の開口部４７ａ上にこれよりも広面積の第２の開口部４
９ａを有するポリイミド樹脂膜４９を形成していた後、
ポリイミド樹脂のイミド化を促進させるために、窒素雰
囲気中で３００〜３５０℃の温度でキュアー処理して熱
硬化させる。Next, after removing the resist film 48 (FIG. 11), an organic resin film 49, for example, a thermosetting polyimide resin film, for relieving the stress generated at the time of mounting is applied to the first opening 47a. Is formed on the passivation film 47 in the peripheral portion (FIG. 12). Here, first, a photosensitive polyimide resin is applied to the entire surface of the passivation film 47 including the first opening 47a, and is patterned by an ordinary lithography technique to form the first polyimide film.
The second opening 4 having a larger area than the opening 47a
After forming the polyimide resin film 49 having 9a,
In order to accelerate the imidization of the polyimide resin, it is cured by heat treatment at a temperature of 300 to 350 ° C. in a nitrogen atmosphere and thermally cured.

【００３９】このポリイミド樹脂のキュアー処理時に
は、前記Ｃｕパッド電極部４３ａ表面は、酸化防止膜４
４で覆われているため、酸化されることはない。At the time of curing the polyimide resin, the surface of the Cu pad electrode portion 43a is covered with the anti-oxidation film 4.
As it is covered with 4, it is not oxidized.

【００４０】本実施の形態では、応力緩和用バッファー
材としてポリイミドを挙げたが、半田リフロー時の熱履
歴に耐性のある、例えば、ＢＣＢ等の有機樹脂膜に置き
換えても問題はない。In the present embodiment, polyimide is used as the buffer material for stress relaxation, but there is no problem even if it is replaced with an organic resin film such as BCB which is resistant to the thermal history during solder reflow.

【００４１】次に、このポリイミド樹脂膜４９をマスク
にして、通常のドライエッチング技術により、前記第２
の開口部４９ａ内の前記酸化防止膜４４をエッチング除
去して前記パッド電極部４３ａの一部を露出させる（図
１３）。Next, using the polyimide resin film 49 as a mask, the second dry etching technique is performed by a usual dry etching technique.
The antioxidant film 44 in the opening 49a is removed by etching to expose a part of the pad electrode portion 43a (FIG. 13).

【００４２】最後に、前記第２の開口部４９ａ内のＣｕ
パッド電極部４３ａ、前記パッシベーション膜４７、前
記ポリイミド樹脂膜４９及び前記第２の開口部４９ａ周
辺の前記ポリイミド樹脂膜４９上面部にバリアメタル膜
５０、例えば、Ｐｄ／Ｎｉ／Ｔｉを形成した後、電解メ
ッキ法、又は印刷法等の半田バンプ形成工程を経て前記
Ｃｕパッド電極部４３ａ上に半田ボールバンプ５１が形
成されている半導体装置を製作する（図１４）。Finally, the Cu in the second opening 49a is
After forming a barrier metal film 50, for example, Pd / Ni / Ti on the pad electrode portion 43a, the passivation film 47, the polyimide resin film 49, and the upper surface of the polyimide resin film 49 around the second opening 49a, A semiconductor device having solder ball bumps 51 formed on the Cu pad electrode portions 43a is manufactured through a solder bump forming process such as an electrolytic plating method or a printing method (FIG. 14).

【００４３】この第２の実施の形態では、上記第１の実
施の形態と同様に工程数も少なく、低コストで製造でき
るという特徴がある。The second embodiment is characterized in that it has a small number of steps as in the first embodiment and can be manufactured at low cost.

【００４４】なお、上記実施の形態では、酸化防止膜と
して、ＳｉＮ膜を用いたが、これに限定されず、例えば
ＳｉＣを用いても良い。Although the SiN film is used as the anti-oxidation film in the above embodiment, the present invention is not limited to this, and SiC, for example, may be used.

【００４５】[0045]

【発明の効果】本発明の半導体装置の製造方法によれ
ば、Ａｌの蒸着及びドライエッチング処理装置等を格別
必要とせず、しかも大幅な工程簡略化を図れ、低コスト
化が可能になる。According to the method of manufacturing a semiconductor device of the present invention, it is not necessary to specially provide an apparatus for vapor deposition of Al and a dry etching apparatus, and the process can be greatly simplified and the cost can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の第1の実施の形態に係わる半導体装
置の製造工程を示す図。FIG. 1 is a diagram showing a manufacturing process of a semiconductor device according to a first embodiment of the invention.

【図２】 本発明の第1の実施の形態に係わる半導体装
置の製造工程を示す工程断面図。FIG. 2 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.

【図３】 本発明の第1の実施の形態に係わる半導体装
置の製造工程を示す工程断面図。FIG. 3 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.

【図４】 本発明の第1の実施の形態に係わる半導体装
置の製造工程を示す工程断面図。FIG. 4 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.

【図５】 本発明の第1の実施の形態に係わる半導体装
置の製造工程を示す工程断面図。FIG. 5 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.

【図６】 本発明の第1の実施の形態に係わる半導体装
置の製造工程を示す工程断面図。FIG. 6 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.

【図７】 本発明の第1の実施の形態に係わる半導体装
置の製造工程を示す工程断面図。FIG. 7 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.

【図８】 本発明の第２の実施の形態に係わる半導体装
置の製造工程を示す図。FIG. 8 is a view showing the manufacturing process of the semiconductor device according to the second embodiment of the invention.

【図９】 本発明の第２の実施の形態に係わる半導体装
置の製造工程を示す工程断面図。FIG. 9 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to a second embodiment of the invention.

【図１０】 本発明の第２の実施の形態に係わる半導体
装置の製造工程を示す工程断面図。FIG. 10 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to a second embodiment of the invention.

【図１１】 本発明の第２の実施の形態に係わる半導体
装置の製造工程を示す工程断面図。FIG. 11 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to a second embodiment of the invention.

【図１２】 本発明の第２の実施の形態に係わる半導体
装置の製造工程を示す工程断面図。FIG. 12 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to a second embodiment of the invention.

【図１３】 本発明の第２の実施の形態に係わる半導体
装置の製造工程を示す工程断面図。FIG. 13 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the invention.

【図１４】 本発明の第２の実施の形態に係わる半導体
装置の製造工程を示す工程断面図。FIG. 14 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to a second embodiment of the invention.

【図１５】 従来の半導体装置の製造工程を示す図。FIG. 15 is a view showing a conventional manufacturing process of a semiconductor device.

【図１６】 従来の半導体装置の製造工程を示す工程断
面図。FIG. 16 is a process cross-sectional view showing a manufacturing process of a conventional semiconductor device.

【図１７】 従来の半導体装置の製造工程を示す図。FIG. 17 is a view showing a manufacturing process of a conventional semiconductor device.

【図１８】 従来の半導体装置の製造工程を示す図。FIG. 18 is a diagram showing a conventional manufacturing process of a semiconductor device.

【図１９】 従来の半導体装置の製造工程を示す図。FIG. 19 is a diagram showing a conventional manufacturing process of a semiconductor device.

【図２０】 従来の半導体装置の製造工程を示す図。FIG. 20 is a view showing a conventional manufacturing process of a semiconductor device.

【図２１】 従来の半導体装置の製造工程を示す図。FIG. 21 is a diagram showing a conventional manufacturing process of a semiconductor device.

【図２２】 従来の半導体装置の製造工程を示す図。FIG. 22 is a view showing a conventional manufacturing process of a semiconductor device.

【符号の説明】[Explanation of symbols]

１０、４０、１００、１０５ 層間絶縁膜 １１、４１、１０１ 配線溝 １２、２０、３２、４２、５０、１０２、１１２ バリ
アメタル膜 １３、４３、１０３ Ｃｕ配線層 １３ａ、４３ａ、１０３ａ Ｃｕパッド電極部 １４、４４、１０４ 酸化防止膜（ＳｉＮ膜） １５、１０８ ＴＥＯＳ膜 １６、１０９ ＳｉＮ膜 １７、４７、１１０ パッシベーション膜 １７ａ、４７ａ、１０５ａ 第１の開口部 １８、４８、１０６ レジスト膜 １９、４９、１１１ 有機樹脂膜（ポリイミド樹脂膜） １９ａ、４９ａ、１１１ａ 第２の開口部 ２１、５１、１１３ 半田ボールパンプ10, 40, 100, 105 Interlayer insulating films 11, 41, 101 Wiring grooves 12, 20, 32, 42, 50, 102, 112 Barrier metal films 13, 43, 103 Cu wiring layers 13a, 43a, 103a Cu pad electrode portions 14, 44, 104 Antioxidation film (SiN film) 15, 108 TEOS films 16, 109 SiN films 17, 47, 110 Passivation films 17a, 47a, 105a First openings 18, 48, 106 Resist films 19, 49, 111 organic resin film (polyimide resin film) 19a, 49a, 111a second opening 21, 51, 113 solder ball pump

───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5F033 HH07 HH18 JJ01 JJ07 JJ18 KK11 KK32 MM01 MM12 MM13 NN06 NN07 PP00 PP27 QQ09 QQ10 QQ11 QQ21 QQ25 QQ28 QQ37 QQ74 RR01 RR04 RR06 RR22 RR27 SS04 SS11 SS21 SS22 TT04 XX19 XX20 XX33 XX34    ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F033 HH07 HH18 JJ01 JJ07 JJ18                       KK11 KK32 MM01 MM12 MM13                       NN06 NN07 PP00 PP27 QQ09                       QQ10 QQ11 QQ21 QQ25 QQ28                       QQ37 QQ74 RR01 RR04 RR06                       RR22 RR27 SS04 SS11 SS21                       SS22 TT04 XX19 XX20 XX33                       XX34

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 半導体基板上の層間絶縁膜にＣｕを主材
料とし、パッド電極部を有する埋め込み配線層を形成す
る工程と、 前記埋め込み配線層を含む前記層間絶縁膜上に配線層の
酸化防止膜及びパッシベーション膜を、順次、成膜する
工程と、 前記パッド電極部上の前記パッシベーション膜部に第１
の開口部を設けて前記酸化防止膜の一部を露出させる工
程と、 前記第１の開口部の形成工程後に、前記第１の開口部と
連接する第２の開口部を有する熱硬化型の有機樹脂膜を
前記パッシベーション膜上に形成する工程と、 前記有機樹脂膜を熱硬化させる工程と、 前記有機樹脂膜の熱硬化工程後に、前記第１の開口部内
の前記酸化防止膜をエッチング除去して前記パッド電極
部を露出させる工程と、 前記第１及び第２の開口部を介して前記パッド電極部に
金属バンプを形成する工程とを含むことを特徴とする半
導体装置の製造方法。1. A step of forming an embedded wiring layer having a pad electrode portion with Cu as a main material in an interlayer insulating film on a semiconductor substrate, and an oxidation prevention of the wiring layer on the interlayer insulating film including the embedded wiring layer. A step of sequentially forming a film and a passivation film, and first forming a film on the passivation film part on the pad electrode part.
A step of exposing a part of the anti-oxidation film by providing a second opening, and a thermosetting type having a second opening connected to the first opening after the step of forming the first opening. After the step of forming an organic resin film on the passivation film, the step of thermally curing the organic resin film, and the step of thermally curing the organic resin film, the antioxidant film in the first opening is removed by etching. A step of exposing the pad electrode portion with a metal bump, and a step of forming a metal bump on the pad electrode portion through the first and second openings. 【請求項２】 前記第２の開口部は、前記第１の開口部
より広面積で、且つ前記第１の開口部上にこれと連接し
て設けられてなることを特徴とする請求項１に記載の半
導体装置の製造方法。2. The second opening has a larger area than the first opening, and is provided on the first opening so as to be connected to the first opening. A method of manufacturing a semiconductor device according to item 1. 【請求項３】 前記有機樹脂膜は、ポリイミド樹脂から
なることを特徴とする請求項１または２に記載の半導体
装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the organic resin film is made of a polyimide resin. 【請求項４】 前記配線層の酸化防止膜は、ＳｉＮ膜、
若しくはＳｉＣ膜からなることを特徴とする請求項１に
記載の半導体装置の製造方法。4. The anti-oxidation film of the wiring layer is a SiN film,
Alternatively, the method of manufacturing a semiconductor device according to claim 1, wherein the method comprises a SiC film. 【請求項５】 前記パッシベーション膜がＴＥＯＳ膜の
単層又は下層がＴＥＯＳ膜、上層がＳｉＮ膜、若しくは
ＳｉＣ膜の多層からなることを特徴とする請求項４に記
載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 4, wherein the passivation film is a single layer of a TEOS film, a lower layer is a TEOS film, and an upper layer is a multilayer of a SiN film or a SiC film. 【請求項６】 半導体基板上の層間絶縁膜に形成した配
線溝内にバリアメタル膜を介して、Ｃｕを主材料とし、
パッド電極部を有する埋め込み配線層を形成する工程
と、 前記埋め込み配線層を含む前記層間絶縁膜上にＳｉＮ膜
及びパッシベーション膜を、順次、成膜する工程と、 前記パッド電極部上の前記パッシベーション膜部に第１
の開口部を設けて前記ＳｉＮ膜の一部を露出させる工程
と、 前記第１の開口部の形成工程後に、前記第１の開口部上
にこの第１の開口部より広面積の第２の開口部を有する
熱硬化型のポリイミド樹脂膜を前記パッシベーション膜
上に形成する工程と、 前記ポリイミド樹脂膜を熱硬化させる工程と、 前記ポリイミド樹脂膜の熱硬化工程後に、前記ポリイミ
ド樹脂膜をマスクにして前記第１の開口部内の前記Ｓｉ
Ｎ膜をエッチング除去して前記パッド電極部を露出させ
る工程と、 前記第１及び第２の開口部を介して前記パッド電極部に
バリアメタル膜を介して半田バンプを形成する工程とを
含むことを特徴とする半導体装置の製造方法。6. Cu as a main material, with a barrier metal film interposed in a wiring groove formed in an interlayer insulating film on a semiconductor substrate,
A step of forming a buried wiring layer having a pad electrode portion, a step of sequentially forming a SiN film and a passivation film on the interlayer insulating film including the buried wiring layer, and the passivation film on the pad electrode portion. Part 1
Of the SiN film to expose a part of the SiN film, and after the step of forming the first opening, the second opening having a larger area than the first opening is formed on the first opening. A step of forming a thermosetting polyimide resin film having an opening on the passivation film, a step of thermosetting the polyimide resin film, after the thermosetting step of the polyimide resin film, using the polyimide resin film as a mask The Si in the first opening
A step of exposing the pad electrode portion by removing the N film by etching; and a step of forming a solder bump on the pad electrode portion via a barrier metal film via the first and second openings. A method for manufacturing a semiconductor device, comprising:
JP2002047333A 2002-02-25 2002-02-25 Method for fabricating semiconductor device Pending JP2003249498A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006073891A (en) * 2004-09-03 2006-03-16 Renesas Technology Corp Semiconductor apparatus and method for manufacturing the same
EP2008301A2 (en) * 2006-04-04 2008-12-31 Nternational Business Machines Corporation Method and structure for eliminating aluminum terminal pad material in semiconductor devices
US7491895B2 (en) 2004-05-28 2009-02-17 Sanyo Electric Co., Ltd. Wiring substrate and method of fabricating the same
US7507658B2 (en) 2004-03-29 2009-03-24 Sanyo Electric Co., Ltd. Semiconductor apparatus and method of fabricating the apparatus
WO2016076478A1 (en) * 2014-11-12 2016-05-19 순천향대학교 산학협력단 Hybrid coupler using intentional mismatching
EP4016606A1 (en) * 2020-12-16 2022-06-22 STMicroelectronics Pte Ltd. Passivation layer for an integrated circuit device that provides a moisture and proton barrier

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7507658B2 (en) 2004-03-29 2009-03-24 Sanyo Electric Co., Ltd. Semiconductor apparatus and method of fabricating the apparatus
US7491895B2 (en) 2004-05-28 2009-02-17 Sanyo Electric Co., Ltd. Wiring substrate and method of fabricating the same
JP2006073891A (en) * 2004-09-03 2006-03-16 Renesas Technology Corp Semiconductor apparatus and method for manufacturing the same
EP2008301A2 (en) * 2006-04-04 2008-12-31 Nternational Business Machines Corporation Method and structure for eliminating aluminum terminal pad material in semiconductor devices
EP2008301A4 (en) * 2006-04-04 2012-09-05 Ibm Method and structure for eliminating aluminum terminal pad material in semiconductor devices
WO2016076478A1 (en) * 2014-11-12 2016-05-19 순천향대학교 산학협력단 Hybrid coupler using intentional mismatching
EP4016606A1 (en) * 2020-12-16 2022-06-22 STMicroelectronics Pte Ltd. Passivation layer for an integrated circuit device that provides a moisture and proton barrier

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