JP2003249078A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a leak current at standby in non-selection of a word line can be reduced in write/read operation for static memory cells. <P>SOLUTION: The device is a SRAM, and the memory cell is constituted of PMOS transistors Q1, Q3 and NMOS transistors Q2, Q4 constituting a flip- flop by two pairs of CMOS inverters, the NMOS transistors Q5, Q6 being a transfer gate, and a NMOS transistor Q7 being a switch for reducing a leak current at standby. At standby, the NMOS transistor Q7 is turned off and a current is suppressed, a leak current is reduced. At operation, the NMOS transistor Q7 is turned on, a node potential VSSMC of a low potential is dropped nearly to a ground potential VSS, and speed reduction caused by insertion of the NMOS transistor Q7 is a little. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effectively applied to a semiconductor memory device such as SRAM using a static memory cell.

[0002]

2. Description of the Related Art According to a study made by the present inventor, the following techniques can be considered for a semiconductor memory device using a static memory cell.

For example, in an SRAM as an example of a semiconductor memory device using static memory cells,
A memory cell having a 6-transistor structure is generally used. This memory cell is composed of MOS transistors whose gates and drains are cross-coupled to each other.

As a technique relating to such a semiconductor device as SRAM, for example, 1995 Symp.
osium on VLSI Circuits Di
best of Technical Papers
p25-p26, "Driving Source-L"
ine (DSL) Cell Architecture
e for Sub-1-V High-Speed
Low-Power Applications ", the technique described in Japanese Patent Laid-Open No. 9-51042, and the like.

[0005]

By the way, as a result of the present inventor's examination of the SRAM technology as described above,
The following points became clear.

For example, in the SRAM as described above, a memory cell having a 6-transistor configuration is shown in FIG.
As shown in FIG. 1, a PMOS transistor Q that forms a flip-flop with two CMOS inverters.
1, Q3 and NMOS transistors Q2 and Q4, and two NMOS transistors Q serving as transfer gates
5, Q6 are combined.

In this static memory cell, transfer gate NMOS transistors Q5 and Q6 are connected to a pair of complementary bit lines BL and BR, and a word line W is also provided.
The gate is connected to L and driven by this word line WL. Further, in the static memory cell, the power supply node on the high potential side is connected to the power supply potential VDD, and the power supply node on the low potential side is connected to the ground potential VSS.

In a write / read operation for such a static memory cell, the power supply node on the high potential side of the memory cell is connected to the power supply potential VDD, and the power supply node on the low potential side is connected to the ground potential VSS. Another problem is that the leakage current (standby current) during standby (standby) increases.

Therefore, the present inventor pays attention to the potential of the power supply node on the low potential side of the memory cell, and makes the potential of this power supply node higher than the ground potential, whereby the leakage current at the time of standby can be reduced. Found.

Therefore, it is an object of the present invention to provide a semiconductor device capable of reducing a leak current during standby in a non-selected word line in a write / read operation with respect to a static memory cell.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, in the semiconductor device according to the present invention, a switch is connected between a power supply node on the low potential side of a static memory cell and a reference potential having a MOS transistor whose gate and drain are cross-coupled to each other, and the static memory In a write / read operation for a cell, the switch is controlled to be OFF when the word line is not selected and ON when the word line is selected.

Further, in the above semiconductor device, the switch is composed of an NMOS transistor or an NMOS transistor and a PMOS transistor connected in parallel, and when this switch is turned off, the low potential side of the static memory cell is selected when the word line is not selected. The potential of the power feeding node is set higher than the ground potential. The switch is controlled by the potential of the word line or the potential of the column selection signal line.

Therefore, according to the semiconductor device, by inserting the switch (NMOS transistor or NMOS transistor and PMOS transistor connected in parallel) in series in the static memory cell, the switch is turned off and the current is reduced in the standby mode. Therefore, the leakage current is reduced. As a result, the standby current of the semiconductor device can be reduced. Further, the switch is turned on during operation, and the power supply node on the low potential side is lowered to near the ground potential, so that the speed reduction due to the insertion of the switch is suppressed.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, the same members are designated by the same reference numerals, and the repeated description thereof will be omitted.

(First Embodiment) A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.

First, referring to FIG. 1, a first embodiment of the present invention will be described.
An example of the configuration of the memory cell in the semiconductor device will be described. FIG. 1 is a circuit diagram showing a memory cell in the semiconductor device of this embodiment.

The semiconductor device of this embodiment is, for example, an SRAM using a static memory cell, and this memory cell has a 7-transistor configuration, and two sets of CMOs are used.
PMO that forms a flip-flop with an S inverter
S transistors Q1 and Q3, NMOS transistors Q2 and Q4, and two NMOs serving as transfer gates.
It is composed of S-transistors Q5 and Q6, and an NMOS transistor Q7 which is a switch for reducing a leak current in standby.

PMOS transistors Q1, Q3 and N
The MOS transistors Q2 and Q4 are flip-flops in which a CMOS inverter including a PMOS transistor Q1 and an NMOS transistor Q2 and a CMOS inverter including a PMOS transistor Q3 and an NMOS transistor Q4 are combined, and the gates and drains thereof are cross-coupled to each other. Also, the PMOS transistor Q
The sources of 1 and Q3 are at power supply potential VDD, and the sources of NMOS transistors Q2 and Q4 (potential VSSMC) are at NMO.
Each of them is connected to the S transistor Q7.

The drains of the NMOS transistors Q5 and Q6 are connected to the drain of the PMOS transistor Q1 and the NMOS transistor Q2, respectively, and the PMOS.
The drain is connected to the commonly connected drains of the transistor Q3 and the NMOS transistor Q4, and the source is connected to the bit line pair BL and BR having a complementary relationship. Also, NMOS
The gates of the transistors Q5 and Q6 are connected to the word line WL and serve as a transfer gate driven by the potential of the word line WL.

The NMOS transistor Q7 has a drain connected to a commonly connected source (potential VSSMC) of the NMOS transistors Q2 and Q4, and a source connected to the ground potential V.
It is connected to SS. Also, the NMOS transistor Q
The gate of 7 is connected to the control line WN, and is used as a switch for reducing the leak current during standby, which is driven by the potential of the control line WN.

Next, an example of the structure of the memory cell array in the semiconductor device of this embodiment will be described with reference to FIG. FIG. 2 is a block diagram showing a memory cell array.

The memory cell array of the present embodiment is arranged in a grid pattern (row direction = m pieces, column direction = n pieces), and has word lines WL0 to WLn and bit line pairs BL0 to BLm, BR0.
To BRm, a plurality of memory cells MC00 to M connected to
Cnm and the memory cells MC00 to MCnm arranged in the column direction, and bit line pairs BL0 to BLm, BR0 to BR.
The column selection circuits YS0 to YSm connected to m, the sense amplifier SA commonly connected to the column selection circuits YS0 to YSm, and the like.

Although not shown, a row decoder driver and a column decoder driver are connected to the memory cell array in the row direction and the column decoder driver in the column direction, respectively, and an arbitrary memory cell MC is selected by these decoder drivers. . In the read operation for the selected memory cell MC, the data in the selected memory cell MC is transferred to the column selection circuit YS and the sense amplifier S through the bit line pair BL and BR.
It is read from an output circuit (not shown) via A. In the write operation, data from a write circuit (not shown) is written to the selected memory cell through the column selection circuit YS and the bit line pair BL and BR.

In this memory cell array, a plurality of memory cells MC00 to MCnm are arranged in the memory cells MC00 to MC0m, MC10 to MC1m ,.
.., MCn0 to MCnm are commonly connected to the above-described NMOS transistors Q7 for reducing the leak current during standby. This NMOS transistor Q
The gates of 7 are word lines WL0, WL1, ...
., WLn, respectively, and driven by the potential of the word line WL.

Next, one example of the simulation result of the memory cell in the semiconductor device of the present embodiment will be described in order with reference to FIGS.

FIG. 3 shows a simulation result of a leak current of a memory cell, (a) is a technique of the present invention, and (b) is a technique.
Shows the prerequisite technology (FIG. 16) of the present invention.

Here, the simulation conditions are: upper limit temperature Tj = 110 ° C., threshold voltage VTHN = 0.2V of NMOS transistor, gate width Wg = 1.0 μm, power supply potential VDD = 1.2V, ground. Potential V
SS = 0V, potential VWL = 0 when word line WL is not selected
V, potential VBL, VBR of bit line pair BL, BR = 1.
2V, the control potential VWN of the control line WN of the NMOS transistor Q7 is set to 0V.

Further, the currents flowing through the respective MOS transistors are complementary in the left and right CMOS inverters, so that the left CMOS inverter is H level, for example.
/ L and the CMOS inverter on the right side also show the current values in the case of L / H.

According to the technique of the present invention, as shown in FIG. 3A, the low potential side node potential VSS of the memory cell MC.
MC is higher than 0V of ground potential VSS 244 / 244m
V, and the leak current Ile of the memory cell MC
The ak is 17.0 / 17.0 pA. On the contrary,
In the base technology of the present invention, as shown in FIG. 3B, the low potential side node potential of the memory cell MC is the ground potential V.
The SS becomes about 0 V, and the leak current Ileak of the memory cell MC becomes 87.3 / 86.1 pA. From this simulation result, the technique of the present invention increases the low potential side node potential VSSMC of the memory cell MC,
It can be confirmed that the leak current Ileak of the memory cell MC can be reduced to about 1/5.

FIG. 4 shows a simulation result of the threshold voltage dependency of the leak current of the memory cell (the technique of the present invention and the prerequisite technique of the present invention).

In the technique of the present invention, the threshold voltage V
As THN is increased from -0.2V to 0.3V, the leak current Ileak decreases from about 87 pA to about 6 pA. On the other hand, in the base technology of the present invention, the threshold voltage VTHN is changed from -0.2 V to 0.
Even if it is increased to 3V, the leak current Ileak is 87p
It becomes constant at about A. From this simulation result,
The technique of the present invention is more suitable for the threshold voltage V of the memory cell MC.
It can be confirmed that the leak current Ileak can be reduced as the THN is increased. For example, the threshold voltage V
About 19% at THN = 0.2V, 6.2 at 0.3V
%, The leak current Ileak can be reduced.

FIG. 5 shows a simulation result of the threshold voltage dependence of the node potential on the low potential side of the memory cell (technology of the present invention).

In the technique of the present invention, the threshold voltage V
When THN is -0.2V to 0V, the low potential side node potential VSSMC is constant at about 0 mV, and the threshold voltage V
As THN is increased from 0.1 V to 0.3 V, the low potential side node potential VSSMC rapidly increases from about 40 mV to about 500 mV. On the contrary,
In the base technology of the present invention, although not shown, it becomes constant at about 0 V of the ground potential. From this simulation result, it can be confirmed that the technique of the present invention can increase the low-potential-side node potential VSSMC of the memory cell MC.

6A and 6B show simulation results of static noise margin (word line ON), in which (a) shows the technique of the present invention and (b) shows the premise technique of the present invention.

The bistability in the memory cell MC depends on how the input / output characteristics of the two CMOS inverters intersect. In order to increase this stability, it is necessary to make the ratio of the driving forces of the two CMOS inverters as large as possible.

In the technique of the present invention, the word line is turned on,
That is, the static noise margin when the word line WL is selected is about 203 mV. On the other hand, also in the base technology of the present invention, the static noise margin when the word line WL is selected is about 203 mV. From this simulation result, it can be confirmed that the technique of the present invention can secure the same degree of static noise margin when the word line WL is selected.

7A and 7B show simulation results of static noise margin (word line off). FIG. 7A shows the technique of the present invention, and FIG. 7B shows the prerequisite technique of the present invention.

In the technique of the present invention, the word line is turned off,
That is, the static noise margin when the word line WL is not selected is about 130 mV. On the other hand, in the base technology of the present invention, the static noise margin when the word line WL is not selected is 454 mV. From this simulation result, it can be confirmed that the technique of the present invention cannot secure a sufficient static noise margin when the word line WL is not selected.

FIG. 8 shows a simulation result of the threshold voltage dependence of the static noise margin (word line off) (the technique of the present invention and the prerequisite technique of the present invention).

In the technique of the present invention, the threshold voltage V
As THN is increased from -0.2V to 0.3V, the static noise margin SNM decreases from about 360mV to about 90mV. On the other hand, in the base technology of the present invention, the threshold voltage VTHN is-
Even if the voltage is increased from 0.2 V to 0.3 V, the static noise margin SNM remains constant at about 460 mV.
From this simulation result, it can be confirmed that the technique of the present invention cannot secure a sufficient static noise margin SNM as the threshold voltage VTHN of the memory cell MC is increased.

FIG. 9 shows a simulation result of the threshold voltage dependency of the cell current (word line ON) of the memory cell (the technique of the present invention and the prerequisite technique of the present invention).

The speed of the memory cell MC depends on the parameter of the cell current Icell. This cell current Ic
If the value of ell is large, the speed will be fast, and if it is small, the speed will be slow.

In the technique of the present invention, the threshold voltage V
As THN is increased from -0.2 V to 0.3 V, the cell current Icell decreases from about 48 μA to about 33 μA. On the other hand, in the base technology of the present invention, the threshold voltage VTHN is changed from -0.2 V to 0.
Even if it is increased to 3V, the cell current Icell is 52 μA.
It becomes constant with the degree. From the simulation result, according to the technique of the present invention, the threshold voltage VTH of the memory cell MC is
It can be confirmed that the cell current Icell cannot be sufficiently secured as N is increased. For example, when the threshold voltage VTHN = 0.2V, it is about 82%, and at 0.3V, 65%.
The cell current Icell is reduced to about%.

Next, referring to FIG. 10, an example of the timing of the write / read operation for the memory cell in the semiconductor device of this embodiment will be described in order. Figure 10
The timings of the write / read operations with respect to the memory cells are shown, (a) shows the technique of the present invention, and (b) shows the premise technique (FIG. 16) of the present invention.

In the technique of the present invention, as shown in FIG. 10A, the word line W is used during the read (write) operation.
A predetermined potential VWL at the time of selection is applied to L, and N
A prescribed control potential VWN is applied to MOS transistor Q7. The NMOS transistor Q7 has a predetermined control potential V
When WN is applied, it is turned on, and the low potential side node potential VSSMC of the memory cell MC is 0 V of the ground potential VSS.
It drops to near. Therefore, the speed decrease at the time of selecting the word line WL in the read (write) operation can be reduced.

In the standby mode, the non-selected potential VWL = 0V is applied to the word line WL, and NMO is applied.
The control potential VWN = 0V is applied to the S transistor Q7. The NMOS transistor Q7 is turned off when 0 V is applied, and the low potential side node potential VSSMC of the memory cell MC is higher than the ground potential VSS = 244 m.
Rise to about V. As a result, the cell current is 17p
It can be reduced to about A.

On the other hand, in the precondition technique of the present invention, as shown in FIG.
At the time of operation, the low-potential-side node potential of the memory cell MC drops to near 0 V of the ground potential VSS, so the speed decrease is small. In the standby mode, the low-potential-side node potential VSSMC of the memory cell MC drops to near 0 V of the ground potential VSS, which causes a problem that the cell current increases to about 87 pA.

Therefore, according to the present embodiment, by inserting the NMOS transistor Q7 in series with the memory cell MC, the NMOS transistor Q7 is in standby.
Is turned off, the current is reduced, and the leak current is reduced. This is the NM in which the leak current of the memory cell MC is inserted in series.
This is because it is narrowed down by the OS transistor Q7. Further, during operation, the NMOS transistor Q7 is turned on, and the low-potential-side node potential VSSMC drops to near the ground potential VSS, so the speed reduction due to the insertion of the NMOS transistor Q7 is small.

(Second Embodiment) A semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 11 and 12.

First, an example of the structure of the memory cell in the semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. FIG. 11 is a circuit diagram showing a memory cell in the semiconductor device of this embodiment.

The semiconductor device of the present embodiment is an SRAM using, for example, a static memory cell as in the first embodiment, and the difference from the first embodiment is that
Switch for reducing leakage current during standby is
The point is that the static noise margin is improved instead of the NMOS transistor and the PMOS transistor connected in parallel from the S transistor.

That is, in the present embodiment, the memory cell MC has PMOS transistors Q1 and Q3 which form a flip-flop by two sets of CMOS inverters.
And the NMOS transistors Q2 and Q4, and two NMOS transistors Q5 and Q6 serving as transfer gates.
And an NMOS transistor Q7 and a PMOS transistor Q8, which are switches for reducing the leak current during standby.

NMOS transistor Q7 and PMOS
The transistor Q8 has a commonly connected drain NMO.
The S transistors Q2 and Q4 are connected to the commonly connected sources (potential VSSMC), and the commonly connected sources are connected to the ground potential VSS. The gates of the NMOS transistor Q7 and the PMOS transistor Q8 are commonly connected to the control line WL and driven by the potential of the control line WL.

Next, referring to FIGS. 11 and 12, one example of the simulation result of the memory cell in the semiconductor device of the present embodiment will be described in order.

FIG. 11 shows the simulation result of the leak current of the memory cell. Here, the simulation conditions are: upper limit temperature Tj = 110 ° C., threshold voltage VTHN = 0.2V of NMOS transistor, threshold voltage VTHP = −0.2V of PMOS transistor, gate width Wg = 1.0 μm. At each potential VDD, VS
S, VWL, VBL, VBR, VWL (control line W of NMOS transistor Q7 and PMOS transistor Q8
The control potential of L) is set similarly to the first embodiment.

As shown in FIG. 11, the low potential side node potential VSSMC of the memory cell MC becomes about 136 mV higher than 0 V of the ground potential VSS, and the leak current Ileak of the memory cell MC is 33.6 pA (IleakN = 1).
2.8pA + IleakP = 20.8pA). From this simulation result, in the present embodiment, the low potential side node potential VSSMC of the memory cell MC becomes lower than that of the first embodiment, and the memory cell M
Although the leak current Ileak of C is increased, it can be reduced to about 35% as compared with the base technology of the present invention.

FIG. 12 shows a simulation result of static noise margin (word line off). Figure 1
2, the word line is off, that is, the word line WL
327mV static noise margin when is not selected
It will be about. From this simulation result, in the present embodiment, the static noise margin when the word line WL is not selected can be increased as compared with the first embodiment.

Therefore, according to the present embodiment, the NMOS transistor Q connected in series in parallel with the memory cell MC.
By inserting 7 and PMOS transistor Q8,
Similar to the first embodiment, the current is throttled in the standby mode to reduce the leak current, and the speed reduction can be reduced during the operation. In particular, the static noise margin can be improved as compared with the first embodiment.

(Third Embodiment) A semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS.

In the present embodiment, an example will be described in which the insertion position of the switch for reducing the leakage current during standby is changed. 13 to 15 are block diagrams showing the main part of the memory cell array.

In the memory cell array shown in FIG. 13, the memory cells MC connected to the word lines WL in the row direction are divided, and the divided memory cells MC are commonly used in block units to reduce the leakage current at the standby time. NMOS transistors Q7 are connected one by one.
Here, two memory cells MC00 and M are provided in the row direction.
An example of division is shown as C01. This N
The MOS transistors Q7 are connected to the word lines WL and driven by the potential of the word lines WL.

In the memory cell array shown in FIG. 14, memory cells MC in the row direction and memory cells MC in the column direction.
Are divided, and the above-mentioned divided NMOS cells Q7 are connected in common to each block unit of the divided memory cells MC for reducing the leak current at the time of standby. Here, six rows each (2 ×
3) Memory cells MC00, MC01, MC10 and MC
11 shows an example of division such as 11, MC20, and MC21. The NMOS transistor Q7 has a word line WL and a column selection signal line YSEL via an OR gate OR.
Respectively connected to the word line WL and the column selection signal line YS.
It is driven by the potential of EL.

In the memory cell array shown in FIG. 15, memory cells MC in the column direction are divided, and the above-mentioned NMOS transistor Q7 for reducing the leak current at the time of standby is commonly used in each block of the divided memory cells MC. They are connected one by one. Here, n in the column direction
An example is shown in which the memory cells are divided into memory cells MC00 to MCn0. This NMOS transistor Q
7 are respectively connected to the column selection signal line YSEL and driven by the potential of the column selection signal line YSEL.

Therefore, according to the present embodiment, as in the case of the first embodiment, the leakage current is reduced by squeezing the current during the standby, and the speed decrease is reduced during the operation, and the area of the memory array is increased. It is possible to optimize the reduction of the leak current, the suppression of the speed decrease, and the suppression of the increase of the memory array area while considering the relationship of

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, in the above-described embodiment, the case where the present invention is applied to the SRAM using the static memory cell has been described as an example, but the present invention is not limited to this.
The present invention can be applied to a memory LSI having memory cells of MOS structure, and can also be applied to a logic LSI with a built-in memory.

[0069]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1) A switch (NMOS transistor or NM connected in parallel) between a power supply node on the low potential side of the static memory cell and a reference potential (ground potential).
OS transistor and PMOS transistor) are connected,
By controlling the switch to be OFF when the word line is not selected in the write / read operation for the static memory cell, the standby current when the word line is not selected can be narrowed, so that the leak current can be reduced. It will be possible.

(2) In the above (1), in the write / read operation for the static memory cell,
By controlling the switch to ON when selecting the word line,
Since the power supply node on the low potential side of the memory cell can be lowered to near the ground potential during the operation of selecting the word line, it is possible to suppress the speed reduction due to the connection of the switch.

(3) In (1) above, by devising the connection of the switch to the static memory cell,
It is possible to optimize the reduction of the leak current, the suppression of the speed decrease, and the suppression of the increase in the memory array area.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a memory cell in a semiconductor device according to a first embodiment of the present invention.

FIG. 2 shows a semiconductor device according to the first embodiment of the present invention,
It is a block diagram which shows a memory cell array.

3A and 3B are characteristic diagrams showing simulation results of a leak current of a memory cell in the semiconductor device according to the first embodiment of the present invention.

FIG. 4 shows a semiconductor device according to the first embodiment of the present invention,
It is a characteristic view which shows the simulation result of the threshold voltage dependence of the leak current of a memory cell.

FIG. 5 shows a semiconductor device according to the first embodiment of the present invention,
It is a characteristic view which shows the simulation result of the threshold voltage dependence of the low electric potential side node electric potential of a memory cell.

6A and 6B are characteristic diagrams showing simulation results of static noise margin (word line on) in the semiconductor device according to the first embodiment of the present invention.

7A and 7B are characteristic diagrams showing simulation results of static noise margin (word line off) in the semiconductor device of the first embodiment of the present invention.

FIG. 8 shows a semiconductor device according to the first embodiment of the present invention,
It is a characteristic view which shows the simulation result of the threshold voltage dependence of static noise margin (word line OFF).

FIG. 9 is a semiconductor device according to the first embodiment of the present invention,
It is a characteristic view which shows the simulation result of the threshold voltage dependence of the cell current (word line ON) of a memory cell.

10A and 10B are timing charts showing the timing of the write / read operation with respect to the memory cell in the semiconductor device according to the first embodiment of the present invention.

FIG. 11 is a circuit diagram showing a memory cell in a semiconductor device according to a second embodiment of the present invention.

FIG. 12 is a characteristic diagram showing a simulation result of static noise margin (word line off) in the semiconductor device according to the second embodiment of the present invention.

FIG. 13 is a block diagram showing a main part of a memory cell array in a semiconductor device according to a third embodiment of the present invention.

FIG. 14 is a block diagram showing a main part of another memory cell array in the semiconductor device according to the third embodiment of the present invention.

FIG. 15 is a block diagram showing a main part of still another memory cell array in the semiconductor device according to the third embodiment of the present invention.

FIG. 16 is a circuit diagram showing a memory cell in a semiconductor device examined as a premise of the present invention.

[Explanation of symbols]

Q1, Q3, Q8 PMOS transistor Q2, Q4, Q5, Q6, Q7 NMOS transistors WL word line BL, BR bit line pair MC memory cell YS column selection circuit SA sense amplifier

Claims (5)

[Claims] 1. A static memory cell having a MOS transistor whose gate and drain are cross-coupled to each other, a word line and a data line pair connected to the static memory cell, and a power supply node on the low potential side of the static memory cell. And a switch connected between a static potential and a reference potential, and in a write / read operation for the static memory cell, the switch is turned off when the word line is not selected, and the switch is selected when the word line is selected. A semiconductor device characterized by controlling ON. 2. The semiconductor device according to claim 1, wherein the switch is formed of an NMOS transistor, the switch is turned off, and when the word line is not selected, a power supply node on a low potential side of the static memory cell is formed. A semiconductor device having a potential higher than a ground potential. 3. The semiconductor device according to claim 1, wherein the switch comprises an NMOS transistor and a PMOS transistor connected in parallel, the switch is turned off, and the static memory cell of the static memory cell is turned off when the word line is not selected. A semiconductor device characterized in that a potential of a power supply node on a low potential side is set to a potential higher than a ground potential. 4. The semiconductor device according to claim 2, wherein the switch is controlled by the potential of the word line. 5. The semiconductor device according to claim 2, wherein the switch is controlled by the potential of a column selection signal line.