JP2003242046A - Information processor, and operational method and program for information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor which can prevent any operational abnormality caused by a physical abnormality of a semiconductor storage means without changing any hardware configuration, and improve the reliability. <P>SOLUTION: In a microcomputer as an information processor, a storage RAM area 5a to save the data to be continuously used even after the resetting is provided in a RAM area 5, a CPU 1 performs the memory check to the RAM area 5 including the storage RAM area 5a, and uses the data present in the storage RAM area 5a in the normal processing operation only when the result of the memory check is excellent. An empty area 7a which is a migration area for migrating the data in the storage RAM area 5a during the memory check is provided in a general register area 7. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, an operation method of the information processing apparatus, and a program, and more particularly to an in-vehicle information processing apparatus and its related technology.

[0002]

2. Description of the Related Art As a prior art related to the present invention, when an information processing device starts an operation after reset, a code check is performed on the data in its RAM, and when the result of the code check is good, Some data are designed to be used for normal operation after the start of operation.

[0003]

However, although an abnormality in the data itself can be found by the code check, the RA
If a physical abnormality has occurred in M itself, the abnormality cannot be detected, and incorrect data may be used at the start of operation after reset, resulting in a problem of low reliability. For example, if the RAM is in an unwritable state due to an abnormality and the reset is performed in a state where the RAM data update is not properly executed, the data stored in the RAM itself is not updated properly and is normal. Therefore, no abnormalities are detected in the code check,
At the start of the operation after the reset, an erroneous processing operation is performed based on the data that has not been properly updated.

In view of the above problems, the present invention provides an information processing apparatus capable of preventing an operational abnormality due to a physical abnormality of a semiconductor memory means without changing the hardware configuration and improving reliability. The purpose is to provide.

[0005]

[Means for Solving the Problems] The technical means for achieving the above-mentioned object are a first semiconductor memory means in which a program and operation data are recorded, and a second semiconductor memory means capable of rewriting the memory content. And an arithmetic processing unit that operates based on the program and the operation data, the arithmetic processing unit storing data in the second semiconductor storage unit with respect to input contents from the outside in its normal processing operation. In an information processing device that performs information processing while using it as a place and outputs the processing result to the outside, the arithmetic processing means, when starting operation after reset, performs the normal processing operation in the second semiconductor storage means. After writing data and reading the data to the storage area used for, the contents of the read data and
A memory check is performed to determine whether the contents of the written data match, and only when the result of the memory check is good, the data existing in the storage area is reset to the normal state after the reset. It is characterized by being used for processing operation.

Preferably, the second semiconductor memory means has a data storage area in which data to be left without being erased at the time of reset is stored, and a save area provided for saving the storage contents of the data storage area. , A normal storage area is provided, and the arithmetic processing means stores the data stored in the second semiconductor storage means at the time of the normal processing operation as the data to be left without being erased at reset. Save in both the save area and the normal storage area or in the data save area, and perform processing operations while saving in the normal storage area for data that does not need to be retained at reset, at the start of operation after the reset, Data in the data storage area is saved to the save area, the memory check is performed on the data save area, and Only if the result of the memory check is good, it is preferable to use the data that is saved in the save area in the normal processing operation after the reset back to the data storage area.

Preferably, the arithmetic processing means is
Before saving the data in the data storage area at the start of the operation after the reset to the save area, the memory check is performed on the save area, and only when the result of the memory check is good, It is preferable that the data in the data saving area is saved in the saving area and the memory check is performed on the data saving area.

Further, preferably, the second semiconductor storage means comprises a RAM and a register, the data storage area and the normal storage area are provided in the RAM, and the save area is provided in the register. Is good.

Further, preferably, the second semiconductor storage means comprises a RAM, and the data storage area, the save area and the normal storage area are provided in the RAM.

Further, the technical means for achieving the above-mentioned object is a first semiconductor memory means in which a program and operation data are recorded, a second semiconductor memory means capable of rewriting the memory content, and the program. And an arithmetic processing unit that operates based on the operation data, wherein the arithmetic processing unit uses the second semiconductor storage unit as a data storage location for input contents from the outside in its normal processing operation. In the operation method of the information processing apparatus for performing information processing while outputting information to the outside, the arithmetic processing means is configured to perform the normal processing operation in the second semiconductor memory means at the start of operation after reset. After writing data to and reading data from the storage area to be used, the contents of the read data and the written data Memory check to determine whether or not the contents of the data match, and only when the results of both memory checks are good, the data existing in the storage area is reset to the normal data after the reset. It is characterized in that it is used for processing operation.

The technical means for achieving the above-mentioned object are a first semiconductor memory means in which a program and operation data are recorded, a second semiconductor memory means in which the memory content can be rewritten, and the program. And an arithmetic processing unit that operates based on the operation data, wherein the arithmetic processing unit uses the second semiconductor storage unit as a data storage location for input contents from the outside in its normal processing operation. In the program of the information processing device for performing information processing while outputting the processing result to the outside, the arithmetic processing means is used for the normal processing operation in the second semiconductor memory means at the start of operation after reset. Data is written to and read from the storage area to be read, and the contents of the read data and the written data are written. Memory check to determine whether or not the contents of the data match, and only when the results of both memory checks are good, the data existing in the storage area is reset to the normal data after the reset. It is characterized in that it is used for processing operation.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment> FIG. 1 is a block diagram of a microcomputer which is an information processing apparatus according to a first embodiment of the present invention. This microcomputer is a vehicle-mounted one-chip microcomputer, and as shown in FIG. 1, a CPU (arithmetic processing unit) 1 and a ROM area (first semiconductor) in which a program and operation data for the operation of the CPU 1 are recorded. The storage unit 3 includes a RAM area (RAM) 5 and a general-purpose register area (register) 7. The RAM area 5 and the register area 7 correspond to the second semiconductor memory means according to the present invention.

In this embodiment, the RAM area 5 is provided with a dedicated storage RAM area (data storage area) 5a for storing data that is continuously used even after the microcomputer is reset. There is. An area other than the storage RAM area 5a in the RAM area 5 is a normal RAM area (normal storage area) 5b used for normal data storage. The storage RAM area 5a and the normal RAM area 5b have the same physical configuration and function, and the CPU 1
The application is only defined by the setting of. RAM
Area 5 is a storage RAM area 5 when the microcomputer is powered off.
A backup function (backup power supply, etc.) for holding the data in a may be provided, or the RAM may be a nonvolatile memory whose rewritable content is rewritable.
Region 5 may be configured.

Further, in the register area 7, there is set a dedicated free area (a save area) 7a for saving the data in the storage RAM area 5a at the time of a memory check which will be described later. Areas of the register area 7 other than the empty area 7a are the normal register area 7 used for normal data storage.
It is b. The free area 7a and the normal register area 7b have the same physical configuration and function, and the CPU 1
The application is only defined by the setting of.

The CPU 1 operates on the basis of the program and operation data stored in the ROM area 3, so that in the normal processing operation, the normal register area of the RAM area 5 and the register area 7 with respect to the contents input from the outside. Information processing is performed using 7b as a data storage location, and the processing results are output to the outside to control various in-vehicle devices.

A microcomputer (particularly C
The operation of PU1) will be described. Steps S1 to S of steps S0 to S11 included in the flowchart of FIG.
The process of 9 is after the first reset process (step S0) or the second reset process (step S11),
It is executed before the normal processing operation of the microcomputer (step S10) is started.

The first reset process in step S0 is a process for starting the microcomputer, which is performed when the power is turned on due to a momentary power failure of the microcomputer, and includes, for example, reading a program from the ROM area 3. The second reset process in step S11 is the operation of the microcomputer (step S1
This is a process for restarting the microcomputer, which is interrupted in response to a command from the outside (or spontaneously) during the normal processing operation of 0), and stops the operation of the microcomputer and the subsequent ROM area 3 Includes reading of the program of.

In addition, in the normal processing operation performed in step S10, the CPU 1 normally processes, among the data stored in the RAM area 5, data that should be left without being erased at reset (data that should be continuously used after reset). RAM
The data is saved in the area 5b and also in the storage RAM area 5a. In this embodiment, of the data stored in the normal RAM area 5b, the data to be continuously used is regularly encoded and stored in the storage RAM area 5a. Of the data stored in the RAM area 5, the data that may be erased at reset is the normal RAM area 5b.
Only stored in.

Here, the data is encoded and stored in the storage RAM.
The reason for saving in the area 5a is as follows. That is, when saving data in the normal RAM area 5a,
Although simple data such as 1, 0 corresponding to ON / OFF of the controlled object is stored for effective use of the storage area, the reliability is low with this simple data. Therefore, when the data is stored in the storage RAM area 5a, it is encoded by a predetermined code to improve reliability.

In this embodiment, the data to be continuously used is stored in both the normal RAM area 5b and the storage RAM area 5a, but it may be stored only in the storage RAM area 5a.

Then, a first reset process (step S0) that is performed when the power is turned on due to a momentary power failure of the microcomputer, or an interrupting operation in response to a command from the outside (or spontaneously) during a normal processing operation of the microcomputer. When the second reset process (step S11) performed in step S11 is performed, the process proceeds to step S1, and processes such as the memory check according to the present embodiment are performed.

In step S1, the data stored in the storage RAM area 5a to be continuously used is saved in the free area 7a. In addition, in step S1, a memory check is performed on the register area 7 prior to the data saving processing. This memory check is to write the data (arbitrary data) to the memory area to be checked (here, the register area 7) and read the data, and then the content of the read data and the content of the written data. Is a process for determining whether or not and, if the write data and the read data match, it is determined that the memory area is normal, and if they do not match, the memory area is physically It is judged that there is a physical abnormality.

In subsequent steps S2 to S5, a memory check is performed on the RAM area 5. That is, first, data (arbitrary data) is written to the RAM area 5 (step S2), and the written data is R
Data read from the AM area 5 (step S3), written data (data value) and read data (data value)
Is determined (step S4). If they match, the process proceeds to step S5. It is determined whether the memory check of all RAM areas 5 is completed. The process of steps S2 to S5 is repeated until completion, and the memory check of all RAM areas 5 is performed. Only when the result of the memory check is good for all RAM areas 5, the process proceeds to step S7 The data to be continuously used, which has been saved in 7a, is restored in the storage RAM area 5a, and the process proceeds to step S8.

If it is determined in step S4 that the written data and the read data do not match, there is a possibility that there is a physical abnormality in the RAM area 5 and the data is saved in the storage RAM area 5a. Since the data that has been processed is in an untrustworthy state, the process proceeds to step S6 and error processing is performed. In this error processing, various contents can be considered, and the following processing contents can be considered by listing some of them.

A first specific example is a method in which all the functions of the microcomputer 1 are stopped and the power is turned off, and then the power is turned on in response to a reset command input from an external monitoring IC to restart the microcomputer. Conceivable. In this case, the memory R
The data stored in the AM area 5a is erased before the power is turned off for error processing or when the microcomputer is restarted after the power is turned on. As a second specific example, there is a method of spontaneously resetting by the operation of the program of the microcomputer 1 (at that time, the contents of the storage RAM area 5a are also erased) and then restarting. In addition, RA
You may make it perform the process which makes the part in which the physical abnormality generate | occur | produced in the M area | region 5 unusable.

In step S8, various code checks (determination as to whether or not the pattern is a specific pattern, sum check, CRC check, etc.) are performed on the data returned to the storage RAM area 5a, and the data is found to be abnormal by the code check. If not found, the process proceeds to step S10, and the data coded and stored in the storage RAM area 5a is converted into normal data and written in the corresponding normal RAM area 5b for normal processing. Used.

The judgment of whether or not the pattern is a specific pattern in the code check is a check of whether or not the data stored in the storage RAM area 5a conforms to the code format for storage.

As a result of the code check in step S8,
If an abnormality is found in the data, the restoration processing is performed on the broken data among the data stored in the storage RAM area 5a in step S9, and then in step S9.
Proceed to 10 and the memory R normalized by the restoration process
The data in the AM area 5a is converted into normal data,
It is written in the corresponding normal RAM area 5b and used for normal processing.

As described above, according to this embodiment, the RAM area 5 is provided with the storage RAM area 5a for storing the data to be continuously used even after the reset, and the CPU 1
At the start of operation after reset, the storage RAM area 5a
Since the memory check is performed on the RAM area 5 including, and the data existing in the storage RAM area 5a is used for the normal processing operation only when the result of the memory check is good, By changing the operation program of the CPU 1 without changing the hardware configuration, it is possible to prevent the operation abnormality caused by using the incorrect data due to the physical abnormality of the RAM area 5, and improve the reliability. Can be achieved.

At the start of the operation after reset, the memory R
It is possible to continue the processing operation using the data before reset, which is stored in the AM area 5a and whose reliability is guaranteed, as it is.

Further, since the storage RAM area 5a for storing the data which is continuously used even after the reset is provided, no extra processing such as searching for a storage destination when the data to be stored is stored is required. Therefore, the efficiency of the program can be improved.

Further, since the empty area 7a, which is a dedicated save area for saving the data in the storage RAM area 5a, is provided, there is no need for extra processing such as searching for a save destination when saving the data, The program and operation can be simplified.

Further, before saving the data in the storage RAM area 5a to the empty area 7a, a memory check is also performed on the register area 7 including the empty area 7a. It is possible to prevent the occurrence of a defect in the data due to a physical abnormality in the empty area 7a when saving the data, and it is possible to further improve the reliability of the data in the storage RAM area 5a.

In general, when performing a memory check on the RAM (RAM area 5), it is necessary to secure a use area for program execution on the RAM, so that the execution area of the program on the RAM is switched. While it is necessary to perform the memory check of the entire RAM several times, the memory check for the register (register area 7) can be executed for the entire register at once without switching the execution area of the program on the RAM. it can. Therefore, by providing the empty area 7a which is the save area in the register area 7, it is possible to easily perform the memory check of the register area 7 before saving the data from the storage RAM area 5a to the empty area 7a. There is.

<Second Embodiment> FIG. 3 is a block diagram of a microcomputer which is an information processing apparatus according to a second embodiment of the present invention. The microcomputer according to the present embodiment is substantially different from the microcomputer according to the first embodiment described above in that the save area according to the present invention is provided in the RAM area 5 as a save RAM area 5c instead of the register 7. Only the points and the points in which the processing operations related thereto have been changed, the portions corresponding to each other are designated by the same reference numerals, and the description thereof will be omitted.

In this embodiment, the RAM area 5 is provided with a save RAM area 5c which is a save area.
An area other than the storage RAM area 5a and the save RAM area 5c in the area 5 is a normal RAM area 5b.
The entire register area 7 is the normal register area 7b.
Has become.

A microcomputer (particularly C
The operation of PU1) will be described. Step S21 of steps S20 to S36 included in the flowchart of FIG.
The processes of to S34 are the first reset process (step S2).
0) or after the second reset processing (step S36) and the normal processing operation of the microcomputer (step S35)
Is executed before is started.

The first and second reset processes of steps S20 and S36 are the same as the first and second reset processes of steps S0 and S11 described above, and step S3
Since the processing content of step 5 is the same as the processing content of step S10 described above and the error processing of steps S25 and S31 is similar to the error processing of step S6 described above, these steps S20, S25, S31, S35, The description of S36 is omitted.

In steps S21 to S24, an area other than the storage RAM area 5a in the RAM area 5 (normal RA
A memory check is performed on the M area 5b and the save RAM area 5c). That is, first, the data (arbitrary data) to the area of the RAM area 5 other than the storage RAM area 5a
Is written (step S21), and the written data is read from the RAM area 5 (step S21).
22), it is determined whether the written data (data value) and the read data (data value) match (step S23), and if they match, step S24.
Then, it is determined whether the memory check of all areas of the RAM area 5 other than the storage RAM area 5a is completed. If not completed, steps S21 to S2 are completed.
The process of step 4 is repeated, and the memory check is performed on all areas of the RAM area 5 other than the storage RAM area 5a. Only when the result of the memory check is good for all the areas, the process proceeds to step S26 and the storage RAM The data to be continuously used in the area 5a is saved in the save RAM area 5c, and the process proceeds to step S27.

If it is determined in step S23 that the written data does not match the read data, the RAM area 5 (the entire area of the RAM area 5 other than the storage RAM area 5a) is physically stored. Since there is a possibility that there is an abnormality and the data stored in the storage RAM area 5a is also unreliable, the process proceeds to step S25 and the same error processing as in step S6 is performed.

In steps S27 to S30, the storage RAM
A memory check is performed on the area 5a. That is, first, data (arbitrary data) is written to the storage RAM area 5a (step S27), the written data is read from the RAM area 5a (step S28), and the written data (data value) And the read data (data value) are determined (step S29). If they are the same, the process proceeds to step S30 to determine whether or not the memory check of the entire storage RAM area 5a is completed. If it is determined and not completed, the processes of steps S27 to S30 are repeated until the completion, and the memory check of the entire storage RAM area 5a is performed, and the result of the memory check is good for the entire storage RAM area 5a. Only in this case, the process proceeds to step S32, and the data saved in the save RAM area 5c to be continuously used is stored in the storage RA. Is returned to the region 5a, Step S33
Proceed to.

If it is determined in step S29 that the written data and the read data do not match, there is a possibility that the storage RAM area 5a has a physical abnormality, and the storage RAM area 5a does not have the physical abnormality. Since the stored data is in an untrustworthy state, the process proceeds to step S31, and the same error processing as in step S6 is performed.

In step S33, the storage RAM area 5a
Various kinds of code check similar to the above-mentioned step S8 are performed on the data returned to step S8. If no abnormality is found in the data by the code check, the process proceeds to step S35 and is encoded in the storage RAM area 5a. The stored data is converted into normal data, written in the corresponding normal RAM area 5b, and used for normal processing.

If an abnormality is found in the data as a result of the code check in step S33, step S3
After the restoration processing for the broken data among the data stored in the storage RAM area 5a is performed in step 4, the process proceeds to step S35, and the data in the storage RAM area 5a normalized by the restoration processing is Converted to normal data and written in the corresponding normal RAM area 5b,
Used for normal processing.

As described above, in this embodiment, the same effect as in the case of the first embodiment described above can be obtained.
As a peculiar effect of this embodiment, since the save RAM area 5c, which is a save area for data in the storage RAM area 5a, is provided in the RAM area 5, it is possible to easily secure a save area having a relatively large capacity. There is an advantage that you can.

[0046]

According to the invention described in claims 1 to 7, when the operation processing means starts the operation after the resetting, the arithmetic processing means is added to the storage area used for the normal processing operation in the second semiconductor storage means. Memory check is performed, and the data existing in the storage area is used for normal processing operation only when the result of the memory check is good, so without changing the hardware configuration, By only changing the operation program of the arithmetic processing means, it is possible to prevent the operation abnormality caused by using the incorrect data due to the physical abnormality of the semiconductor storage means, and improve the reliability.

Further, at the time of starting the operation after the reset, it is possible to continue the processing operation by using the data before the reset, in which the reliability is guaranteed, as it is.

According to the second aspect of the invention, since the dedicated data storage area for storing the data that is continuously used even after the reset is provided, the data is saved when the data to be saved is saved. No extra processing such as searching for the destination is required, and the efficiency of the program can be improved.

Since a dedicated save area for saving the data in the data storage area is provided, there is no need for extra processing such as searching for a save destination when saving the data,
The program and operation can be simplified.

According to the third aspect of the present invention, before the data in the data save area is saved in the save area, the memory check is also performed on the save area. It is possible to prevent a problem from occurring in the data due to a physical abnormality in the save area when saving the data, and it is possible to further improve the reliability of the data in the data storage area.

According to the fourth aspect of the invention, generally, when performing a memory check on the RAM, it is necessary to secure a use area for program execution on the RAM. Although it is necessary to perform the memory check of the entire RAM separately while switching the execution regions, the memory check for the registers can be executed for the entire registers at once without switching the execution region of the program on the RAM. . Therefore, by providing the save area in the register, it is possible to easily perform the memory check of the register before saving the data from the data storage area to the save area.

According to the fifth aspect of the invention, since the save area is provided in the RAM, it is possible to easily secure the save area having a relatively large capacity.

[Brief description of drawings]

FIG. 1 is a block diagram of a microcomputer that is an information processing device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the microcomputer shown in FIG.

FIG. 3 is a block diagram of a microcomputer that is an information processing device according to a second embodiment of the present invention.

4 is a flowchart showing the operation of the microcomputer of FIG.

[Explanation of symbols]

1 CPU 3 ROM area 5 RAM area 5a storage RAM area 5b Normal RAM area 5c Save RAM area 7 General-purpose register area 7a free space 7b Normal register area

Claims (7)

[Claims] 1. A first semiconductor memory means in which a program and operation data are recorded, a second semiconductor memory means in which the memory content can be rewritten, and an arithmetic processing means which operates based on the program and the operation data. The arithmetic processing means performs information processing with respect to input contents from the outside in its normal processing operation while using the second semiconductor storage means as a data storage location, and outputs the processing result to the outside. In the information processing apparatus for outputting, the arithmetic processing means writes data into the storage area used for the normal processing operation in the second semiconductor storage means and stores the data when the operation is started after reset. After reading, the memory check to determine whether the contents of the read data and the contents of the written data match. It was carried out, in which case the memory check result is good only, the information processing apparatus characterized by using the data present in the storage area in the normal processing operation after the reset. 2. The information processing apparatus according to claim 1, wherein the second semiconductor storage means stores a data storage area in which data to be left without being erased at reset is stored, and a storage of the data storage area. A save area provided for saving contents and a normal storage area are provided, and the arithmetic processing unit erases data stored in the second semiconductor storage unit during the normal processing operation at reset. Data that should be left without being saved is stored in both the data storage area and the normal storage area or in the data storage area, and data that does not need to be left at reset is stored in the normal storage area while processing operations are performed. When the operation is started after the reset, the data in the data storage area is saved in the save area, and the data is saved in the data save area. The memory check, and only when the result of the memory check is good, the data saved in the save area is returned to the data storage area and used for the normal processing operation after the reset. An information processing device characterized by: 3. The information processing apparatus according to claim 2, wherein the arithmetic processing unit saves the data in the data storage area at the start of the operation after the reset to the save area before the save area. The memory check is performed on the data storage area, the data in the data storage area is saved in the save area, and the memory check is performed on the data storage area only when the result of the memory check is good. Information processing device. 4. The information processing apparatus according to claim 2, wherein the second semiconductor storage means includes a RAM and a register, and the data storage area and the normal storage area are the RAM.
The information processing device, wherein the save area is provided in the register. 5. The information processing apparatus according to claim 2, wherein the second semiconductor storage means includes a RAM, and the data storage area, the save area, and the normal storage area are provided in the RAM. An information processing device characterized by the above. 6. A first semiconductor memory means in which a program and operation data are recorded, a second semiconductor memory means in which the memory content can be rewritten, and an arithmetic processing means which operates based on the program and the operation data. The arithmetic processing means performs information processing with respect to input contents from the outside in its normal processing operation while using the second semiconductor storage means as a data storage location, and outputs the processing result to the outside. In the operation method of the information processing device for outputting, in the arithmetic processing means, at the time of starting the operation after resetting, writing data to a storage area used for the normal processing operation in the second semiconductor storage means, After the data is read, it is determined whether the content of the read data and the content of the written data match. Memory check is performed, and the data existing in the storage area is used for the normal processing operation after the reset only when the results of both memory checks are good. How it works. 7. A first semiconductor memory means in which a program and operation data are recorded, a second semiconductor memory means in which the memory content can be rewritten, and an arithmetic processing means which operates based on the program and the operation data. The arithmetic processing means performs information processing with respect to input contents from the outside in its normal processing operation while using the second semiconductor storage means as a data storage location, and outputs the processing result to the outside. In the program of the information processing device to be output, the arithmetic processing unit writes data to a storage area used for the normal processing operation in the second semiconductor storage unit at the start of operation after resetting and After making the data read, determine whether the content of the read data and the content of the written data match. A memory check is performed, and only when the results of both memory checks are good, the data existing in the storage area is used for the normal processing operation after the reset. program.