JP2003234503A - Semiconductor light-emitting device - Google Patents

Semiconductor light-emitting device

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Publication number
JP2003234503A
JP2003234503A JP2002032307A JP2002032307A JP2003234503A JP 2003234503 A JP2003234503 A JP 2003234503A JP 2002032307 A JP2002032307 A JP 2002032307A JP 2002032307 A JP2002032307 A JP 2002032307A JP 2003234503 A JP2003234503 A JP 2003234503A
Authority
JP
Japan
Prior art keywords
light emitting
layer
emitting device
conductive layer
type conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002032307A
Other languages
Japanese (ja)
Other versions
JP4063548B2 (en
Inventor
Mitsuhiro Tanaka
光浩 田中
Tomohiko Shibata
智彦 柴田
Osamu Oda
小田  修
Takashi Egawa
孝志 江川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NGK Insulators Ltd
Original Assignee
NGK Insulators Ltd
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Publication date
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Priority to JP2002032307A priority Critical patent/JP4063548B2/en
Priority to US10/351,390 priority patent/US6835965B2/en
Priority to EP03002738.7A priority patent/EP1335435B1/en
Publication of JP2003234503A publication Critical patent/JP2003234503A/en
Application granted granted Critical
Publication of JP4063548B2 publication Critical patent/JP4063548B2/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y20/00Nanooptics, e.g. quantum optics or photonic crystals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025Physical imperfections, e.g. particular concentration or distribution of impurities
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/30Structure or shape of the active region; Materials used for the active region
    • H01S5/34Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/343Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/34333Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/0242Crystalline insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02458Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • HELECTRICITY
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    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S2301/00Functional characteristics
    • H01S2301/17Semiconductor lasers comprising special layers
    • H01S2301/173The laser chip comprising special buffer layers, e.g. dislocation prevention or reduction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting device that reduces dislocation density, and has high luminous efficiency. <P>SOLUTION: A foundation layer 13 for composing a semiconductor light- emitting device 20 contains Al, and-consists of a nitride semiconductor having a dislocation density of 10<SP>11</SP>/cm<SP>2</SP>or less. Additionally, n- and p-type conductive layers 14 and 17 are composed of a nitride semiconductor that has a small content of Al as compared with the nitride semiconductor and has a dislocation density of 10<SP>10</SP>/cm<SP>2</SP>or less. Furthermore, a luminous layer 15 is composed of a nitride semiconductor that has a small content of Al as compared with the nitride semiconductor and has a dislocation density of 10<SP>10</SP>/cm<SP>2</SP>or less. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体発光素子に
関し、詳しくはフォトダイオードなどとして好適に用い
ることのできるIII族窒化物を用いた半導体発光素子に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device, and more particularly to a semiconductor light emitting device using a group III nitride which can be suitably used as a photodiode or the like.

【0002】[0002]

【従来の技術】III族窒化物膜は、半導体発光素子を構
成する半導体膜として用いられており、近年において
は、特に緑色光から青色光用の高輝度光源、さらには、
紫外光及び白色光用の光源としても期待されている。
2. Description of the Related Art Group III nitride films are used as semiconductor films for semiconductor light emitting devices, and in recent years, particularly high brightness light sources for green light to blue light, and further,
It is also expected as a light source for ultraviolet light and white light.

【0003】近年においては、このようなIII族窒化物
膜を形成する基板として、所定の基材上にエピタキシャ
ル成長により形成した下地膜を具える、いわゆるエピタ
キシャル基板が頻繁に用いられている。そして、このエ
ピタキシャル基板上に、単層のIII族窒化物膜あるいは
複数のIII族窒化物膜が積層されてなる所定のIII族窒化
物層群を、MOCVD法などを用いて形成することによ
り、目的とする半導体発光素子を得ている。
In recent years, as a substrate for forming such a group III nitride film, a so-called epitaxial substrate having a base film formed by epitaxial growth on a predetermined base material is frequently used. Then, a predetermined group III nitride layer group formed by laminating a single layer group III nitride film or a plurality of group III nitride films is formed on this epitaxial substrate by using the MOCVD method or the like, The desired semiconductor light emitting device is obtained.

【0004】図1は、従来のいわゆるPIN型の半導体
発光素子の一例を示す構成図である。
FIG. 1 is a block diagram showing an example of a conventional so-called PIN type semiconductor light emitting device.

【0005】図1に示す半導体発光素子10において
は、主としてサファイア単結晶からなる基板1上におい
て、GaNからなるバッファ層2、Siドープのn−G
aNからなる下地層3、Siドープのn−AlGaNか
らなるn型導電層4、InGaNからなる多重量子井戸
(MQW)構造の発光層5、Mgドープのp−AlGa
Nからなるp型クラッド層6、Mgドープのp−GaN
からなるp型導電層7がこの順に形成されている。図1
に示す半導体発光素子10においては、n型導電層4か
らp型導電層7までが発光素子構造を構成する。
In the semiconductor light emitting device 10 shown in FIG. 1, a GaN buffer layer 2 and a Si-doped n-G are provided on a substrate 1 mainly made of sapphire single crystal.
An underlayer 3 made of aN, an n-type conductive layer 4 made of Si-doped n-AlGaN, a light emitting layer 5 made of InGaN having a multiple quantum well (MQW) structure, and Mg-doped p-AlGa.
P-type cladding layer 6 made of N, Mg-doped p-GaN
The p-type conductive layer 7 made of is formed in this order. Figure 1
In the semiconductor light emitting device 10 shown in FIG. 3, the n-type conductive layer 4 to the p-type conductive layer 7 form a light emitting device structure.

【0006】n型導電層4の一部は露出しており、この
露出した部分にAl/Tiなどのn型電極8が形成され
るとともに、p型導電層7上にはAu/Niなどのp型
電極9が形成されている。
A part of the n-type conductive layer 4 is exposed, and an n-type electrode 8 of Al / Ti or the like is formed on this exposed portion, and Au / Ni or the like is formed on the p-type conductive layer 7. A p-type electrode 9 is formed.

【0007】そして、n型電極8及びp型電極9間に所
定の電圧を印加することにより、発光層5内でキャリア
の再結合が生じ、所定の波長の光を発光する。なお、前
記波長は、発光層の構造及び組成などによって決定され
る。
Then, by applying a predetermined voltage between the n-type electrode 8 and the p-type electrode 9, recombination of carriers occurs in the light emitting layer 5, and light of a predetermined wavelength is emitted. The wavelength is determined by the structure and composition of the light emitting layer.

【0008】[0008]

【発明が解決しようとする課題】図1に示す半導体発光
素子10において、バッファ層2は、基板1と下地層3
との格子定数差を補完して、基板1上方に形成されるべ
き下地層3などのエピタキシャル成長を可能とすべく、
緩衝層としての作用を果たすものである。したがって、
通常はその結晶性を無視して500〜700℃の低温に
おいて、アモルファス状に形成される。
In the semiconductor light emitting device 10 shown in FIG. 1, the buffer layer 2 includes the substrate 1 and the base layer 3.
In order to compensate for the difference in lattice constant between and, and to enable epitaxial growth of the underlayer 3 to be formed above the substrate 1,
It functions as a buffer layer. Therefore,
Normally, ignoring its crystallinity, it is formed in an amorphous state at a low temperature of 500 to 700 ° C.

【0009】この結果、バッファ層2中には比較的多量
の転位が含有されてしまい、この転位の一部が貫通転位
として下地層3、n型導電層4、発光層5、p型クラッ
ド層6、及びp型導電層7中に伝搬する。結果としてこ
れらの層中にも1010/cmを超える量の転位が含
まれていまい、結晶品質が劣化してしまっていた。特
に、短波長用の半導体発光素子、すなわちn型導電層3
及び発光層4がAlをより多く含む場合において上記傾
向は顕著になる。
As a result, a relatively large amount of dislocations are contained in the buffer layer 2, and some of these dislocations are threading dislocations, which are the underlying layer 3, the n-type conductive layer 4, the light-emitting layer 5, and the p-type cladding layer. 6 and the p-type conductive layer 7. As a result, dislocations in excess of 10 10 / cm 2 were included in these layers, and the crystal quality was deteriorated. In particular, a semiconductor light emitting device for short wavelength, that is, the n-type conductive layer 3
The above tendency becomes remarkable when the light emitting layer 4 contains more Al.

【0010】このような高転位で低結晶品質の層から半
導体発光素子を構成すると、発光層の転位に起因してい
わゆる非発光再結合が起こり、発光効率が減少するとい
う問題があった。
When a semiconductor light emitting device is composed of such a layer having high dislocations and low crystal quality, there is a problem that so-called non-radiative recombination occurs due to the dislocations in the light emitting layer and the luminous efficiency is reduced.

【0011】本発明は、転位密度を低減し、高い発光効
率を有する半導体発光素子を提供することを目的とす
る。
An object of the present invention is to provide a semiconductor light emitting device having a reduced dislocation density and a high luminous efficiency.

【0012】[0012]

【課題を解決するための手段】上記目的を達成すべく、
本発明の半導体発光素子は、所定の基板上において、窒
化物半導体からなる下地層と、窒化物半導体層群を含む
発光素子構造とを具え、前記下地層を構成する前記窒化
物半導体は、少なくともAlを含むとともに、転位密度
が1011/cm以下であり、前記発光素子構造を構成
する前記窒化物半導体層群は、前記下地層を構成する前
記窒化物半導体よりも少ない含有量でAlを含むととも
に、転位密度が1×1010/cm以下であることを特
徴とする。
[Means for Solving the Problems] In order to achieve the above object,
The semiconductor light emitting device of the present invention comprises a base layer made of a nitride semiconductor and a light emitting device structure including a group of nitride semiconductor layers on a predetermined substrate, and the nitride semiconductor constituting the base layer is at least In addition to containing Al, the dislocation density is 10 11 / cm 2 or less, and the nitride semiconductor layer group forming the light emitting device structure contains Al in a smaller content than the nitride semiconductor forming the underlayer. In addition to the above, the dislocation density is 1 × 10 10 / cm 2 or less.

【0013】本発明者らは、上記目的を達成するべく鋭
意検討を実施した。上述した発光効率の劣化は、半導体
発光素子を構成する各層の低結晶品質に基づく高転位の
結果として生じるものであることから、本発明者らは、
半導体発光素子を構成する各層の転位量を減らして結晶
品質を向上させることを試みた。
The inventors of the present invention have made extensive studies to achieve the above object. The above-mentioned deterioration of the luminous efficiency is caused as a result of high dislocations based on the low crystal quality of each layer constituting the semiconductor light emitting device.
An attempt was made to improve the crystal quality by reducing the dislocation amount of each layer constituting the semiconductor light emitting device.

【0014】上述したように、半導体発光素子を構成す
る各層中における転位は、低結晶品質のバッファ層に起
因するものである。図1に示す従来の半導体発光素子に
おいては、基板1としてはサファイア単結晶が用いら
れ、下地層3としてはn−GaNが用いられていたた
め、下地層3上にIII族窒化物であるn−AlGaNか
らなるn型導電層4を形成すると、下地層3内に存在す
る転位がn型導電層4内にも伝搬してしまうという問題
があった。特に、n型導電層4を構成するn−AlGa
N中のAl含有量が増大すると、クラックを発生させて
しまう場合もあった。これは、n型導電層4がAlを含
むことによってその格子定数が縮小されるため、このn
型導電層4内に引張応力が発生することに起因する。
As described above, the dislocations in each layer constituting the semiconductor light emitting device are caused by the low crystal quality buffer layer. In the conventional semiconductor light emitting device shown in FIG. 1, since sapphire single crystal is used as the substrate 1 and n-GaN is used as the underlayer 3, n-nitride which is a group III nitride is formed on the underlayer 3. When the n-type conductive layer 4 made of AlGaN is formed, there is a problem that dislocations existing in the underlayer 3 propagate to the n-type conductive layer 4. In particular, n-AlGa forming the n-type conductive layer 4
When the Al content in N was increased, cracks were sometimes generated. This is because when the n-type conductive layer 4 contains Al, its lattice constant is reduced.
This is because tensile stress is generated in the mold conductive layer 4.

【0015】そこで、バッファ層のみならず、下地層に
ついても種々検討を行った。図1に示す従来の半導体発
光素子においては、その構成から明らかなように、発光
層などはGaを主とした窒化物半導体から構成されてい
る。したがって、これら各層に対する下地層についても
Ga系を主とした、例えばGaNから構成することが当
然と考えられていた。その結果、基板との格子不整合が
生じ、これを緩和するために低温形成のバッファ層が必
要とされていた。
Therefore, various studies were conducted not only on the buffer layer but also on the underlayer. In the conventional semiconductor light emitting device shown in FIG. 1, as is clear from the structure, the light emitting layer and the like are composed of a nitride semiconductor mainly containing Ga. Therefore, it was naturally considered that the underlying layer for each of these layers was also made of, for example, GaN, mainly Ga-based. As a result, a lattice mismatch with the substrate occurs, and a buffer layer formed at a low temperature is required to alleviate this.

【0016】しかしながら、本発明者らは、当然と思わ
れていた下地層の組成に着目し、この組成を変化させる
ことを試みた。その結果、下地層を低転位で良好な結晶
品質のAlを主とする窒化物半導体から構成することを
想到した。この下地層はバッファ層が存在しない場合に
おいても、サファイアなどの基板上に大きな格子定数差
を補完してエピタキシャル成長することができる。ま
た、下地層の高い結晶品質に基づいて、下地層上に形成
された導電層及び発光層の結晶品質も改善され、それら
の転位量が低減される。結果として、半導体発光素子を
構成する各層中に転位量が低減され、高い転位量に基づ
く非発光再結合を効果的に抑制することができる。
However, the present inventors paid attention to the composition of the underlayer which was supposed to be natural, and tried to change this composition. As a result, they have conceived that the underlayer is composed of a nitride semiconductor mainly composed of Al with low dislocation and good crystal quality. Even if there is no buffer layer, this underlayer can be epitaxially grown on a substrate such as sapphire by complementing a large difference in lattice constant. Further, based on the high crystal quality of the underlayer, the crystal quality of the conductive layer and the light emitting layer formed on the underlayer is also improved, and the dislocation amount thereof is reduced. As a result, the dislocation amount is reduced in each layer constituting the semiconductor light emitting device, and non-radiative recombination due to the high dislocation amount can be effectively suppressed.

【0017】また、このような高結晶品質の下地層は、
放熱特性に優れている。このため、下地層の高結晶品質
と放熱特性との相乗効果によって、半導体発光素子の発
光効率を向上させることができ、高輝度発光が可能とな
る。
Further, such an underlayer having high crystal quality is
Excellent heat dissipation characteristics. Therefore, due to the synergistic effect of the high crystal quality of the underlayer and the heat dissipation characteristic, the light emitting efficiency of the semiconductor light emitting element can be improved, and high brightness light emission is possible.

【0018】[0018]

【発明の実施の形態】以下、本発明を発明の実施の形態
に即して詳細に説明する。図2は、本発明の半導体発光
素子の一例を示す構成図である。図2に示す半導体発光
素子20は、基板11上において、下地層13、n型導
電層14、発光層15、p型クラッド層16、及びp型
導電層17を順次具えている。そして、図1に示す従来
の半導体発光素子10と同様に、n型導電層14の一部
は露出しており、この露出したn型導電層14上には、
例えばAl/Tiからなるn型電極18が形成され、p
型導電層15上には例えばAu/Niからなるp型電極
19が形成されて、いわゆるPIN型の半導体発光素子
を構成している。
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the embodiments of the invention. FIG. 2 is a configuration diagram showing an example of the semiconductor light emitting device of the present invention. The semiconductor light emitting device 20 shown in FIG. 2 includes a base layer 13, an n-type conductive layer 14, a light emitting layer 15, a p-type clad layer 16, and a p-type conductive layer 17 in this order on a substrate 11. Then, similarly to the conventional semiconductor light emitting device 10 shown in FIG. 1, a part of the n-type conductive layer 14 is exposed, and on the exposed n-type conductive layer 14,
For example, an n-type electrode 18 made of Al / Ti is formed, and p
A p-type electrode 19 made of, for example, Au / Ni is formed on the mold conductive layer 15 to form a so-called PIN type semiconductor light emitting device.

【0019】図2において、n型導電層14、発光層1
5、p型クラッド層16、及びp型導電層17は半導体
発光素子における窒化物半導体層群を構成し、この窒化
物半導体層群と、n型電極18及びp型電極19とから
発光素子構造が構成される。なお、p型クラッド層16
は必要に応じて省略することもできる。
In FIG. 2, the n-type conductive layer 14 and the light emitting layer 1
5, the p-type cladding layer 16 and the p-type conductive layer 17 form a nitride semiconductor layer group in the semiconductor light emitting device, and the nitride semiconductor layer group, the n-type electrode 18 and the p-type electrode 19 form a light emitting device structure. Is configured. The p-type cladding layer 16
Can be omitted if desired.

【0020】下地層13は、本発明にしたがって、Al
を含み、転位密度が10 11/cm以下の窒化物半導体
から構成されていることが必要であり、前記転位密度は
さらに1010/cm以下であることが好ましい。この
場合においては、基板11との格子定数差を補完して、
自らエピタキシャル成長されることができるとともに、
その結果、下地層13上においてn型導電層14、発光
層15、及びp型導電層17をもエピタキシャル成長さ
せることができる。
The underlayer 13 is made of Al according to the present invention.
And the dislocation density is 10 11/ CmTwoThe following nitride semiconductors
The dislocation density is
10 moreTen/ CmTwoThe following is preferable. this
In some cases, the lattice constant difference from the substrate 11 is complemented,
In addition to being able to grow epitaxially by itself,
As a result, the n-type conductive layer 14 emits light on the underlayer 13.
The layer 15 and the p-type conductive layer 17 are also grown epitaxially.
Can be made.

【0021】また、窒化物半導体層群を構成するn型導
電層14、発光層15、及びp型導電層17は、下地層
13よりもAlの少ない含有量で、転位密度が1010
cm以下の窒化物半導体から構成されていることが必
要である。これによって、半導体発光素子20の発光効
率を向上させることができる。
Further, the n-type conductive layer 14, the light-emitting layer 15, and the p-type conductive layer 17 constituting the nitride semiconductor layer group contain less Al than the underlayer 13 and have a dislocation density of 10 10 /.
It must be composed of a nitride semiconductor of cm 2 or less. As a result, the luminous efficiency of the semiconductor light emitting device 20 can be improved.

【0022】これは、下地層13とn型導電層14との
間のAl組成差に起因して貫通転位の割合が減少し、n
型導電層14、発光層15、及びp型導電層17中の転
位密度を低減することができ、これによって、n型導電
層14などの結晶品質が向上するためである。
This is because the ratio of threading dislocations decreases due to the Al composition difference between the underlayer 13 and the n-type conductive layer 14, and
This is because the dislocation density in the type conductive layer 14, the light emitting layer 15, and the p type conductive layer 17 can be reduced, which improves the crystal quality of the n type conductive layer 14 and the like.

【0023】上述した効果は、下地層13を構成する前
記窒化物半導体におけるAlの含有量が多いほど顕著に
なり、前記窒化物半導体がその構成III族元素の総てに
対して50原子%以上のAlを含有していることが好ま
しく、さらにはAlNから構成されていることが好まし
い。
The above-mentioned effects become more remarkable as the content of Al in the nitride semiconductor forming the underlayer 13 increases, and the nitride semiconductor contains 50 atomic% or more of all the group III elements. Al is preferably contained, and more preferably AlN is contained.

【0024】このように、下地層13を上述した高Al
含有量の窒化物半導体から構成することによって、n型
導電層14の結晶品質をさらに向上させることができ
る。その結果、下地層13上に形成されたn型導電層1
4、発光層15、及びp型導電層17の結晶品質を向上
させて、さらなる低転位化を達成することもできる。
As described above, the underlayer 13 is formed of the high Al content described above.
The crystal quality of the n-type conductive layer 14 can be further improved by using the nitride semiconductor in the content. As a result, the n-type conductive layer 1 formed on the underlayer 13
4, it is also possible to improve the crystal quality of the light emitting layer 15 and the p-type conductive layer 17 to achieve further low dislocation.

【0025】例えば、下地層13がAlNから構成さ
れ、下地層13上に直接的に形成されたn型導電層14
がGaを比較的多く含有するAlGaNなどから構成さ
れる場合などにおいては、下地層13とn型導電層14
との間の組成差が増大するために、下地層13の転位量
に比較してn型導電層14の転位量をより低減すること
ができる。
For example, the underlayer 13 is made of AlN, and the n-type conductive layer 14 is formed directly on the underlayer 13.
Is composed of AlGaN or the like containing a relatively large amount of Ga, the underlying layer 13 and the n-type conductive layer 14
Therefore, the dislocation amount of the n-type conductive layer 14 can be further reduced as compared with the dislocation amount of the underlayer 13.

【0026】特に、窒化物半導体層群のGa含有量がそ
の構成III族元素の総てに対して80%以上である場合
には、前記窒化物半導体層群を構成するn型導電層1
4、発光層15、及びp型導電層17の転位密度を1×
10/cm以下まで簡易に低減することができ、現
状においては1×10/cm以下まで低減すること
ができる。なお、前記Ga含有量は前記窒化物半導体層
群の全体における平均組成である。
In particular, when the Ga content of the nitride semiconductor layer group is 80% or more with respect to all the constituent group III elements, the n-type conductive layer 1 constituting the nitride semiconductor layer group is formed.
4, the light emitting layer 15, and the p-type conductive layer 17 have a dislocation density of 1 ×
It can be easily reduced to 10 9 / cm 2 or less, and can be reduced to 1 × 10 8 / cm 2 or less at present. The Ga content is an average composition of the entire nitride semiconductor layer group.

【0027】Alを含み、低転位密度で高結晶品質の窒
化物半導体からなる下地層13は、例えば、MOCVD
法により、その成膜温度を制御することによって得るこ
とができる。具体的には、成膜温度を1100℃以上に
設定することによって、目的とする高結晶品質の窒化物
半導体からなる下地層13を簡易に得ることができる。
なお、本特許の成膜温度は、基板温度を意味する。
The underlayer 13 made of a nitride semiconductor containing Al and having a low dislocation density and a high crystal quality is, for example, MOCVD.
It can be obtained by controlling the film forming temperature by the method. Specifically, by setting the film formation temperature to 1100 ° C. or higher, it is possible to easily obtain the target underlayer 13 made of a nitride semiconductor of high crystal quality.
The film formation temperature in this patent means the substrate temperature.

【0028】低転位密度で高い結晶品質のn型導電層1
4などは、上述した低転位で高結晶品質の下地層13上
に、例えばMOCVD法などによってエピタキシャル成
長させることにより、必然的に得ることができる。
N-type conductive layer 1 having low dislocation density and high crystal quality
4 and the like can be inevitably obtained by epitaxially growing the underlayer 13 having low dislocation and high crystal quality by the MOCVD method or the like.

【0029】なお、上述したような特性を満足する下地
層13は放熱特性にも優れているため、高結晶品質と高
放熱特性との相乗効果によって、半導体発光素子20の
発光効率は一層向上し、高輝度発光が可能となる。
Since the underlayer 13 satisfying the above characteristics is also excellent in heat dissipation characteristics, the light emitting efficiency of the semiconductor light emitting device 20 is further improved by the synergistic effect of high crystal quality and high heat dissipation characteristics. Therefore, high brightness light emission becomes possible.

【0030】基板11は、サファイア単結晶、ZnO単
結晶、LiAlO単結晶、LiGaO単結晶、Mg
Al単結晶、MgO単結晶などの酸化物単結晶、
Si単結晶、SiC単結晶などのIV族あるいはIV−IV族
単結晶、GaAs単結晶、AlN単結晶、GaN単結
晶、及びAlGaN単結晶などのIII−V族単結晶、Z
Bなどのホウ化物単結晶などの、公知の基板材料か
ら構成することができる。
The substrate 11 is made of sapphire single crystal, ZnO single crystal, LiAlO 2 single crystal, LiGaO 2 single crystal, Mg.
Al 2 O 4 single crystals, oxide single crystals such as MgO single crystals,
Group IV or IV-IV single crystals such as Si single crystals and SiC single crystals, GaAs single crystals, AlN single crystals, GaN single crystals, and III-V group single crystals such as AlGaN single crystals, Z
It can be composed of known substrate materials such as boride single crystals such as r 2 B.

【0031】なお、図2に示す本発明の半導体発光素子
においては、発光層15下側の導電層をn型とし、上側
の導電層をp型としているが、両者を逆転させて形成す
ることもできる。また、発光層15は単一の窒化物半導
体層から構成することもできるが、多重量子井戸構造な
どのような多層膜から構成することもできる。
In the semiconductor light emitting device of the present invention shown in FIG. 2, the lower conductive layer of the light emitting layer 15 is n-type and the upper conductive layer is p-type. You can also Further, the light emitting layer 15 can be composed of a single nitride semiconductor layer, but can also be composed of a multilayer film such as a multiple quantum well structure.

【0032】図3は、本発明の半導体発光素子のその他
の例を示す構成図である。図3に示す半導体発光素子3
0は、基板21上において、下地層23、n型導電層2
4、発光層25、及びp型導電層27を順次具えてい
る。そして、n型導電層24の一部は露出しており、こ
の露出したn型導電層24上には、例えばAl/Tiか
らなるn型電極28が形成され、p型導電層27上には
例えばAu/Niからなるp型電極29が形成されて、
いわゆるリッジ型のレーザダイオードを構成している。
FIG. 3 is a configuration diagram showing another example of the semiconductor light emitting device of the present invention. Semiconductor light emitting element 3 shown in FIG.
0 indicates the base layer 23 and the n-type conductive layer 2 on the substrate 21.
4, the light emitting layer 25, and the p-type conductive layer 27 are sequentially provided. Then, a part of the n-type conductive layer 24 is exposed, an n-type electrode 28 made of, for example, Al / Ti is formed on the exposed n-type conductive layer 24, and on the p-type conductive layer 27. For example, a p-type electrode 29 made of Au / Ni is formed,
It constitutes a so-called ridge type laser diode.

【0033】図3において、n型導電層24、発光層2
5、及びp型導電層27は半導体発光素子における窒化
物半導体層群を構成し、この窒化物半導体層群と、n型
電極28及びp型電極29とから発光素子構造が構成さ
れる。
In FIG. 3, the n-type conductive layer 24 and the light emitting layer 2 are shown.
5 and the p-type conductive layer 27 form a nitride semiconductor layer group in the semiconductor light emitting element, and the nitride semiconductor layer group and the n-type electrode 28 and the p-type electrode 29 form a light emitting element structure.

【0034】下地層23は、本発明にしたがって、Al
を含み、転位密度が10 11/cm以下の窒化物半導体
から構成されていることが必要であり、前記転位密度は
さらに1010/cm以下であることが好ましい。この
場合においては、基板21との格子定数差を補完して、
自らエピタキシャル成長されることができるとともに、
その結果、下地層23上においてn型導電層24、発光
層25、及びp型導電層27をもエピタキシャル成長さ
せることができる。
The underlayer 23 is made of Al according to the present invention.
And the dislocation density is 10 11/ CmTwoThe following nitride semiconductors
The dislocation density is
10 moreTen/ CmTwoThe following is preferable. this
In some cases, the lattice constant difference from the substrate 21 is complemented,
In addition to being able to grow epitaxially by itself,
As a result, the n-type conductive layer 24 and the light emission are formed on the underlayer 23.
The layer 25 and the p-type conductive layer 27 are also grown epitaxially.
Can be made.

【0035】また、窒化物半導体層群を構成するn型導
電層24、発光層25、及びp型導電層27は、下地層
23よりもAlの少ない含有量で、転位密度が1010
cm以下の窒化物半導体から構成されていることが必
要である。これによって、半導体発光素子30の発光効
率を向上させることができる。
Further, the n-type conductive layer 24, the light-emitting layer 25, and the p-type conductive layer 27 constituting the nitride semiconductor layer group contain less Al than the underlayer 23 and have a dislocation density of 10 10 /
It must be composed of a nitride semiconductor of cm 2 or less. As a result, the luminous efficiency of the semiconductor light emitting device 30 can be improved.

【0036】この場合においても、前述したように下地
層23とn型導電層24との間のAl組成差に起因して
貫通転位の割合が減少し、n型導電層24、発光層2
5、及びp型導電層27中の転位密度を低減することが
でき、これによって、n型導電層24などの結晶品質が
向上するためである。
Also in this case, the ratio of threading dislocations is reduced due to the difference in Al composition between the underlayer 23 and the n-type conductive layer 24 as described above, and the n-type conductive layer 24 and the light emitting layer 2 are reduced.
5 and the dislocation density in the p-type conductive layer 27 can be reduced, which improves the crystal quality of the n-type conductive layer 24 and the like.

【0037】上述した効果は、下地層23を構成する前
記窒化物半導体におけるAlの含有量が多いほど顕著に
なり、前記窒化物半導体がその構成III族元素の総てに
対して50原子%以上のAlを含有していることが好ま
しく、さらにはAlNから構成されていることが好まし
い。
The above-mentioned effects become more remarkable as the content of Al in the nitride semiconductor forming the underlayer 23 increases, and the nitride semiconductor contains 50 atomic% or more of all the group III elements. Al is preferably contained, and more preferably AlN is contained.

【0038】このように、下地層23を上述した高Al
含有量の窒化物半導体から構成することによって、n型
導電層24の結晶品質をさらに向上させることができ
る。その結果、下地層23上に形成されたn型導電層2
4、発光層25、及びp型導電層27の結晶品質を向上
させて、さらなる低転位化を達成することもできる。
As described above, the underlayer 23 is formed of the high Al content described above.
The crystal quality of the n-type conductive layer 24 can be further improved by comprising the content of the nitride semiconductor. As a result, the n-type conductive layer 2 formed on the underlayer 23
4, it is also possible to improve the crystal quality of the light emitting layer 25 and the p-type conductive layer 27 to achieve further low dislocation.

【0039】特に、窒化物半導体層群のGa含有量がそ
の構成III族元素の総てに対して80%以上である場合
には、前記窒化物半導体層群を構成するn型導電層2
4、発光層25、及びp型導電層27の転位密度を、上
記同様に1×10/cm以下まで簡易に低減するこ
とができ、現状においては1×10/cm 以下まで
低減することができる。なお、前記Ga含有量は前記窒
化物半導体層群の全体における平均組成である。
In particular, the Ga content of the nitride semiconductor layer group is
If the composition is 80% or more of all the group III elements
Is an n-type conductive layer 2 that constitutes the nitride semiconductor layer group.
4, the light emitting layer 25, and the p-type conductive layer 27
1 x 10 as above9/ CmTwoCan be easily reduced to
Can be done, and currently 1 × 108/ Cm TwoUp to
It can be reduced. The Ga content is the same as
2 is an average composition of the entire compound semiconductor layer group.

【0040】Alを含み、低転位密度で高結晶品質の窒
化物半導体からなる下地層23は、例えば、MOCVD
法により、その成膜温度を制御することによって得るこ
とができる。具体的には、成膜温度を1100℃以上に
設定することによって、目的とする高結晶品質の窒化物
半導体からなる下地層23を簡易に得ることができる。
なお、本特許の成膜温度は、基板温度を意味する。
The underlayer 23 made of a nitride semiconductor containing Al and having a low dislocation density and a high crystal quality is, for example, MOCVD.
It can be obtained by controlling the film forming temperature by the method. Specifically, by setting the film formation temperature to 1100 ° C. or higher, it is possible to easily obtain the target underlayer 23 made of a high-quality nitride semiconductor.
The film formation temperature in this patent means the substrate temperature.

【0041】低転位密度で高い結晶品質のn型導電層2
4などは、上述した低転位で高結晶品質の下地層23上
に、例えばMOCVD法などによってエピタキシャル成
長させることにより、必然的に得ることができる。
N-type conductive layer 2 having low dislocation density and high crystal quality
4 and the like can be inevitably obtained by epitaxial growth on the underlayer 23 of low dislocation and high crystal quality described above, for example, by the MOCVD method.

【0042】なお、上述したような特性を満足する下地
層23は放熱特性にも優れているため、高結晶品質と高
放熱特性との相乗効果によって、半導体発光素子30の
発光効率は一層向上し、高輝度発光が可能となる。
Since the underlayer 23 satisfying the above characteristics is also excellent in heat dissipation characteristics, the light emitting efficiency of the semiconductor light emitting device 30 is further improved by the synergistic effect of high crystal quality and high heat dissipation characteristics. Therefore, high brightness light emission becomes possible.

【0043】基板21は、上述した基板11と同様にサ
ファイア単結晶などから構成することができる。
The substrate 21 can be made of sapphire single crystal or the like, like the substrate 11 described above.

【0044】なお、図3に示す本発明の半導体発光素子
においては、発光層25下側の導電層をn型とし、上側
の導電層をp型としているが、両者を逆転させて形成す
ることもできる。また、発光層25は単一の窒化物半導
体層から構成することもできるが、多重量子井戸構造な
どのような多層膜から構成することもできる。
In the semiconductor light emitting device of the present invention shown in FIG. 3, the lower conductive layer of the light emitting layer 25 is n-type and the upper conductive layer is p-type. You can also Further, the light emitting layer 25 may be composed of a single nitride semiconductor layer, or may be composed of a multilayer film such as a multiple quantum well structure.

【0045】[0045]

【実施例】(実施例1)本実施例においては、図2に示
すPIN型の半導体発光素子を作製した。基板11とし
て2インチ径の厚さ500μmのC面サファイア単結晶
を用い、これをMOCVD装置の中に設置した。MOC
VD装置には、ガス系としてH2、N2、TMA、TM
G、Cp2Mg、NH3、SiH4が取り付けてある。圧
力を100Torrに設定した後、H2を平均流速1m
/secで流しながら、基板11を1150℃まで昇温
した。
EXAMPLE (Example 1) In this example, a PIN type semiconductor light emitting device shown in FIG. 2 was produced. A C-plane sapphire single crystal having a diameter of 2 inches and a thickness of 500 μm was used as the substrate 11, and this was installed in a MOCVD apparatus. MOC
The VD device has H 2 , N 2 , TMA, TM as a gas system.
G, Cp 2 Mg, NH 3 and SiH 4 are attached. After setting the pressure to 100 Torr, add H 2 to the average flow velocity of 1 m.
The substrate 11 was heated to 1150 ° C. while flowing at a rate of / sec.

【0046】その後、TMAとNH3とを、所定量供給
して、下地層13としてのAlN層を厚さ1μmまで成
長させた。この際、成膜速度を0.3μm/hrとなる
ように、TMA及びNHの供給量を設定した。このA
lN層中の転位密度をTEMによって観察したところ、
8×10/cmであった。AlNの(002)面の
X線ロッキングカーブを測定したところ、その半値幅は
100秒以下であり、表面粗さ(ra)は2Å以下と良
好な結晶品質を有することが確認された。
Then, a predetermined amount of TMA and NH 3 was supplied to grow an AlN layer as the underlayer 13 to a thickness of 1 μm. At this time, the supply amounts of TMA and NH 3 were set so that the film formation rate was 0.3 μm / hr. This A
When the dislocation density in the 1N layer was observed by TEM,
It was 8 × 10 9 / cm 2 . When the X-ray rocking curve of the (002) plane of AlN was measured, the full width at half maximum was 100 seconds or less, and the surface roughness (ra) was 2Å or less, and it was confirmed to have good crystal quality.

【0047】次いで、基板温度を1120℃に設定した
後、圧力を常圧にし、TMA、NH、SiHを全ガ
ス平均流速1m/secで流して、n型導電層14とし
てSiをドープしたn−GaN層を厚さ3μm成長させ
た。原料供給量は成膜速度が3μm/hrとなるように
設定した。なお、SiHは、キャリア濃度が5×10
17/cmとなるように供給した。
Next, after setting the substrate temperature to 1120 ° C., the pressure was set to normal pressure, TMA, NH 3 , and SiH 4 were flowed at an average flow rate of all gases of 1 m / sec to dope Si as the n-type conductive layer 14. The n-GaN layer was grown to a thickness of 3 μm. The raw material supply rate was set so that the film formation rate was 3 μm / hr. SiH 4 has a carrier concentration of 5 × 10 5.
It was supplied so as to be 17 / cm 3 .

【0048】次いで、各原料ガスの供給を停止し、キャ
リアガスを窒素に変更した後、基板温度を700℃とし
た。前記n−GaN層上に、TMI、TMG、NH
全ガス流速1m/secで流して、発光層15としての
i−InGaN層をMQW構造として形成した。その
後、TMIをTMAに切り替えると共にCp 2Mgをキ
ャリア濃度が2×1017/cmとなるようにして供給
し、p型クラッド層16としてのp−AlGaN層を厚
さ20nmに成長させた。その後、TMAを停止して基
板温度を100度に上昇した後TMG、NH、Cp2
Mgを供給し、p型導電層17としてのMgをドープし
たp−GaN層を厚さ0.2μmに形成した。
Then, the supply of each source gas is stopped and the cap
After changing the rear gas to nitrogen, set the substrate temperature to 700 ° C.
It was TMI, TMG, NH on the n-GaN layerThreeTo
Flowing at a total gas flow rate of 1 m / sec as the light emitting layer 15
The i-InGaN layer was formed as an MQW structure. That
After that, change TMI to TMA and Cp 2Mg
Carrier concentration is 2 × 1017/ CmThreeSupply as
The p-AlGaN layer as the p-type cladding layer 16 is thickened.
To 20 nm. After that, stop TMA and start
After raising the plate temperature to 100 degrees, TMG, NHThree, Cp2
Supply Mg to dope Mg as the p-type conductive layer 17
The p-GaN layer was formed to a thickness of 0.2 μm.

【0049】n−GaN層、i−InGaN層及びp−
GaN層の転位密度をTEMによって観察したところ、
それぞれ5×10/cm、5×10/cm 及び
5×10/cmであった。
N-GaN layer, i-InGaN layer and p-
When the dislocation density of the GaN layer was observed by TEM,
5 × 10 each7/ CmTwo5 x 107/ Cm Twoas well as
5 x 107/ CmTwoMet.

【0050】さらに、これらの各層を部分的にエッチン
グ除去することによって、n型導電層14を構成するn
−GaN層の一部を露出させ、この露出部分に対してA
l/Tiからなるn型電極18を形成した。また、p型
導電層17を構成するp−GaN層上にAu/Niから
なるp型電極19を形成した。
Further, the n-type conductive layer 14 is formed by partially removing each of these layers by etching.
-A part of the GaN layer is exposed, and A
An n-type electrode 18 made of 1 / Ti was formed. Further, the p-type electrode 19 made of Au / Ni was formed on the p-GaN layer forming the p-type conductive layer 17.

【0051】(比較例1)本比較例においては、図1に
示すPIN型の半導体発光素子を作製した。基板1とし
てのサファイア単結晶基板を用い、実施例と同様のMO
CVD装置内に設置した。基板1を600℃に加熱した
後、TMG及びNHを供給してバッファ層2としての
GaN層を厚さ0.03μmに形成した。
Comparative Example 1 In this comparative example, the PIN type semiconductor light emitting device shown in FIG. 1 was manufactured. Using a sapphire single crystal substrate as the substrate 1, the same MO as in the example was used.
It was installed in the CVD device. After heating the substrate 1 to 600 ° C., TMG and NH 3 were supplied to form a GaN layer as the buffer layer 2 with a thickness of 0.03 μm.

【0052】その後、一旦、TMG及びNHの供給を
中断し、基板温度を1120℃に設定して、TMG、N
、及びSiHを供給し、下地層3としてのn−G
aN層を、成膜速度3μm/hrで厚さ3μmに形成し
た。次いで、実施例と同様にして、n型導電層4からp
型導電層7までを形成し、さらにAl/Tiのn型電極
8、Au/Niのp型電極9を形成することによって、
半導体発光素子10を作製した。
After that, the supply of TMG and NH 3 is once interrupted, the substrate temperature is set to 1120 ° C., and TMG and N 3 are set.
H 3 and SiH 4 are supplied, and n-G as the underlayer 3 is supplied.
The aN layer was formed to a thickness of 3 μm at a film forming rate of 3 μm / hr. Then, similar to the embodiment, the n-type conductive layer 4 to p
By forming up to the type conductive layer 7, an n-type electrode 8 of Al / Ti and a p-type electrode 9 of Au / Ni are formed.
A semiconductor light emitting device 10 was produced.

【0053】n型導電層4、発光層5、及びp型導電層
7を構成するn−GaN層、i−InGaN層、及びp
−GaN層中における転位密度をTEM観察によって測
定したところ、それぞれ2×1010/cm、2×10
10/cm及び2×10/cmであった。
An n-GaN layer, an i-InGaN layer, and a p that constitute the n-type conductive layer 4, the light emitting layer 5, and the p-type conductive layer 7.
The dislocation density in -GaN layer was measured by TEM observation, each 2 × 10 10 / cm 2, 2 × 10
10 / cm 2 and 2 × 10 9 / cm 2 .

【0054】図4は、上記実施例1及び比較例1で作製
した半導体発光素子の発光特性を示すグラフである。図
4においては、半導体発光素子への注入電流と発光出力
との関係を示している。図4から明らかなように、所定
の注入電流に対しては、実施例1で得た半導体発光素子
の方が比較例1で得た半導体発光素子よりも大きな発光
出力を示すことが分かる。
FIG. 4 is a graph showing the light emission characteristics of the semiconductor light emitting devices produced in Example 1 and Comparative Example 1 described above. FIG. 4 shows the relationship between the injection current to the semiconductor light emitting element and the light emission output. As is clear from FIG. 4, the semiconductor light emitting device obtained in Example 1 exhibits a larger light emission output than the semiconductor light emitting device obtained in Comparative Example 1 for a given injection current.

【0055】また、実施例1において得た半導体発光素
子においては、注入電流の増大に伴って発光出力も増大
し、高注入電流領域では高い発光出力を示すことが分か
る。一方、比較例1において得た半導体発光素子におい
ては、高注入電力領域において素子が破壊し、これに伴
って発光出力が劣化することが分かる。
Further, it is understood that in the semiconductor light emitting device obtained in Example 1, the light emission output also increases with the increase of the injection current, and the high light emission output is exhibited in the high injection current region. On the other hand, in the semiconductor light emitting device obtained in Comparative Example 1, it was found that the device was destroyed in the high injection power region, and the light emission output was deteriorated accordingly.

【0056】(実施例2)本実施例においては、図3に
示すリッジ型のレーザダイオードを簡略化したものを作
製した。具体的には、発光層25、p型導電層27、n
型電極28及びp型電極29を形成することなく、下地
層23を発光層として機能させ、所定の励起光を用いる
ことにより誘導放出を実施した。
Example 2 In this example, a simplified version of the ridge type laser diode shown in FIG. 3 was produced. Specifically, the light emitting layer 25, the p-type conductive layer 27, n
The underlying layer 23 was made to function as a light emitting layer without forming the mold electrode 28 and the p-type electrode 29, and stimulated emission was carried out by using predetermined excitation light.

【0057】基板21として2インチ径の厚さ500μ
mのC面サファイア単結晶を用い、これをMOCVD装
置の中に設置した。MOCVD装置には、ガス系として
2、N2、TMA、TMG、Cp2Mg、NH3、SiH
4が取り付けてある。圧力を100Torrに設定した
後、H2を平均流速1m/secで流しながら、基板2
1を1150℃まで昇温した。
The substrate 21 has a diameter of 2 inches and a thickness of 500 μm.
A m-plane C-plane sapphire single crystal was used and placed in a MOCVD apparatus. The MOCVD apparatus uses H 2 , N 2 , TMA, TMG, Cp 2 Mg, NH 3 , and SiH as a gas system.
4 is attached. After setting the pressure to 100 Torr, while flowing H 2 at an average flow rate of 1 m / sec, the substrate 2
1 was heated to 1150 ° C.

【0058】その後、TMAとNH3とを、所定量供給
して、下地層23としてのAlN層を厚さ1μmまで成
長させた。この際、成膜速度を0.3μm/hrとなる
ように、TMA及びNHの供給量を設定した。このA
lN層中の転位密度をTEMによって観察したところ、
8×10/cmであった。AlNの(002)面の
X線ロッキングカーブを測定したところ、その半値幅は
100秒以下であり、表面粗さ(ra)は2Å以下と良
好な結晶品質を有することが確認された。
After that, a predetermined amount of TMA and NH 3 was supplied to grow an AlN layer as the underlayer 23 to a thickness of 1 μm. At this time, the supply amounts of TMA and NH 3 were set so that the film formation rate was 0.3 μm / hr. This A
When the dislocation density in the 1N layer was observed by TEM,
It was 8 × 10 9 / cm 2 . When the X-ray rocking curve of the (002) plane of AlN was measured, the full width at half maximum was 100 seconds or less, and the surface roughness (ra) was 2Å or less, and it was confirmed to have good crystal quality.

【0059】次いで、基板温度を1120℃に設定した
後、圧力を常圧にし、TMG、NH、SiHを全ガ
ス平均流速1m/secで流して、n型導電層24とし
てSiをドープしたn−GaN層を厚さ3μm成長させ
た。原料供給量は成膜速度が3μm/hrとなるように
設定した。なお、SiHは、キャリア濃度が1.1×
1017/cmとなるように供給した。
Next, after setting the substrate temperature to 1120 ° C., the pressure was set to normal pressure, TMG, NH 3 , and SiH 4 were flowed at an average flow rate of all gases of 1 m / sec to dope Si as the n-type conductive layer 24. The n-GaN layer was grown to a thickness of 3 μm. The raw material supply rate was set so that the film formation rate was 3 μm / hr. SiH 4 has a carrier concentration of 1.1 ×
It was supplied so as to be 10 17 / cm 3 .

【0060】その後、上述のようにして作製したアセン
ブリを3000μmの長さで劈開し、幅500μmのリ
ッジ型のレーザダイオードを作製した。前記n−GaN
層の転位密度をTEMによって観察したところ、5×1
/cmであった。
Thereafter, the assembly produced as described above was cleaved to a length of 3000 μm to produce a ridge type laser diode having a width of 500 μm. The n-GaN
When the dislocation density of the layer was observed by TEM, it was 5 × 1.
It was 0 7 / cm 2 .

【0061】(比較例2)本比較例においては、実施例
2同様に、リッジ型のレーザダイオードを作製した。但
し、基板21を600℃に加熱し、TMG及びNH
供給することにより、基板21上にバッファ層してのG
aN層を厚さ0.03μmに設けた。このとき、前記バ
ッファ層上に形成したn−GaN層の転位密度をTEM
によって観察したところ、2×1010/cmであっ
た。
Comparative Example 2 In this comparative example, a ridge type laser diode was manufactured in the same manner as in Example 2. However, when the substrate 21 is heated to 600 ° C. and TMG and NH 3 are supplied, G as a buffer layer is formed on the substrate 21.
The aN layer was provided to a thickness of 0.03 μm. At this time, the dislocation density of the n-GaN layer formed on the buffer layer was measured by TEM.
It was 2 × 10 10 / cm 2 when observed by.

【0062】実施例2及び比較例2で得たレーザダイオ
ードの誘導放出光出力と励起光強度との関係を調べたと
ころ、図5に示すような結果が得られた。本発明に従っ
て得た実施例2で示すレーザダイオードにおいては、
0.5MW/cmの励起光強度で誘導放出が生じるの
に対し、比較例2で示すような低温バッファ層を有する
レーザダイオードにおいては、0.6MW/cmの励
起光強度で誘導放出が生じることが確認された。すなわ
ち、本発明に従って得た実施例2におけるレーザダイオ
ードにおいては、誘導放出の生じるしきい値が低減され
ており、励起効率の大きいことが確認された。
When the relationship between the stimulated emission light output and the excitation light intensity of the laser diodes obtained in Example 2 and Comparative Example 2 was examined, the results shown in FIG. 5 were obtained. In the laser diode shown in Example 2 obtained according to the present invention,
Stimulated emission occurs at an excitation light intensity of 0.5 MW / cm 2 , whereas in a laser diode having a low temperature buffer layer as shown in Comparative Example 2, stimulated emission occurs at an excitation light intensity of 0.6 MW / cm 2. It was confirmed to occur. That is, it was confirmed that in the laser diode of Example 2 obtained according to the present invention, the threshold value at which stimulated emission occurs was reduced, and the excitation efficiency was high.

【0063】以上、実施例及び比較例から明らかなよう
に、本発明に従って作製された半導体発光素子において
は、下地層の高結晶品質に起因して各層の結晶品質も改
善され、転位量が低減されている効果と、AlN下地層
の放熱特性の向上効果との相乗効果によって発光効率及
び励起効率が向上し、高輝度発光が実現されていること
が分かる。したがって、実施例に示す半導体発光素子
は、比較例に示す半導体発光素子と比較して、高い効率
の半導体発光素子であり、高輝度発光可能であることが
確認された。
As is clear from the above examples and comparative examples, in the semiconductor light emitting device manufactured according to the present invention, the crystal quality of each layer is improved due to the high crystal quality of the underlayer, and the dislocation amount is reduced. It can be seen that the luminous efficiency and the excitation efficiency are improved by the synergistic effect of the effect described above and the effect of improving the heat dissipation characteristic of the AlN underlayer, and high-luminance light emission is realized. Therefore, it was confirmed that the semiconductor light emitting device of the example is a highly efficient semiconductor light emitting device and can emit light with high brightness as compared with the semiconductor light emitting device of the comparative example.

【0064】以上、具体例を挙げながら、本発明を発明
の実施の形態に即して詳細に説明してきたが、本発明は
上記内容に限定されるものではなく、本発明の範疇を逸
脱しない限りにおいてあらゆる変形や変更が可能であ
る。
Although the present invention has been described in detail with reference to the embodiments of the invention with reference to specific examples, the present invention is not limited to the above contents and does not depart from the scope of the present invention. All modifications and changes are possible as long as possible.

【0065】例えば、基板に窒化処理を加えたり、III
族原料による基板の前処理などを行なうこともできる。
また、下地層の組成を連続的に変化させたり、成膜条件
を段階に分けて変化させたりすることも可能である。さ
らに、導電層や発光層などの結晶性をさらに向上させる
目的で、下地層と導電層との間などにバッファ層やひず
み超格子などの多層積層構造を温度、流量、圧力、原料
供給量、及び添加ガスなどの成長条件を変化させること
により、挿入することもできる。また、発光層下方のn
層側にn−AlGaNクラッドを挿入しても良い。各層
の成膜については、同一の成膜装置で行う必要はなく、
別の装置を使用しても良い。
For example, nitriding treatment may be applied to the substrate, or III
Pretreatment of the substrate with a group material can also be performed.
It is also possible to change the composition of the underlayer continuously or to change the film forming conditions in stages. Further, for the purpose of further improving the crystallinity of the conductive layer or the light emitting layer, a multilayer laminated structure such as a buffer layer or a strained superlattice is provided between the underlayer and the conductive layer, such as temperature, flow rate, pressure, raw material supply amount, Also, it can be inserted by changing the growth conditions such as the additive gas. In addition, n below the light emitting layer
An n-AlGaN cladding may be inserted on the layer side. It is not necessary to perform film formation for each layer in the same film forming apparatus.
Other devices may be used.

【0066】また、上記下地層は、Ge、Si、Mg、
Zn、Be、P、及びBなどの添加元素を含有すること
もできる。さらに、意識的に添加した元素に限らず、成
膜条件などに依存して必然的に取り込まれる微量元素、
並びに原料、反応管材質に含まれる微量不純物を含むこ
ともできる。
The underlayer is made of Ge, Si, Mg,
Additional elements such as Zn, Be, P, and B can also be contained. Furthermore, not only the elements that were intentionally added, but trace elements that are inevitably incorporated depending on the film formation conditions,
In addition, trace amounts of impurities contained in the raw materials and reaction tube materials may be included.

【0067】また、本発明の半導体発光素子は、上述し
たPIN型の半導体発光素子のみならず、あらゆる型の
半導体発光素子に対して用いることができる。
The semiconductor light emitting device of the present invention can be used not only for the PIN type semiconductor light emitting device described above, but also for any type of semiconductor light emitting device.

【0068】[0068]

【発明の効果】以上説明したように、本発明の半導体発
光素子は、Alを含み、低転位密度の高結晶品質の窒化
物半導体から下地層を構成しているため、従来のような
バッファ層を必要とせずに、基板との格子定数差を補完
して導電層や発光層などのエピタキシャル成長を可能と
する。さらには、下地層の高結晶品質に基づいて前記導
電層や前記発光層などの結晶性を改善し、低転位化する
ことができる。
As described above, in the semiconductor light emitting device of the present invention, since the underlayer is composed of a nitride semiconductor containing Al and having a low dislocation density and a high crystal quality, a conventional buffer layer is used. It is possible to supplement the lattice constant difference with the substrate and to grow the conductive layer and the light emitting layer epitaxially without the need for Further, the crystallinity of the conductive layer, the light emitting layer and the like can be improved and the dislocations can be reduced based on the high crystal quality of the underlayer.

【0069】この結果、本発明の半導体発光素子は、低
転位密度の窒化物半導体層群から構成される発光素子構
造を有するようになるため、実際の使用において、発光
効率を向上させることができる。
As a result, the semiconductor light emitting device of the present invention has a light emitting device structure composed of a group of nitride semiconductor layers having a low dislocation density, so that the luminous efficiency can be improved in actual use. .

【図面の簡単な説明】[Brief description of drawings]

【図1】従来の半導体発光素子の一例を示す構成図であ
る。
FIG. 1 is a configuration diagram showing an example of a conventional semiconductor light emitting device.

【図2】本発明の半導体発光素子の一例を示す構成図で
ある。
FIG. 2 is a configuration diagram showing an example of a semiconductor light emitting device of the present invention.

【図3】本発明の半導体発光素子の他の例を示す構成図
である。
FIG. 3 is a configuration diagram showing another example of the semiconductor light emitting device of the present invention.

【図4】半導体発光素子の発光特性を示すグラフであ
る。
FIG. 4 is a graph showing emission characteristics of a semiconductor light emitting device.

【図5】リッジ型のGaN膜からの誘導放出出力と励起
光強度との関係を示すグラフである。
FIG. 5 is a graph showing the relationship between stimulated emission output from a ridge-type GaN film and excitation light intensity.

【符号の説明】[Explanation of symbols]

1,11,21 基板、2 バッファ層、3,13,2
3 下地層、4,14,24 n型導電層、5,15,
25 発光層、6,16 p型クラッド層、7,17,
27 p型導電層、8,18,28 n型電極、9、1
9,29 p型電極、10,20,30 半導体発光素
1,11,21 substrate, 2 buffer layers, 3,13,2
3 underlayer, 4, 14, 24 n-type conductive layer, 5, 15,
25 light emitting layer, 6,16 p-type cladding layer, 7, 17,
27 p-type conductive layer, 8, 18, 28 n-type electrode, 9, 1
9,29 p-type electrode, 10,20,30 semiconductor light emitting device

───────────────────────────────────────────────────── フロントページの続き (72)発明者 小田 修 愛知県名古屋市瑞穂区須田町2番56号 日 本碍子株式会社内 (72)発明者 江川 孝志 愛知県名古屋市昭和区小桜町2−14 柳荘 6 Fターム(参考) 5F041 AA40 CA05 CA34 CA40 CA46 CA65 5F073 AA13 AA74 CA07 CB05 CB07 DA05 DA35 EA29    ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Oda Osamu             2-56, Sudacho, Mizuho-ku, Nagoya-shi, Aichi             Inside Hon insulator Co., Ltd. (72) Inventor Takashi Egawa             2-14 Kozakura-cho, Showa-ku, Nagoya-shi, Aichi Prefecture             6 F-term (reference) 5F041 AA40 CA05 CA34 CA40 CA46                       CA65                 5F073 AA13 AA74 CA07 CB05 CB07                       DA05 DA35 EA29

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】所定の基板上において、窒化物半導体から
なる下地層と、窒化物半導体層群を含む発光素子構造と
を具える半導体発光素子であって、 前記下地層を構成する前記窒化物半導体は、少なくとも
Alを含むとともに、転位密度が1011/cm以下で
あり、前記発光素子構造を構成する前記窒化物半導体層
群は、前記下地層を構成する前記窒化物半導体よりも少
ない含有量でAlを含むとともに、転位密度が1×10
10/cm以下であることを特徴とする、半導体発光
素子。
1. A semiconductor light emitting device comprising a base layer made of a nitride semiconductor and a light emitting device structure including a group of nitride semiconductor layers on a predetermined substrate, wherein the nitride forming the base layer. The semiconductor contains at least Al and has a dislocation density of 10 11 / cm 2 or less, and the nitride semiconductor layer group forming the light emitting device structure contains less than the nitride semiconductor forming the underlayer. Al is contained in an amount, and the dislocation density is 1 × 10
A semiconductor light-emitting device characterized by having a density of 10 / cm 2 or less.
【請求項2】前記下地層を構成する前記窒化物半導体
の、全III族元素に対するAl含有量が50原子%以上
であることを特徴とする、請求項1に記載の半導体発光
素子。
2. The semiconductor light emitting device according to claim 1, wherein the nitride semiconductor forming the underlayer has an Al content of 50 atomic% or more with respect to all group III elements.
【請求項3】前記下地層を構成する前記窒化物半導体
は、AlNであることを特徴とする、請求項2に記載の
半導体発光素子。
3. The semiconductor light emitting device according to claim 2, wherein the nitride semiconductor forming the underlayer is AlN.
【請求項4】前記下地層を構成する前記窒化物半導体
は、MOCVD法により1100℃以上の温度で形成さ
れたことを特徴とする、請求項1〜3のいずれか一に記
載の半導体発光素子。
4. The semiconductor light emitting device according to claim 1, wherein the nitride semiconductor forming the underlayer is formed by MOCVD at a temperature of 1100 ° C. or higher. .
【請求項5】前記発光素子構造を構成する前記窒化物半
導体層群の、全III族元素に対するGa含有量が80%
以上であることを特徴とする、請求項1〜4いずれか一
に記載の半導体発光素子。
5. The Ga content of all the group III elements in the nitride semiconductor layer group constituting the light emitting device structure is 80%.
It is above, The semiconductor light-emitting device as described in any one of Claims 1-4 characterized by the above-mentioned.
【請求項6】前記発光素子構造を構成する前記窒化物半
導体層群は、n型導電層、p型導電層、及び発光層を含
み、前記発光層は、前記基板上において前記n型導電層
及び前記p型導電層で挟まれるようにして位置すること
を特徴とする、請求項1〜5いずれか一に記載の半導体
発光素子。
6. The nitride semiconductor layer group forming the light emitting device structure includes an n-type conductive layer, a p-type conductive layer, and a light emitting layer, and the light emitting layer is the n type conductive layer on the substrate. The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device is located so as to be sandwiched between the p-type conductive layer and the p-type conductive layer.
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* Cited by examiner, † Cited by third party
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US9343641B2 (en) 2011-08-02 2016-05-17 Manutius Ip, Inc. Non-reactive barrier metal for eutectic bonding process
US9012939B2 (en) 2011-08-02 2015-04-21 Kabushiki Kaisha Toshiba N-type gallium-nitride layer having multiple conductive intervening layers
US20130032810A1 (en) 2011-08-03 2013-02-07 Bridgelux, Inc. Led on silicon substrate using zinc-sulfide as buffer layer
US8564010B2 (en) 2011-08-04 2013-10-22 Toshiba Techno Center Inc. Distributed current blocking structures for light emitting diodes
US8686430B2 (en) 2011-09-07 2014-04-01 Toshiba Techno Center Inc. Buffer layer for GaN-on-Si LED
US8698163B2 (en) 2011-09-29 2014-04-15 Toshiba Techno Center Inc. P-type doping layers for use with light emitting devices
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US8664679B2 (en) 2011-09-29 2014-03-04 Toshiba Techno Center Inc. Light emitting devices having light coupling layers with recessed electrodes
US20130082274A1 (en) 2011-09-29 2013-04-04 Bridgelux, Inc. Light emitting devices having dislocation density maintaining buffer layers
US9178114B2 (en) 2011-09-29 2015-11-03 Manutius Ip, Inc. P-type doping layers for use with light emitting devices

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0964477A (en) 1995-08-25 1997-03-07 Toshiba Corp Semiconductor light emitting element and its manufacture
TW418549B (en) * 1998-06-26 2001-01-11 Sharp Kk Crystal growth method for nitride semiconductor, nitride semiconductor light emitting device, and method for producing the same
KR20010029852A (en) 1999-06-30 2001-04-16 도다 다다히데 Group ⅲ nitride compound semiconductor device and producing method therefor
US6596079B1 (en) * 2000-03-13 2003-07-22 Advanced Technology Materials, Inc. III-V nitride substrate boule and method of making and using the same
JP3626423B2 (en) 2000-05-22 2005-03-09 日本碍子株式会社 Photonic device manufacturing method
US6495894B2 (en) * 2000-05-22 2002-12-17 Ngk Insulators, Ltd. Photonic device, a substrate for fabricating a photonic device, a method for fabricating the photonic device and a method for manufacturing the photonic device-fabricating substrate
US6469320B2 (en) * 2000-05-25 2002-10-22 Rohm, Co., Ltd. Semiconductor light emitting device
US6680959B2 (en) * 2000-07-18 2004-01-20 Rohm Co., Ltd. Semiconductor light emitting device and semiconductor laser
US6649942B2 (en) * 2001-05-23 2003-11-18 Sanyo Electric Co., Ltd. Nitride-based semiconductor light-emitting device

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US8664638B2 (en) 2009-08-28 2014-03-04 Seoul Opto Device Co., Ltd. Light-emitting diode having an interlayer with high voltage density and method for manufacturing the same

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