JP2003228995A - Method and device for analyzing defect of measured device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To analyze retrieval of various kinds of defect items by simplifying setting of analysis conditions. <P>SOLUTION: This device has a plurality of kinds of patterns for retrieving a defective cell, a data storage part for analyzation 203 in which a retrieval area table is stored, a ROM 201 in which an application program for analyzing defect is stored, and a CPU 200 by which defective data of a device 30 to be measured are taken in by performing the application program for analyzing defect, they are stored in a data storage section for analysis, while in analyzing defect of the device to be measured, addresses of defective cells in each address in the retrieval area table are obtained by referring to the defective data, and it is tested for each defect item whether a fault pattern in the device to be measured coincides with the specified pattern for retrieving a defect cell or not by overlapping the pattern for retrieving a defective cell specified for the noticed cell in the retrieval area table to the cell on the retrieval area table. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure analysis method and apparatus for a device under test such as a memory IC or a logic IC.

[0002]

2. Description of the Related Art Defective data and path data can be obtained from a measurement result of an integrated circuit tester (IC tester) of a device under test such as a memory IC or a logic IC. By analyzing the pattern of the acquired failure data, it is possible to analyze what causes the failure.

A defective cell search pattern (pattern 1) used in conventional defect analysis of a device under test,
FIG. 9 shows an example of a search area table showing the relationship between the address of each cell in the search area for performing the defect search of the device under test and the defective cell search pattern used for the defect search in the cell specified by each address. Show. In pattern 1, t indicates the position of the defective cell (defective bit) to be searched, and f indicates the position of the cell that is the defective condition.

In the conventional failure analysis of the device under test, as shown in FIG. 9, the pattern for searching the fail information (defective data) of the IC is one kind of pattern 1, and the pattern 1 is each cell of interest in the search area table. When the cell adjacent to the target cell in the device under test is continuously failing by superposing the search area table and the pattern 1 on the basis of (defective cell to be searched), "adjacent bit fail" is given as a failure item. I was aware.

[0005]

However, recently,
As the circuit configuration of the IC has become complicated, there has been a problem that a simple and continuous defect data search of adjacent bits cannot sufficiently analyze the defect of the device under test.
For this reason, the cause of the failure of the device under test cannot be specified in detail, and failure analysis corresponding to the type of IC or the failure item to be searched cannot be performed.

The present invention has been made in view of the above circumstances, and the number of types of search patterns is increased in order to search for defective bit shape data having complicated bits, and the number of types of search patterns is increased, thereby making it possible to obtain analysis conditions. An object of the present invention is to provide a failure analysis method and apparatus for a device under test, which can simplify setting and analyze a search for many types of failure items.

[0007]

In order to achieve the above object, the invention described in claim 1 tests a device under test by an integrated circuit test apparatus, and obtains defective data of the device under test by the test. In addition, a plurality of types of defective cell search patterns used to search for defective cells of the device under test, the address of each cell in the search area for performing a defect search of the device under test, and the cell specified by each address A search area table indicating a relationship with any of the plurality of types of defective cell search patterns used for defect search is created for each defect item of the device under test, and the search is performed during failure analysis of the device under test. The address of the defective cell at each address in the area table is acquired by referring to the defective data acquired by the above test, In addition, the defective cell search pattern specified for the target cell in the search area table is overlapped on the search area table with the target cell as a reference, and the failure pattern in the device under test is the specified failure. It is characterized in that it is inspected for each defective item whether or not it matches the cell search pattern.

The invention described in claim 2 is the same as claim 1.
In the method of analyzing a failure of a device under test according to the above item 3, the defective cell search pattern and the search area table are used as parts when the failure of the device under test is analyzed.

The invention described in claim 3 is the same as claim 1
In the method of analyzing a failure of a device under test according to the item [4], when the failure of the device under measurement is analyzed, the defective cell search pattern and the search area table which are made into parts are used in an inverted form.

The invention according to claim 4 is the same as claim 1
In the method of analyzing a failure of a device under test as described in (1), when the failure of the device under measurement is analyzed, the defective cell search pattern and the search area table which are made into parts are used in a vertically inverted form.

The invention described in claim 5 is the same as claim 1.
In the failure analysis method for a device under test described in (1), when the device under test is analyzed for failure, the defective cell search pattern and the search area table that have been made into parts are used after being vertically inverted and then horizontally inverted. And

According to the invention of claim 6, the device under test created for each defective item based on the defective data of the device under test acquired by testing the device under test by the integrated circuit test apparatus. A plurality of types of defective cell search patterns used to search for defective cells, an address of each cell in a search area for performing a defect search of the device under test, and a plurality of cells used for defect search in a cell specified by each address First storage means for storing a search area table showing a relationship with any one of the defective cell search patterns, and a failure analysis application program for performing a failure analysis of the device under test are stored. Executes second storage means and the failure analysis application program stored in the second storage means. In this way, the failure data of the device under test acquired by performing the test of the device under test is fetched and stored in the first storage means, and at the time of failure analysis of the device under test, each item in the search area table is read. The address of the defective cell in the address is acquired and stored by referring to the defective data acquired by the test, and the defective cell search pattern designated for the target cell in the search area table is stored on the search area table. Processing means for inspecting, for each of the defective items, whether or not the failure pattern of the device under test that overlaps with the target cell matches the specified defective cell search pattern. .

The invention according to claim 7 is the same as claim 6
In the defect testing apparatus for a device under test according to claim 7, the defective cell search pattern and the search area table are divided into parts and stored in the first storage means, and the processing means includes a defect of the device under test. At the time of analysis, the device under test is inspected by using the defective cell search pattern and the search area table which have been made into parts.

The invention described in claim 8 is the same as claim 6.
In the device under test for measuring a device under test according to claim 7, the processing means uses the device-under-test device in a form in which the defective cell search pattern and the search area table that have been made into parts at the time of failure analysis of the device under test are inverted. It is characterized by inspecting.

The invention according to claim 9 is the same as claim 6
In the defect testing apparatus for a device under test according to claim 7, the processing means uses a pattern of a defective cell search and a search area table, which have been made into parts at the time of failure analysis of the device under test, in a vertically inverted form to be measured. Characterized by inspecting the device.

According to a tenth aspect of the present invention, in the defect testing apparatus for a device under test according to the sixth aspect, the processing means searches for the defective cell that has been made into the component when the device under test is analyzed for defects. The device to be measured is inspected by vertically inverting the use pattern and the search area table and then using the horizontally inverted form.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the configuration of a failure analysis apparatus for a device under test according to an embodiment of the present invention. The failure analysis apparatus for a device under test according to the embodiment of the present invention,
Test the device under test with the integrated circuit test equipment,
The defect data of the device under test is acquired by the test, a plurality of types of defective cell search patterns used for searching for defective cells of the device under test, and each cell in the search area for performing the defect search of the device under test. An address and a search area table showing a relationship with any of the plurality of types of defective cell search patterns used for defective search in cells specified by each address, and creating for each defective item of the device under test, During the failure analysis of the device under test, the address of the defective cell at each address in the search area table is acquired and stored by referring to the defective data acquired by the test, and at the same time, the target cell is searched in the search area table. The designated defective cell search pattern is searched for on the search area table. A failure analysis method for a device under test, wherein the failure pattern in the device under test is checked for each of the defective items to determine whether or not the failure pattern in the device under test overlaps with the specified defective cell search pattern. It is a device for carrying out.

In FIG. 1, a failure analysis apparatus 20 for a device under test according to this embodiment includes a CPU 200 and a ROM.
201, RAM 202, and analysis data storage unit 203
And an input / output (I / O) interface 204, and an input operation unit 205 for inputting various data and performing various settings. CPU200, ROM201, RAM2
02, the analysis data storage unit 203, the input / output (I / O) interface 204, and the input operation unit 205 are mutually connected via a bus 210. Reference numeral 10 denotes an integrated circuit test apparatus, and the integrated circuit test apparatus 10 is a device under test 3
Device under test 30 obtained by performing 0 test
The failure data of is written in the fail memory 100.

The ROM 201 stores various programs including a failure analysis application program for performing failure analysis of the device under test 30 and fixed data. The RAM 202 has a work area used when the CPU 200 performs arithmetic processing, and a memory area for temporarily storing data processed by the CPU 200.

In the analysis data storage section 203, the device under test created for each defective item based on the defective data of the device under test 30 obtained by testing the device under test 30 by the integrated circuit test apparatus 10. A plurality of types of defective cell search patterns used to search for defective cells of 30 and addresses of each cell in a search area for performing a defective search of the device under test 30 and a cell specified by each address are used for defective search. A search area table indicating a relationship with any of a plurality of types of defective cell search patterns is stored.

By executing the failure analysis application program, the CPU 200 fetches the failure data of the device under test 30 written in the fail memory 100 of the integrated circuit test apparatus 10 and stores it in the analysis data storage unit 203. During the failure analysis of the device under test 30, the address of the defective cell at each address in the search area table is acquired and stored by referring to the defective data, and at the same time the address of the target cell is designated in the search area table. The defective cell search pattern is overlaid on the search area table with the target cell as a reference, and it is inspected for each defective item whether or not the failure pattern in the device under test 30 matches the designated defective cell search pattern. To do.

The CPU 200 is a processing means of the present invention,
M201 corresponds to the second storage unit of the present invention, and the analysis data storage unit 203 corresponds to the first storage unit of the present invention. Here, FIG. 4 shows three types of defective cell search patterns for searching adjacent bit defects of the memory device as the device under test 30 and a search area table example. Here, the "adjacent bit defect" is one of the defect items of the device under test 30, and means that the adjacent cell is defective.

Even if there is only one defect name to be retrieved, the shape of the defect retrieval pattern differs depending on the position of the cell to be retrieved on the retrieval area table. Search area table (Fig. 4 (A))
4 is the pattern number of the search pattern used in the defect search shown in FIG. 4B, and three different patterns 1 to 3 are provided as the defective cell search pattern (FIG. 4B). used.

In Patterns 1 to 3, "t" indicates the position of a defective bit (defective cell) to be searched, and "f" indicates the position of a bit (cell) which is a defective condition. Fails at the "@" position are not subject to bad conditions. When it is determined that the search conditions match, that is, when the defective cell search pattern specified for the target cell in the search area table is overlaid on the search area table with the target cell as the reference, the defective cell search is performed. If the search pattern and the search area table match, there is a defective item,
Bad data after the search is deleted.

Next, a procedure for searching for a defect of the device under test by the device for analyzing a defect of the device under test according to the present embodiment will be described with reference to the flowcharts of FIGS. First, a test is performed on the device under test 30 by the integrated circuit test apparatus 10, and the fail data of the cell in the device under test 30 acquired by this test is associated with the address of the device under test 30 and the fail memory 100.
To store. After that, by operating the input operation unit 205, the CPU 200 executes the failure analysis application program, and writes the failure data (corresponding to the address) of the device under test 30 written in the fail memory 100 of the integrated circuit test apparatus 10. The obtained data) is taken in via the input / output interface 204 and stored in the analysis data storage unit 203 (step 300).

Next, the user creates a defective cell search pattern and a search area table for each defective item suitable for the device under test 30 based on the test result of the device under test 30 by the integrated circuit test apparatus 10 for analysis. The data is stored in the data storage unit 203 (step 301). Further, the user sets the search order of a plurality of defective items when searching for a failure in the device under test 30 using the input operation unit 205 (step 302), and sets the search direction on the search area table (step 303). . Defective items are "adjacent bit defect" and "word line crossing defect".
Etc.

Then, when the user operates the input operation unit 205 to instruct to start the defect search of the device under test 30, the CPU 200 starts the execution of the defect analysis application program stored in the ROM 201, and the device under test is measured. The defect search of the device 30 is started (step 304). When the defect search is started, first, the device under test 3 stored in the analysis data storage unit 203 is detected.
The defective data of 0 is searched (step 305), and the address of the defective cell (failed cell) is acquired (step 306).

Next, a defective cell search pattern is acquired from the pattern number designated at the address of the defective cell in the search area table (step 30).
7) It is determined whether or not the target cell matches the defective cell search pattern. That is, the defective cell that has failed, for example, the position of the cell at the address X = 1, Y = 1 in the search area table in FIG. The defective cell search pattern is overlaid on the search area table to search the defective cell for the defective cell depending on whether or not there is a fail cell at all the positions of "f" where pattern 3 is overlaid in the search area table. It is determined whether the pattern matches (step 308). In this case, since they do not match, step 305
The process returns to.

If it is determined in step 308 that the target cell matches the defective cell search pattern, it is located on the search area table in correspondence with the positions of "t" and "f" in the pattern. The address of the defective cell is acquired, and the defective data of the cell at that address in the analysis data storage unit 203 is deleted. Then
It is determined whether the search has been completed for all addresses in the search area table (step 310). If the search has not been completed, the process returns to step 305.

On the other hand, when it is determined in step 310 that the search has been completed for all addresses in the search area table, it is determined whether the search has been completed for all defective items (step 311). If it is determined in step 311 that the search has not been completed for all defective items,
The process returns to step 305 to execute the same process as described above. If it is determined in step 311 that the search has been completed for all defective items, the failure search is ended.

FIG. 5 shows an example of actual fault search. Figure 5
FIG. 5A shows the contents of the search area table, and FIG. 5B shows the contents of pattern 1 (the same as that shown in FIG. 4) of the defective cell search patterns. In the figure, when a failing bit (cell position) on the search area table is searched in the X direction, an address where X is 1 and Y is 1 is searched. As described in the example of FIG. 4, the failure search of this position is performed in the pattern 3, but they do not match, and the next fail position (address) in the search area table is searched again. Here, the “failed cell” (failed cell) is a cell in which the data written by the integrated circuit device 10 during the test and the data read out do not match.

When the search is performed again, X is 2 in the next fail bit in the search area table.
An address with Y = 2 is searched, and since the fail shape matches the pattern 1 which is the defective cell search pattern designated by this address, it means that there is one defective item being searched.

The defective cell search pattern used for the failure search at each address in the search area table regularly changes depending on the position of the cell in the device under test 30. FIG. 6 shows an example of a combination of four types of search area tables showing the pattern numbers of the defective cell search patterns used for the failure search of each cell in each search area inside the device under test 30, and FIG. 7 shows each search. An example of the combination of the defective cell search patterns used for the areas will be shown.

The inside of the device under test 30 is divided into, for example, four search areas (A, B, C, D), and based on the search area table created for the search area A, the search area used for the search area B is used. As the table, a table in which the contents of the search area table used for the search area A are horizontally inverted is used. Also,
For the search area A, the search area C is a table in which the contents of the search area table used for the search area A are vertically inverted, and for the search area D, the contents of the search area table used for the search area A. After vertically flipping, a table in the form of horizontally flipping is used.

In the conventional failure analysis method (or failure analysis apparatus) for the device under test, a search pattern must be set for each different search area, and when one search pattern exists in the search area A. Created three types of defective cell search patterns for the search areas B, C, and D, and performed a failure search for the device under test 30. In the embodiment of the present invention, the search conditions for the search areas B, C, D are not created, but the defective cell search pattern for the search area A is made into a component and three types of inversion directions are designated. Can be specified.

The basic search area table and defective cell search pattern are made into parts, and in each search area,
FIG. 8 shows the contents of the table for specifying the search area table and the bad cell search pattern to be used by specifying the contents of the reverse information for the basic search area table and the bad cell search pattern. As shown in the figure, it is possible to deal with all other search areas only by creating the search area table and the bad cell search pattern search area A.

In the present embodiment, a plurality of types of defective cell search patterns used to search for defective cells of the device under test, the address of each cell in the search area for performing the defect search of the device under test, and each address are specified. A search area table showing a relationship with any of the plurality of types of defective cell search patterns used for defective search in a cell to be searched, and the search information is obtained by using the partized data and inversion information. I try to simplify and search in a certain way. Therefore, according to the present embodiment, it is possible to significantly reduce the combination of search conditions, so that it is possible to perform defect analysis with few mistakes on the device under measurement. Further, since the search shape can be arbitrarily specified, detailed analysis can be performed. It becomes possible to do.

[0038]

EFFECTS OF THE INVENTION In the failure analysis inside an IC such as a memory device, 40 to 100 kinds of failure searches are performed. In the case of the defective pattern search of FIG. 8, 12 types of defective cell search patterns have to be described under the conventional search conditions, but in the present invention, it is possible to set only 3 types and inversion information as conditions. is there. As described above, according to the present invention, it is possible to significantly reduce the number of combinations of search conditions, so that it is possible to perform defect analysis with few mistakes on a device under test and to finely specify a search shape. It is possible to perform various analyzes.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a failure analysis apparatus for a device under test according to an embodiment of the present invention.

FIG. 2 is a flowchart showing the processing contents of the device under test failure analysis apparatus according to the embodiment of the present invention shown in FIG.

FIG. 3 is a flowchart showing the processing contents of a failure analysis apparatus for a device under test according to the embodiment of the present invention shown in FIG.

FIG. 4 is an explanatory diagram showing an example of a search area table and a defective cell search pattern used when performing a defect search of a device under test.

FIG. 5 is an explanatory diagram showing an example of a search area table and a defective cell search pattern used in actual defect search.

FIG. 6 is an explanatory diagram showing a combination example of four types of search area tables showing pattern numbers of defective cell search patterns used for failure search of each cell in each search area inside the device under test.

FIG. 7 is an explanatory diagram showing an example of a combination of defective cell search patterns used in each search area.

FIG. 8 shows the contents of a table for specifying a search area table and a bad cell search pattern to be used in each search area by designating the contents of reverse information for the basic search area table and the bad cell search pattern. FIG.

FIG. 9 is an explanatory view showing an example of a search area table and a defective cell search pattern used for conventional defect analysis of a device under test.

[Explanation of symbols]

10 ... Integrated circuit tester 20. Failure analysis device for device under test 30 ... Device to be measured 100 ... Fail memory 200 ... CPU 201 ... ROM 202 ... RAM 203 ... Data storage unit for analysis 204 ... I / O interface 205 ... Input operation unit

Claims (10)

[Claims] 1. A device under test is tested by an integrated circuit test apparatus, defective data of the device under test is acquired by the test, and a plurality of types of defective cell search used for searching for defective cells of the device under test are performed. Pattern and the address of each cell in the search area for performing a defect search of the device under test and one of the plurality of types of defective cell search patterns used for defect search in the cell specified by each address. A search area table shown is created for each defective item of the device under test, and at the time of failure analysis of the device under test, the address of the defective cell at each address in the search area table is referred to by the defective data acquired by the test. Acquired, stored, and specified for the cell of interest in the search area table. For each of the defective items, it is determined whether or not the failure pattern in the device under test is overlapped with the good cell search pattern on the search area table with reference to the cell of interest as a reference. A failure analysis method for a device under test characterized by inspecting. 2. The failure analysis method for a device under test according to claim 1, wherein the defect cell search pattern and the search area table are used as parts when the device under test is analyzed for defects. 3. The device under test according to claim 1, wherein the defective cell search pattern and the search area table, which have been made into components, are used in an inverted form when the device under test is analyzed for defects. Failure analysis method. 4. The device under test according to claim 1, wherein the defective cell search pattern and the search area table, which have been made into components, are used in a vertically inverted form when the device under test is analyzed for defects. Failure analysis method. 5. The defective cell search pattern and search area table, which have been made into parts, are used after being vertically inverted and then horizontally inverted when the device under test is analyzed for defects. Of device under test for failure analysis. 6. A plurality of types used for searching a defective cell of a device under test created for each defective item based on defect data of the device under test acquired by performing a test of the device under test with an integrated circuit test apparatus. Of the defective cell search pattern, and the plurality of types of defective cell search patterns used for defect search in the address of each cell in the search area for performing the defect search of the device under test and the cell specified by each address A first storage unit that stores a search area table that indicates the relationship between the two; a second storage unit that stores a failure analysis application program for performing a failure analysis of the device under test; By executing the failure analysis application program stored in the second storage means. Address data of a defective cell at each address in the search area table at the time of defect analysis of the device to be measured. Is stored by referring to the defective data obtained by the test, and the defective cell search pattern specified for the target cell in the search area table is stored in the search area table based on the target cell. And a processing unit that inspects for each defective item whether or not the failure pattern in the device under test matches the specified defective cell search pattern. Analyzer. 7. The defective cell search pattern and the search area table are made into parts and stored in the first storage means, and the processing means is made into the parts at the time of failure analysis of the device under test. 7. The device under test for testing a device under test according to claim 6, wherein the device under test is inspected by using a pattern for searching a defective cell and a search area table. 8. The processing means inspects the device under test by using the defective cell search pattern and the search area table, which have been made into parts, in an inverted form when the device under test is analyzed for defects. The defect test apparatus for a device under test according to claim 6. 9. The processing means inspects the device under test by using the defective cell search pattern and the search area table, which have been made into parts, in a vertically inverted form at the time of failure analysis of the device under test. The defect test apparatus for a device under test according to claim 6. 10. The processing means inspects the device under test by vertically inverting and then horizontally inverting the defective cell search pattern and the search area table, which have been made into parts, during the failure analysis of the device under test. The defect testing apparatus for a device under test according to claim 6, wherein: