JP2003224071A - Manufacturing method for nitride based semiconductor and nitride semiconductor element using the same - Google Patents

Manufacturing method for nitride based semiconductor and nitride semiconductor element using the same

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Publication number
JP2003224071A
JP2003224071A JP2002019655A JP2002019655A JP2003224071A JP 2003224071 A JP2003224071 A JP 2003224071A JP 2002019655 A JP2002019655 A JP 2002019655A JP 2002019655 A JP2002019655 A JP 2002019655A JP 2003224071 A JP2003224071 A JP 2003224071A
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JP
Japan
Prior art keywords
substrate
buffer layer
nitride
layer
based semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002019655A
Other languages
Japanese (ja)
Inventor
Akihiko Ishibashi
明彦 石橋
Takeshi Sugawara
岳 菅原
Yasutoshi Kawaguchi
靖利 川口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
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Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2002019655A priority Critical patent/JP2003224071A/en
Publication of JP2003224071A publication Critical patent/JP2003224071A/en
Pending legal-status Critical Current

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  • Recrystallisation Techniques (AREA)
  • Semiconductor Lasers (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high quality nitride based semiconductor or an element constituted of the nitride based semiconductor not generating cracks on a Si substrate, and to provide the manufacturing method. <P>SOLUTION: An AlxGayInzN (0≤x≤1, 0≤y≤1, 0≤z≤1 and x+y+z=1) semiconductor layer 3 is grown by using an impurity added ZnO buffer layer 2 on a Si substrate 1. Thus, a columnar polycrystalline ZnO buffer layer for which the (c) axis orientatability is high and a grain size in a horizontal direction is small within the (C) plane is formed, and a nitride based semiconductor single crystal layer less influenced by heat distortion from the Si substrate is manufactured on it. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は高密度光情報処理や
ディスプレー分野などへの応用が期待されている可視域
から紫外域の発振波長を有する半導体レーザ、照明用固
体光源に用いられる高効率紫外線発光ダイオード、高周
波/高出力トランジスター等の応用に用いられる窒化物
系半導体素子に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor laser having an oscillation wavelength in the visible region to ultraviolet region, which is expected to be applied to the fields of high-density optical information processing and displays, and high-efficiency ultraviolet rays used for a solid light source for illumination The present invention relates to a nitride-based semiconductor device used for applications such as light emitting diodes and high frequency / high power transistors.

【0002】[0002]

【従来の技術】V族元素に窒素(N)を有する窒化物半
導体は、そのバンドギャップの大きさや絶縁破壊電圧の
大きさ等から、可視域から紫外域の広い波長に発光帯を
有する短波長発光素子やハイパワー電子デバイスの材料
として有望視されている。中でも窒化物系半導体(Ga
N系半導体:AlxGayInzN(0≦x,y,z≦
1、x+y+z=1))は研究が盛んに行われ、青色発
光ダイオード(LED)、緑色LEDが実用化されてい
る。また、光ディスク装置の大容量化のために、400
nm帯に発振波長を有する半導体レーザが熱望されてお
り、窒化物系半導体を材料とする半導体レーザが注目さ
れ、現在では実用化レベルに達しようとしている。
2. Description of the Related Art Nitride semiconductors containing nitrogen (N) as a group V element have a short wavelength having an emission band in a wide wavelength range from the visible region to the ultraviolet region due to the size of the band gap and the breakdown voltage. It is regarded as a promising material for light emitting devices and high-power electronic devices. Above all, nitride-based semiconductors (Ga
N-based semiconductor: Al x Ga y In z N (0 ≦ x, y, z ≦
1, x + y + z = 1)) has been actively researched, and blue light emitting diodes (LEDs) and green LEDs have been put to practical use. Moreover, in order to increase the capacity of the optical disk device, 400
A semiconductor laser having an oscillation wavelength in the nm band has been eagerly awaited, and a semiconductor laser made of a nitride-based semiconductor has attracted attention, and at present, it is about to reach a practical level.

【0003】窒化物系半導体の結晶成長においては、現
在のところ良質でかつ大口径な窒化物系半導体バルク結
晶の作製が極めて困難であるために、サファイア、Si
C、Si等の異種基板を用いて有機金属気相成長法(M
OVPE法)等の手法を用いたヘテロエピタキシーが行
われている。ヘテロエピタキシーにおいては、各種基板
と窒化物系半導体との間に存在する格子定数や熱膨張係
数の不整合による界面での欠陥の発生を抑制するため
に、通常、窒化物系半導体を成長する温度に対し成長温
度を低くして作製した多結晶AlGaN系バッファ層、
あるいは通常の窒化物系半導体を成長する温度において
AlN単結晶またはGaN/AlN単結晶からなる超格
子バッファ層を堆積し、基板とエピ結晶との間に発生す
る応力を緩和する等の手法が開示されている。
In crystal growth of a nitride-based semiconductor, it is extremely difficult at present to produce a high-quality, large-diameter nitride-based semiconductor bulk crystal, so that sapphire and Si are used.
Metalorganic vapor phase epitaxy (M
Heteroepitaxy using a method such as the OVPE method) is performed. In heteroepitaxy, in order to suppress the occurrence of defects at the interface due to the mismatch of the lattice constant and the thermal expansion coefficient existing between various substrates and the nitride-based semiconductor, the temperature at which the nitride-based semiconductor is grown is usually set. A polycrystalline AlGaN-based buffer layer manufactured at a low growth temperature,
Alternatively, a method is disclosed in which a superlattice buffer layer made of AlN single crystal or GaN / AlN single crystal is deposited at a temperature at which a normal nitride-based semiconductor is grown, and stress generated between the substrate and the epicrystal is relaxed. Has been done.

【0004】特に、Si基板上に高品質な窒化物系半導
体が形成できれば、コスト、量産性等産業上極めて著し
い効果が期待され、様々な取り組みが為されている。
In particular, if a high-quality nitride semiconductor can be formed on a Si substrate, very significant industrial effects such as cost and mass productivity are expected, and various efforts have been made.

【0005】例えば、「Material Resea
rch Society Symposium Pro
ceedings Volume 449, p373
(1997 Material Research S
ociety)」には、(111)Si基板に対し電子
ビーム蒸着法またはレーザアブレーションMBE法によ
りZnO膜をデポした後、MOVPE法によりAlN、
GaNを順次積層し、GaN結晶を得る手法が開示され
ている。また、「第61回応用物理学会学術講演会講演
予稿集(2000年9月 北海道工業大学)4a−Y−
14」には、(001)Si基板上にRFマグネトロン
スパッター法を用いて柱状構造を有する多結晶ZnOを
堆積した後、ECR−MBE法を用いて多結晶GaNを
堆積する手法が開示されている。
[0005] For example, "Material Research"
rch Society Symposium Pro
ceedings Volume 449, p373
(1997 Material Research S
), a ZnO film is deposited on a (111) Si substrate by an electron beam evaporation method or a laser ablation MBE method, and then AlN is deposited by a MOVPE method.
A method of sequentially stacking GaN to obtain a GaN crystal is disclosed. In addition, “Proceedings of 61st JSAP Academic Lecture Meeting (September 2000, Hokkaido Institute of Technology) 4a-Y-
14 ”discloses a method of depositing polycrystalline ZnO having a columnar structure on a (001) Si substrate by using an RF magnetron sputtering method and then depositing polycrystalline GaN by using an ECR-MBE method. .

【0006】[0006]

【発明が解決しようとする課題】しかしながら、Siの
熱膨張係数と窒化物系半導体の熱膨張係数を比較する
と、前者の方が小さく、Si基板を加熱して窒化物系半
導体単結晶を成長し、成長後室温に降温すると、熱膨張
不整に起因して窒化物系半導体結晶に引っ張り応力が加
わり、結晶に反りやクラックが発生する。通常、GaN
を単結晶で成長すると、約1μmでクラックが発生す
る。
However, comparing the coefficient of thermal expansion of Si with the coefficient of thermal expansion of a nitride semiconductor, the former is smaller, and the Si substrate is heated to grow a nitride semiconductor single crystal. When the temperature is lowered to room temperature after growth, tensile stress is applied to the nitride-based semiconductor crystal due to the thermal expansion irregularity, and the crystal is warped or cracked. Usually GaN
When is grown as a single crystal, cracks occur at about 1 μm.

【0007】ZnOはGaNと格子定数が近く、GaN
のバッファ層として有望と考えられているが、ZnOの
配向性を上げて結晶性を向上させると、Si基板の熱歪
みがGaNに直接加えられることになり、クラックの問
題が回避できない。例えば、従来行われてきた技術で
は、図3に示すように、(111)Si基板1上に、柱
状多結晶のZnOバッファ層6を堆積し、これにGaN
初期成長核7を堆積し、続けて成長を行いGaN層8を
得る。この方法では、基板に垂直な方向のc軸配向性を
上げるために、基板をZnOが分解蒸発しない程度に高
温加熱する必要性がり、この場合、かなりの程度(柱状
多結晶の膜厚程度)の横方向成長が起こるために、Ga
N初期成長核7のそれぞれにおいて、ZnOバッファ層
6を通してSi基板1とのコヒーレンシーが高くなり、
結局Si基板1の熱歪みがGaN層8に加わることにな
るので、GaN層8にクラックが発生する。
ZnO has a lattice constant close to that of GaN.
Although it is considered to be promising as a buffer layer, if the crystallinity is improved by increasing the orientation of ZnO, the thermal strain of the Si substrate is directly applied to GaN, and the problem of cracks cannot be avoided. For example, in the conventional technique, as shown in FIG. 3, a columnar polycrystalline ZnO buffer layer 6 is deposited on a (111) Si substrate 1, and GaN is deposited on the ZnO buffer layer 6.
Initially grown nuclei 7 are deposited and then grown to obtain a GaN layer 8. In this method, in order to improve the c-axis orientation in the direction perpendicular to the substrate, it is necessary to heat the substrate at a high temperature such that ZnO is not decomposed and evaporated. In this case, the substrate is heated to a considerable extent (the thickness of the columnar polycrystal). Ga of the Ga
In each of the N initial growth nuclei 7, the coherency with the Si substrate 1 is increased through the ZnO buffer layer 6,
Eventually, the thermal strain of the Si substrate 1 will be applied to the GaN layer 8, and the GaN layer 8 will be cracked.

【0008】本発明は以上のような問題を鑑みてなされ
たもので、異種基板、特に量産性、生産性に優れた、S
i基板上にクラックのない高品質な窒化物系半導体単結
晶層を作製する方法及びその構造を提供するものであ
る。
The present invention has been made in view of the above problems, and it is an S-type substrate of a different type, particularly excellent in mass productivity and productivity.
Provided are a method and a structure for producing a high quality nitride-based semiconductor single crystal layer without cracks on an i substrate.

【0009】[0009]

【課題を解決するための手段】本発明の窒化物系半導体
の製造方法は、Si基板上に不純物添加したZnOバッ
ファ層を用いてAlxGayInzN(0≦x≦1, 0
≦y≦1, 0≦z≦1, x+y+z=1)系半導体
を成長することを特徴とする。特に、不純物が少なくと
もIn,Ga,Alのいずれかで構成されることを特徴
とする。ZnOバッファ層に不純物添加することによ
り、従来の不純物を添加しないZnOバッファ層を用い
た場合に比べ、c軸配向性には優れるが横方向成長の程
度は小さい、いわゆる縦/横比の大きい柱状多結晶Zn
Oバッファ層が得られ、基板の熱歪みをZnOバッファ
層上のGaNに加えないようにする。更に、Si基板の
熱膨張係数はZnOの熱膨張係数よりも大きく前記c軸
配向性が高くかつ縦/横比の大きい柱状多結晶ZnOバ
ッファ層に対し圧縮歪みをもたらすので、GaNに比べ
わずかに大きいZnOの格子定数はC面内で縮小される
ことになり、よりGaNのバルク格子定数に近くなるの
で、この効果を利用することによりGaNとZnOの格
子不整合を回避する。この場合、不純物添加したZnO
バッファ層を用いることにより、柱状多結晶ZnOバッ
ファ層の横方向成長を抑制することにより、ZnOの単
結晶性の高いドメインサイズを小さくしているので、S
i基板から熱歪みが前記バッファを通してGaNに加え
られることを回避する。
According to the method of manufacturing a nitride semiconductor of the present invention, an Al x Ga y In z N (0 ≦ x ≦ 1, 0) is formed by using an impurity-doped ZnO buffer layer on a Si substrate.
≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) based semiconductor is characterized by growing. In particular, the feature is that the impurities are composed of at least one of In, Ga, and Al. By adding impurities to the ZnO buffer layer, the columnar shape is excellent in c-axis orientation but has a small degree of lateral growth, that is, a columnar shape with a large vertical / horizontal ratio, as compared with the case of using a conventional ZnO buffer layer without adding impurities. Polycrystalline Zn
An O buffer layer is obtained, which prevents thermal strain of the substrate from being added to the GaN on the ZnO buffer layer. Further, the coefficient of thermal expansion of the Si substrate is larger than that of ZnO, and the columnar polycrystalline ZnO buffer layer having a high c-axis orientation and a large aspect / width ratio causes compressive strain. The large lattice constant of ZnO will be reduced in the C-plane, and it will be closer to the bulk lattice constant of GaN. Therefore, by utilizing this effect, the lattice mismatch between GaN and ZnO is avoided. In this case, ZnO doped with impurities
By using the buffer layer to suppress the lateral growth of the columnar polycrystalline ZnO buffer layer, the domain size of ZnO having high single crystallinity is reduced.
Avoid applying thermal strain from the i-substrate through the buffer to GaN.

【0010】また、本発明の窒化物系半導体素子は、S
i基板上に不純物添加したZnOバッファ層を用いて形
成されたAlxGayInzN(0≦x≦1,0≦y≦
1,0≦z≦1,x+y+z=1)系半導体から構成さ
れることを特徴とする。
The nitride semiconductor device of the present invention is S
Al x Gay y In z N (0 ≦ x ≦ 1, 0 ≦ y ≦ formed using an impurity-doped ZnO buffer layer on an i substrate
1, 0 ≦ z ≦ 1, x + y + z = 1) based semiconductor.

【0011】また、本発明の窒化物系半導体の製造方法
は、Si基板上に不純物添加したAl23バッファ層を
用いてAlxGayInzN(0≦x≦1,0≦y≦1,
0≦z≦1,x+y+z=1)系半導体を成長すること
を特徴とする。特に、不純物が少なくともSi,Geの
いずれかで構成されることを特徴とする。不純物添加に
よりc軸配向性が高くかつ縦/横比の大きい柱状多結晶
Al23バッファ層を作製し、この上のGaN層にSi
基板からの熱歪みを加えないようにすることは、前記Z
nOバッファ層と同様である。更に、ZnOバッファ層
の場合とは逆に、Si基板の熱膨張係数はAl23の熱
膨張係数よりも小さく、前記c軸配向性が高くかつ縦/
横比の大きい柱状多結晶Al23バッファ層に対し引っ
張り歪みをもたらすので、GaNに比べ小さいAl23
の格子定数はC面内で増大されることになり、よりGa
Nのバルク格子定数に近くなるので、この効果を利用す
ることにより、GaNとAl23の格子不整合を回避す
る。この場合、不純物添加したAl23バッファ層を用
いることにより、柱状多結晶Al23バッファ層の横方
向成長を抑制することにより、Al23の単結晶性の高
いドメインサイズを小さくしているので、Si基板から
熱歪みが前記バッファを通してGaNに加えられること
を回避する。
Further, in the method for manufacturing a nitride-based semiconductor of the present invention, Al x Ga y In z N (0 ≦ x ≦ 1,0 ≦ y is used by using an Al 2 O 3 buffer layer doped with impurities on a Si substrate. ≦ 1,
0 ≦ z ≦ 1, x + y + z = 1) -based semiconductor is grown. In particular, it is characterized in that the impurities are composed of at least Si or Ge. A columnar polycrystalline Al 2 O 3 buffer layer having a high c-axis orientation and a large aspect ratio is formed by adding impurities, and Si is formed on the GaN layer on the columnar polycrystalline Al 2 O 3 buffer layer.
Preventing thermal strain from the substrate is described in the above Z
It is similar to the nO buffer layer. Further, contrary to the case of the ZnO buffer layer, the coefficient of thermal expansion of the Si substrate is smaller than that of Al 2 O 3 , and the c-axis orientation is high and the longitudinal / longitudinal
Because results in tensile strain to a large columnar polycrystalline Al 2 O 3 buffer layer of the lateral ratio, small Al 2 O 3 compared to GaN
The lattice constant of is to be increased in the C-plane, and
Since it is close to the bulk lattice constant of N, the lattice mismatch between GaN and Al 2 O 3 is avoided by utilizing this effect. In this case, the Al 2 O 3 buffer layer doped with impurities is used to suppress the lateral growth of the columnar polycrystalline Al 2 O 3 buffer layer, thereby reducing the domain size of Al 2 O 3 having high single crystallinity. Therefore, thermal strain from the Si substrate is prevented from being applied to GaN through the buffer.

【0012】また、本発明の窒化物系半導体素子は、S
i基板上に不純物添加したAl23バッファ層を用いて
形成されたAlxGayInzN(0≦x≦1,0≦y≦
1,0≦z≦1,x+y+z=1)系半導体から構成さ
れることを特徴とする。
The nitride semiconductor device of the present invention is S
Al was formed with Al 2 O 3 buffer layer doped impurity i on the substrate x Ga y In z N (0 ≦ x ≦ 1,0 ≦ y ≦
1, 0 ≦ z ≦ 1, x + y + z = 1) based semiconductor.

【0013】[0013]

【発明の実施の形態】以下、本発明の実施の形態につい
て図面を用いて詳細に説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

【0014】本発明の窒化物系半導体の成長方法は有機
金属気相成長法(MOVPE)法に限定するものではな
く、ハイドライド気相成長法(H−VPE法)や分子線
エピタキシー法(MBE法)など、窒化物半導体層を成
長させるために、これまで提案されている全ての方法に
適用できる。また、MOVPE成長法において、成長圧
力は減圧から、大気圧、加圧(760Torr以上)(1
Torr=133.322Pa)いずれでも良く、各層において最適な
圧力に切りかえても良い。また、原料を基板に供給する
ためのキャリアガスは少なくとも窒素または水素等の不
活性ガスを含むガスで供給される。
The method for growing a nitride-based semiconductor of the present invention is not limited to the metal organic chemical vapor deposition (MOVPE) method, but may be a hydride vapor phase epitaxy method (H-VPE method) or a molecular beam epitaxy method (MBE method). ), Etc., can be applied to all the methods proposed so far for growing a nitride semiconductor layer. In addition, in the MOVPE growth method, the growth pressure ranges from reduced pressure to atmospheric pressure and pressure (760 Torr or more) (1
(Torr = 133.322 Pa), any pressure may be used, and the pressure may be switched to an optimum pressure in each layer. The carrier gas for supplying the raw material to the substrate is at least a gas containing an inert gas such as nitrogen or hydrogen.

【0015】また、本発明における窒化物系半導体と
は、V族元素に窒素を含む半導体のことであって、例え
ばV族元素にN以外にPやAsを含む場合においても適
用できる。
The nitride-based semiconductor in the present invention is a semiconductor containing nitrogen as a group V element, and can be applied, for example, when the group V element contains P or As in addition to N.

【0016】(実施例1)本発明のSi基板上に不純物
添加したZnOバッファ層を用いてAlxGayInz
(0≦x≦1,0≦y≦1,0≦z≦1,x+y+z=
1)系半導体を成長する方法について説明する。
Example 1 Using a ZnO buffer layer doped with impurities on the Si substrate of the present invention, Al x Ga y In z N
(0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z =
1) A method for growing a system semiconductor will be described.

【0017】図1に示すように(111)Si基板1上
にスパッタ法を用いてZnO:Alバッファ層2を膜厚
10nm堆積する。次に、MOVPE法を用いてAlG
aInN層3を成長する。ZnO:Alバッファ層2は
マグネトロンスパッタリング装置を用いてAlドープし
たZnOのターゲットを、ArとO2の混合ガスを導入
することによりスパッタリングする。基板温度は約30
0℃である。また、AlGaInN層3は減圧MOVP
E法を用い、基板を室温から加熱していく際に、約40
0℃から成長を始め、前記成長を行いながらAlGaI
nN層3を構成する組成に応じたより高い温度で前記A
lGaInN層3の単結晶を成長する。例えばAlGa
N層では約1080℃で、InGaN層では約800℃
の基板温度で成長する。約400℃から成長を行う理由
はZnO:Alバッファ層2の熱分解を回避するため
で、約400℃以上の基板温度になると前記ZnO:A
lバッファ層2は急激に分解しバッファ層が消失する。
ZnO:Alバッファ層2を堆積する際に、熱分解に対
する保護膜として例えばAlN膜を数原子層スパッタリ
ングしておいてもよい。
As shown in FIG. 1, a ZnO: Al buffer layer 2 is deposited to a thickness of 10 nm on a (111) Si substrate 1 by a sputtering method. Next, using the MOVPE method, AlG
The aInN layer 3 is grown. The ZnO: Al buffer layer 2 is sputtered by introducing an Al-doped ZnO target using a magnetron sputtering device by introducing a mixed gas of Ar and O 2 . Substrate temperature is about 30
It is 0 ° C. In addition, the AlGaInN layer 3 is a low pressure MOVP.
Using method E, when heating the substrate from room temperature,
The growth starts from 0 ° C., and the AlGaI
The above A at a higher temperature depending on the composition of the nN layer 3
A single crystal of the lGaInN layer 3 is grown. For example AlGa
Approx. 1080 ° C for N layer and 800 ° C for InGaN layer
Grows at the substrate temperature of. The reason for growing from about 400 ° C. is to avoid thermal decomposition of the ZnO: Al buffer layer 2, and when the substrate temperature is about 400 ° C. or higher, the ZnO: A
The l buffer layer 2 is rapidly decomposed and the buffer layer disappears.
When depositing the ZnO: Al buffer layer 2, for example, several atomic layers of an AlN film may be sputtered as a protective film against thermal decomposition.

【0018】次に、不純物添加したZnOバッファ層の
有効性について説明する。
Next, the effectiveness of the ZnO buffer layer doped with impurities will be described.

【0019】図2(a)に示すように(111)Si基
板1上にZnO:Alバッファ層2を堆積する。この場
合基板温度は約300℃前後で制御を行う。これは(1
11)Si基板1から得られる<111>方向の配向性
を上げるためであり、(111)Si基板1上に六方晶
のZnOのc軸配向性を上げることによりAlGaIn
N系半導体結晶のc軸配向性を揃えることを目的とす
る。c軸配向性を揃えるためには、基板温度を高くする
ことが望ましく、スパッタ時の基板温度あるいはスパッ
タ後に、例えば酸素を主成分とする雰囲気中において熱
処理を施して、ZnO:Alバッファ層2のc軸配向性
を揃えても良い。特に、ZnOにAl不純物を添加する
理由は、柱状多結晶ZnOのC面内における横方向のグ
レインサイズを小さくするためで、詳しい機構は現在の
ところ解明されていないが、不純物添加によってZnO
スパッタ時の核の基板上における塗れ性が向上し、独立
な核が増えて多結晶性が上がることや、不純物をきっか
けとして結晶の緩和が起こるために、横方向には大きな
単結晶が成長しにくい等の機構が考えられる。発明者ら
の実験によると、ZnO:Alバッファ層2の堆積温度
(または堆積後の熱処理温度)に対し、C面内における
横方向の平均グレインサイズをプロットすると図4のよ
うになり、不純物添加をしない従来の方法に対して、不
純物を添加すると約半分程度に小さい平均グレインサイ
ズが実現できた。前記のようにZnOが分解しない温度
範囲において、基板温度が高い程c軸配向性が向上する
ので、250℃から350℃においてZnO:Alバッ
ファ層2の堆積または熱処理することが望ましい。この
ようにして得られたZnO:Alバッファ層2上に、M
OVPEでGaNを成長すると、小さいグレインサイズ
のバッファ層に対応してGaN初期成長核4が形成さ
れ、従来法に比べてより小さな核が形成される。これに
より、前記GaN初期成長核が小さいと、Si基板との
熱膨張不整合によって加えられる熱歪みが小さくなるの
で、図2(b)に示すGaN層5に加えられる熱歪みが
低減され、よりクラックの少ないGaN層が得られた。
図5は、「不純物濃度が1016cm-3以下」、すなわち
ZnOバッファ層に不純物がほとんど添加されていない
(全く添加されていない、あるいは、若干量添加されて
はいるが無視できる程度の量)約5μm膜厚のGaNに
おけるクラック密度を1とした場合に、前記密度を不純
物添加濃度に対してプロットした図を示す。不純物濃度
の増大に対応してクラック密度が減少していくことがわ
かった。
As shown in FIG. 2 (a), a ZnO: Al buffer layer 2 is deposited on a (111) Si substrate 1. In this case, the substrate temperature is controlled at about 300 ° C. This is (1
11) To improve the orientation of <111> direction obtained from the Si substrate 1, and to increase the c-axis orientation of hexagonal ZnO on the (111) Si substrate 1 to form AlGaIn
The purpose is to align the c-axis orientation of the N-based semiconductor crystal. In order to make the c-axis orientation uniform, it is desirable to raise the substrate temperature, and after the substrate temperature during sputtering or after sputtering, heat treatment is performed in, for example, an atmosphere containing oxygen as a main component to form the ZnO: Al buffer layer 2 You may make the c-axis orientation uniform. In particular, the reason for adding Al impurities to ZnO is to reduce the lateral grain size in the C-plane of columnar polycrystalline ZnO, and the detailed mechanism has not been clarified at present, but ZnO is added by adding impurities.
The wettability of the nuclei on the substrate during sputtering is improved, the number of independent nuclei increases, and the polycrystallinity increases, and the relaxation of crystals occurs as a result of impurities, so that a large single crystal grows in the lateral direction. Mechanisms such as difficulty can be considered. According to the experiments conducted by the inventors, the average grain size in the lateral direction in the C plane is plotted against the deposition temperature (or the heat treatment temperature after deposition) of the ZnO: Al buffer layer 2 as shown in FIG. By adding impurities, the average grain size was reduced to about half as compared with the conventional method that does not do. As described above, in the temperature range in which ZnO is not decomposed, the higher the substrate temperature is, the more the c-axis orientation is improved. Therefore, it is desirable to deposit or heat-treat the ZnO: Al buffer layer 2 at 250 to 350 ° C. On the ZnO: Al buffer layer 2 thus obtained, M
When GaN is grown by OVPE, GaN initial growth nuclei 4 are formed corresponding to the buffer layer having a small grain size, and smaller nuclei are formed as compared with the conventional method. As a result, when the GaN initial growth nuclei are small, the thermal strain applied due to the thermal expansion mismatch with the Si substrate is small, so the thermal strain applied to the GaN layer 5 shown in FIG. A GaN layer with few cracks was obtained.
FIG. 5 shows that the impurity concentration is 10 16 cm −3 or less, that is, almost no impurities are added to the ZnO buffer layer (no impurities are added at all, or some impurities are added but negligible). ) A graph in which the crack density in GaN having a film thickness of about 5 μm is set to 1 and the density is plotted against the impurity addition concentration is shown. It was found that the crack density decreased as the impurity concentration increased.

【0020】本実施例ではZnOバッファ層にAl不純
物を添加する場合について説明したが、他のGa、In
等のn型不純物、N等のp型不純物、その他の不純物で
あっても同様の効果が得られる。特に、n型不純物の場
合は、後述するように、n型Si基板を用いた窒化物系
半導体素子においてn型Si基板にn電極を設ける際に
有効となり、クラックの少ない高品質な窒化物系半導体
を得るだけではなく、量産性、生産性に優れた窒化物系
半導体素子を作製する方法となる。
In this embodiment, the case where Al impurities are added to the ZnO buffer layer has been described, but other Ga, In
Similar effects can be obtained with n-type impurities such as N, p-type impurities such as N, and other impurities. In particular, in the case of n-type impurities, as will be described later, it is effective when providing an n-electrode on an n-type Si substrate in a nitride-based semiconductor device using an n-type Si substrate, and a high-quality nitride-based nitride-based This is a method for producing a nitride-based semiconductor element that is excellent not only in obtaining a semiconductor but also in mass productivity and productivity.

【0021】また、本実施例では不純物添加したZnO
バッファー層の形成方法としてスパッタ法で説明した
が、電子ビーム蒸着法やECR−MBE法等、従来から
用いられているいかなる成膜法も適用できることは言う
までもない。
Further, in this embodiment, ZnO doped with impurities is used.
Although the sputtering method has been described as the method for forming the buffer layer, it goes without saying that any conventionally used film forming method such as an electron beam evaporation method or an ECR-MBE method can be applied.

【0022】本発明の方法を窒化物系半導体レーザに適
用した例を、図7を用いて説明する。
An example in which the method of the present invention is applied to a nitride semiconductor laser will be described with reference to FIG.

【0023】まず、(111)n−Si基板71上にZ
nO:Alバッファ層72を堆積した基板に対し、n?
AlGaNクラッド層73、n?AlGaInN光ガイ
ド層74、GaInN系多重量子井戸(MQW)活性層
75、p−AlGaNキャップ層76、p?AlGaI
nN光ガイド層77、p−AlGaNクラッド層78、
p?AlGaInNコンタクト層79を順次結晶成長し
た後、p−AlGaNクラッド層78、p?AlGaI
nNコンタクト層79をリッジストライプ状に加工し、
リッジの両脇をSiO2絶縁膜81で覆い、電流注入領
域を形成する。ストライプ幅は3〜5ミクロン程度であ
る。絶縁膜81の開口部のp?AlGaInNコンタク
ト層79表面と、絶縁膜81の一部はp電極80が設け
られている。また、(111)n−Si基板71裏面に
はn電極82が形成されている。本素子(基板を除く)
のトータル膜厚は約5μmである。
First, Z is formed on a (111) n-Si substrate 71.
For the substrate on which the nO: Al buffer layer 72 is deposited, n?
AlGaN cladding layer 73, n? AlGaInN optical guide layer 74, GaInN-based multiple quantum well (MQW) active layer 75, p-AlGaN cap layer 76, p? AlGaI
nN optical guide layer 77, p-AlGaN cladding layer 78,
p? After sequentially growing the AlGaInN contact layer 79, the p-AlGaN cladding layer 78, p? AlGaI
The nN contact layer 79 is processed into a ridge stripe shape,
Both sides of the ridge are covered with a SiO 2 insulating film 81 to form a current injection region. The stripe width is about 3-5 microns. P? Of the opening of the insulating film 81? A p-electrode 80 is provided on the surface of the AlGaInN contact layer 79 and part of the insulating film 81. An n electrode 82 is formed on the back surface of the (111) n-Si substrate 71. This element (excluding substrate)
Has a total film thickness of about 5 μm.

【0024】従来、Si基板上に前記素子構造を形成す
る場合には、熱歪みに起因するクラック発生の制約のた
めに、トータル膜厚が1μmに満たない膜厚の制限があ
り、レーザの光ガイドに必要な光閉じ込めを実現するた
めには、上記膜厚の制限は大きな課題となって高品質な
レーザ素子を得ることが不可能であった。
Conventionally, when the above-mentioned device structure is formed on a Si substrate, the total film thickness is limited to less than 1 μm due to the restriction of crack generation due to thermal strain. In order to realize the optical confinement necessary for the guide, the limitation of the film thickness becomes a big problem and it is impossible to obtain a high quality laser device.

【0025】本方法によって得られた素子は、レーザ素
子にとって十分な膜厚を得ることが可能となり、Si基
板上に極めて高品質な波長400nm帯に発振する窒化
物系半導体レーザが可能となった。前記素子中にはクラ
ックや欠陥が少なく信頼性も高く、60℃、30mWで
10000時間以上の寿命を得た。
The device obtained by this method can obtain a sufficient film thickness for a laser device, and a nitride semiconductor laser which oscillates in a wavelength band of 400 nm having an extremely high quality on a Si substrate becomes possible. . The device had few cracks and defects and high reliability, and a life of 10,000 hours or more was obtained at 60 ° C. and 30 mW.

【0026】本実施例では、窒化物系半導体レーザにつ
いて説明したが、Si上に高品質な窒化物系半導体が実
現できれば、窒化物系半導体の物性を生かした、高周
波、高出力、高温動作可能なFET、バイポーラトラン
ジスタ、あるいは、紫外域の発光特性を利用した発光ダ
イオードや照明用光源等の窒化物系半導体素子に適用で
きることは言うまでもない。さらにSiと窒化物系半導
体が一体化することにより、集積化による効果も当然実
現できる。
In the present embodiment, the nitride semiconductor laser has been described. However, if a high quality nitride semiconductor can be realized on Si, it is possible to operate at high frequency, high output and high temperature by utilizing the physical properties of the nitride semiconductor. It is needless to say that the present invention can be applied to a FET, a bipolar transistor, or a nitride-based semiconductor element such as a light emitting diode or a light source for illumination that utilizes the emission characteristics in the ultraviolet region. Further, by integrating Si and the nitride-based semiconductor, the effect of integration can be naturally realized.

【0027】なお、本実施例ではSi基板の(111)
面について説明したが、微量傾斜した面方位を有するS
i基板に対しても有効である。更に、結晶欠陥の低減を
目的としてSi基板やSi基板上のGaN膜に金属や誘
電体膜を選択的に設けたり、エッチング等により加工溝
を形成した基板に対して選択横方向成長を用いる手法も
当然適用できる。
In this embodiment, (111) of the Si substrate is used.
The surface has been described, but S having a slightly tilted surface orientation
It is also effective for i-boards. Further, a method of selectively providing a metal or dielectric film on a Si substrate or a GaN film on the Si substrate for the purpose of reducing crystal defects, or using selective lateral growth on a substrate having a processed groove formed by etching or the like. Can also be applied.

【0028】また、本発明は、高品質な窒化物系半導体
を成長した後、エッチング等を用いてSi基板更には不
純物添加ZnOバッファ層を除去して窒化物系半導体の
みから構成される基板の作製方法にも適用できる。
Further, according to the present invention, after a high quality nitride semiconductor is grown, the Si substrate and the impurity-added ZnO buffer layer are removed by etching or the like to obtain a substrate composed of only the nitride semiconductor. It can also be applied to the manufacturing method.

【0029】(実施例2)Si基板上に高品質な窒化物
系半導体を成長する他の方法について説明する。
(Example 2) Another method for growing a high-quality nitride semiconductor on a Si substrate will be described.

【0030】図6のように(111)Si基板1上にス
パッタ法を用いてAl23:Siバッファ層9を膜厚1
0nm堆積する。次に、MOVPE法を用いてAlGa
InN層10を成長する。Al23:Siバッファ層9
はマグネトロンスパッタリング装置を用いてSiドープ
したAl23のターゲットをArとO2の混合ガスを導
入することによりスパッタリングする。基板温度は約5
00℃である。次に、AlGaInN層10は減圧MO
VPE法を用い、AlGaInN層10を構成する組成
に応じた高い温度で前記AlGaInN層3の単結晶を
成長する。例えばAlGaN層では約1080℃で、I
nGaN層では約800℃の基板温度で成長する。Al
23:Siバッファ層9は実施例1のZnO:Alバッ
ファ層に比べ熱的に安定であるために、前記Al23
Siバッファ層9を堆積後、MOVPE法を用いてAl
GaInN層10を成長する際に基板加熱によるバッフ
ァ層の熱分解が回避できる利点を有し、c軸配向性を向
上させるために酸素を主成分とする雰囲気中において熱
処理するにも有利となる。
As shown in FIG. 6, an Al 2 O 3 : Si buffer layer 9 having a film thickness of 1 is formed on the (111) Si substrate 1 by the sputtering method.
Deposit 0 nm. Next, using the MOVPE method, AlGa
The InN layer 10 is grown. Al 2 O 3 : Si buffer layer 9
Is sputtered by introducing a mixed gas of Ar and O 2 into a Si-doped Al 2 O 3 target using a magnetron sputtering device. Substrate temperature is about 5
It is 00 ° C. Next, the AlGaInN layer 10 is depressurized MO.
Using the VPE method, a single crystal of the AlGaInN layer 3 is grown at a high temperature according to the composition of the AlGaInN layer 10. For example, in the AlGaN layer, at about 1080 ° C., I
The nGaN layer grows at a substrate temperature of about 800 ° C. Al
Since the 2 O 3 : Si buffer layer 9 is more thermally stable than the ZnO: Al buffer layer of Example 1, the above Al 2 O 3 : Si buffer layer 9 is:
After depositing the Si buffer layer 9, Al is formed using the MOVPE method.
When the GaInN layer 10 is grown, it has an advantage that thermal decomposition of the buffer layer due to substrate heating can be avoided, and it is also advantageous for heat treatment in an atmosphere containing oxygen as a main component in order to improve the c-axis orientation.

【0031】Al23バッファ層にSi不純物を添加す
る理由は実施例1のZnOバッファ層と同様で、c軸配
向性が高くかつ横方向のグレインサイズの小さい柱状多
結晶バッファ層を作製するためである。ZnOバッファ
層との違いはAl23がSiに比べ熱膨張係数が大きい
ことからAl23には引っ張りの熱歪みが加わり、Al
23のc面内における格子定数が拡大されるので、Ga
NとAl23との格子不整合が低減されより高品質な窒
化物系半導体層が得られる。
The reason why Si impurities are added to the Al 2 O 3 buffer layer is the same as in the ZnO buffer layer of Example 1, and a columnar polycrystalline buffer layer having a high c-axis orientation and a small lateral grain size is prepared. This is because. The difference from the ZnO buffer layer is that Al 2 O 3 has a larger coefficient of thermal expansion than Si, so that tensile strain is added to Al 2 O 3 and
Since the lattice constant of 2 O 3 in the c-plane is expanded, Ga
The lattice mismatch between N and Al 2 O 3 is reduced, and a higher quality nitride semiconductor layer can be obtained.

【0032】実施例1と同様に、Si基板上にAl
23:Siバッファ層を用いて窒化物系半導体層から構
成されるレーザ素子を作製したところ、実施例1と同様
な特性を有する高品質なレーザが得られた。前記素子中
にはクラックや欠陥が少なく信頼性も高く、60℃、3
0mWで10000時間以上の寿命を得た。
Similar to the first embodiment, Al is formed on the Si substrate.
When a laser device composed of a nitride semiconductor layer was manufactured using a 2 O 3 : Si buffer layer, a high quality laser having the same characteristics as in Example 1 was obtained. The device has few cracks and defects and high reliability.
A life of 10,000 hours or more was obtained at 0 mW.

【0033】Al23バッファ層に添加する不純物は他
にGe等のIV族系の元素においても同様の効果が確認
された。
It was confirmed that other impurities added to the Al 2 O 3 buffer layer also had the same effect on Group IV elements such as Ge.

【0034】不純物添加Al23バッファ層の堆積方法
は本実施例の場合に制限されるものではなく、通常行わ
れる他のいかなる手法であってもよいことは言うまでも
ない。
It is needless to say that the method of depositing the impurity-added Al 2 O 3 buffer layer is not limited to the case of this embodiment, and any other commonly used method may be used.

【0035】[0035]

【発明の効果】以上説明したように、本発明の窒化物系
半導体の製造方法によれば、Si基板からの熱歪みを窒
化物系半導体層に加えることを回避し、従来では実現困
難であった膜厚を有するクラックのない高品質な窒化物
系半導体単結晶層を実現でき、量産性、生産性に優れた
窒化物系半導体素子を作製することが可能となる。
As described above, according to the method for manufacturing a nitride-based semiconductor of the present invention, it is possible to avoid applying thermal strain from the Si substrate to the nitride-based semiconductor layer, and it is difficult to realize the conventional method. It is possible to realize a high-quality nitride-based semiconductor single crystal layer having a uniform film thickness, and to manufacture a nitride-based semiconductor element having excellent mass productivity and productivity.

【0036】また本発明の窒化物系半導体素子構造によ
れば、Si基板上にクラックや欠陥を発生させずに光導
波構造を形成するのに十分な膜厚を有するレーザを実現
でき、レーザに限らず低コストな窒化物系半導体素子が
実現できる。
Further, according to the nitride-based semiconductor device structure of the present invention, it is possible to realize a laser having a film thickness sufficient to form an optical waveguide structure without causing cracks or defects on a Si substrate. Without limitation, a low cost nitride semiconductor device can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施の形態を示す窒化物系半導
体の構造断面図
FIG. 1 is a structural cross-sectional view of a nitride semiconductor showing a first embodiment of the present invention.

【図2】本発明の第1の実施の形態を示す窒化物系半導
体の製造工程図
FIG. 2 is a manufacturing process diagram of a nitride-based semiconductor showing a first embodiment of the present invention.

【図3】従来の窒化物系半導体の製造工程図FIG. 3 is a manufacturing process diagram of a conventional nitride-based semiconductor

【図4】本発明の一実施例の効果を示す図FIG. 4 is a diagram showing an effect of one embodiment of the present invention.

【図5】本発明の一実施例の効果を示す図FIG. 5 is a diagram showing an effect of one embodiment of the present invention.

【図6】本発明の第2の実施の形態を示す窒化物系半導
体の構造断面図
FIG. 6 is a structural cross-sectional view of a nitride-based semiconductor showing a second embodiment of the present invention.

【図7】本発明の第1の実施の形態を示す窒化物系半導
体素子断面図
FIG. 7 is a cross-sectional view of a nitride semiconductor device showing the first embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 Si基板 2 ZnO:Alバッファ層 3 AlGaInN層 4 GaN初期成長核 5 GaN層 6 ZnOバッファ層 7 GaN初期成長核 8 GaN層 9 Al2O3:Siバッファ層 10 AlGaInN層 71 n−Si基板 72 ZnO:Alバッファ層 73 n−AlGaNクラッド層 74 n−AlGaInN光ガイド層 75 GaInN系多重量子井戸活性層 76 p−AlGaNキャップ層 77 p−AlGaInN光ガイド層 78 p−AlGaNクラッド層 79 p−AlGaInNコンタクト層 80 p電極 81 SiO2 82 n電極1 Si substrate 2 ZnO: Al buffer layer 3 AlGaInN layer 4 GaN initial growth nucleus 5 GaN layer 6 ZnO buffer layer 7 GaN initial growth nucleus 8 GaN layer 9 Al2O3: Si buffer layer 10 AlGaInN layer 71 n-Si substrate 72 ZnO: Al Buffer layer 73 n-AlGaN cladding layer 74 n-AlGaInN optical guide layer 75 GaInN-based multiple quantum well active layer 76 p-AlGaN cap layer 77 p-AlGaInN optical guide layer 78 p-AlGaN cladding layer 79 p-AlGaInN contact layer 80 p Electrode 81 SiO 2 82 n-electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 川口 靖利 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 4G077 AA03 BE11 DB08 EB01 ED06 EF02 HA02 TB05 TC13 TK01 4K030 AA11 BA02 BA08 BA11 BA38 BB02 CA04 DA02 FA10 HA04 JA10 LA18 5F045 AA04 AB14 AF03 AF13 BB12 BB13 CA12 DA53 5F052 JA07 KA01 5F073 AA45 AA55 AA74 CA07 CB04 CB07 EA29    ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yasutoshi Kawaguchi             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F term (reference) 4G077 AA03 BE11 DB08 EB01 ED06                       EF02 HA02 TB05 TC13 TK01                 4K030 AA11 BA02 BA08 BA11 BA38                       BB02 CA04 DA02 FA10 HA04                       JA10 LA18                 5F045 AA04 AB14 AF03 AF13 BB12                       BB13 CA12 DA53                 5F052 JA07 KA01                 5F073 AA45 AA55 AA74 CA07 CB04                       CB07 EA29

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】Si基板上に不純物添加したZnOバッフ
ァ層を用いてAlxGayInzN(0≦x≦1,0≦y
≦1,0≦z≦1,x+y+z=1)系半導体を成長す
ることを特徴とする窒化物系半導体の製造方法。
1. Al x Gay y In z N (0≤x≤1,0≤y using a ZnO buffer layer doped with impurities on a Si substrate.
≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) system semiconductor is grown, The manufacturing method of the nitride system semiconductor characterized by the above-mentioned.
【請求項2】不純物が少なくともIn,Ga,Alのい
ずれかで構成されることを特徴とする請求項1に記載の
窒化物系半導体の製造方法。
2. The method for producing a nitride-based semiconductor according to claim 1, wherein the impurity is composed of at least In, Ga or Al.
【請求項3】Si基板上に不純物添加したZnOバッフ
ァ層を用いて形成されたAlxGayInzN(0≦x≦
1,0≦y≦1,0≦z≦1,x+y+z=1)系半導
体素子。
3. An Al x Ga y In z N (0 ≦ x ≦) formed by using an impurity-doped ZnO buffer layer on a Si substrate.
1,0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) based semiconductor device.
【請求項4】不純物が少なくともIn,Ga,Alのい
ずれかで構成されることを特徴とする請求項3に記載の
AlxGayInzN(0≦x≦1,0≦y≦1,0≦z
≦1,x+y+z=1)系半導体素子。
4. The Al x Ga y In z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1 according to claim 3, wherein the impurities are composed of at least In, Ga or Al. , 0 ≦ z
≦ 1, x + y + z = 1) based semiconductor device.
【請求項5】Si基板上に不純物添加したAl23バッ
ファ層を用いてAlxGayInzN(0≦x≦1,0≦
y≦1,0≦z≦1,x+y+z=1)系半導体を成長
することを特徴とする窒化物系半導体の製造方法。
5. An Al x Ga y In z N (0≤x≤1,0≤ using an Al 2 O 3 buffer layer doped with impurities on a Si substrate.
y ≦ 1,0 ≦ z ≦ 1, x + y + z = 1) -based semiconductor is grown, and a method for manufacturing a nitride-based semiconductor.
【請求項6】不純物が少なくともSi,Geのいずれか
で構成されることを特徴とする請求項5に記載の窒化物
系半導体の製造方法。
6. The method for manufacturing a nitride-based semiconductor according to claim 5, wherein the impurities are composed of at least one of Si and Ge.
【請求項7】Si基板上に不純物添加したAl23バッ
ファ層を用いて形成されたAlxGayInzN(0≦x
≦1,0≦y≦1,0≦z≦1,x+y+z=1)系半
導体素子。
7. An Al x Ga y In z N (0 ≦ x formed by using an Al 2 O 3 buffer layer doped with impurities on a Si substrate.
≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1, x + y + z = 1) based semiconductor device.
【請求項8】不純物が少なくともSi,Geのいずれか
で構成されることを特徴とする請求項7に記載のAlx
GayInzN(0≦x≦1,0≦y≦1,0≦z≦1,
x+y+z=1)系半導体素子。
8. The Al x according to claim 7, wherein the impurities are composed of at least one of Si and Ge.
Ga y In z N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1,
x + y + z = 1) type semiconductor device.
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0366921A (en) * 1989-08-04 1991-03-22 Kayseven Co Ltd Torque transmitting means
JP2006040932A (en) * 2004-07-22 2006-02-09 Mitsubishi Electric Corp Nitride semiconductor device and its manufacturing method
KR100631905B1 (en) * 2005-02-22 2006-10-11 삼성전기주식회사 Nitride single crystal substrate manufacturing method and nitride semiconductor light emitting device manufacturing method using the same
KR100664986B1 (en) 2004-10-29 2007-01-09 삼성전기주식회사 Nitride based semiconductor device using nanorods and method for manufacturing the same
JP2009038179A (en) * 2007-08-01 2009-02-19 National Institute For Materials Science Element substrate and manufacturing method thereof
JP2013080968A (en) * 2013-01-25 2013-05-02 Meijo University GROWTH METHOD FOR GaN-BASED COMPOUND SEMICONDUCTOR, AND SUBSTRATE WITH GROWTH LAYER
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JP2013123052A (en) * 2011-12-09 2013-06-20 Power Integrations Inc Method of forming gallium nitride layer on silicon substrate, and gallium nitride substrate
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0366921A (en) * 1989-08-04 1991-03-22 Kayseven Co Ltd Torque transmitting means
JP2006040932A (en) * 2004-07-22 2006-02-09 Mitsubishi Electric Corp Nitride semiconductor device and its manufacturing method
KR100664986B1 (en) 2004-10-29 2007-01-09 삼성전기주식회사 Nitride based semiconductor device using nanorods and method for manufacturing the same
KR100631905B1 (en) * 2005-02-22 2006-10-11 삼성전기주식회사 Nitride single crystal substrate manufacturing method and nitride semiconductor light emitting device manufacturing method using the same
KR101308128B1 (en) * 2006-06-13 2013-09-12 서울옵토디바이스주식회사 Light emitting device and the fabrication method thereof
KR101259995B1 (en) * 2006-06-24 2013-05-06 서울옵토디바이스주식회사 Light emitting device and the fabrication method thereof
JP2009038179A (en) * 2007-08-01 2009-02-19 National Institute For Materials Science Element substrate and manufacturing method thereof
JP2013123052A (en) * 2011-12-09 2013-06-20 Power Integrations Inc Method of forming gallium nitride layer on silicon substrate, and gallium nitride substrate
JPWO2014092163A1 (en) * 2012-12-14 2017-01-12 日本碍子株式会社 Surface light emitting device using zinc oxide substrate
JP2013080968A (en) * 2013-01-25 2013-05-02 Meijo University GROWTH METHOD FOR GaN-BASED COMPOUND SEMICONDUCTOR, AND SUBSTRATE WITH GROWTH LAYER

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