JP2003223357A - Address generating device for circular address buffer and integrated circuit with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve memory using efficiency and flexibility in the design of the circular buffer of an integrated circuit. <P>SOLUTION: This dual mode address generator comprises inputs that receive a current address A, an address offset M, a buffer length L, and a control signal; and logic configured to compute a first memory address for a buffer with an implied lower boundary and a second memory address for a buffer with an implied higher boundary response to the A, M, and L. One of the first and second memory addresses is provided in response to the control signal. The first memory address corresponds the current address A plus the address offset M for a first circular buffer having an implied lower address boundary X and including addresses X through (X+L), and the second memory address corresponds the current address A plus the address offset M for a second circular buffer having an implied higher address boundary Y and including addresses Y through (Y-L). <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to memory addressing, and more particularly to addressing circular buffers used in digital systems such as digital signal processors.

[0002]

Circular addressing, also called modulo addressing, is commonly used in digital signal processing and other data processing applications. In a circular buffer to which circular addressing is applied, one address range is assigned to that buffer. When generating the address of the circular buffer, the offset value increments the current address and generates the next address. If the sum of the current address and the offset value indicates an address outside the allocated address range, the next address wraps around to the opposite boundary of the circular buffer.

In the prior art, various proposals have been made for generating an address of a circular buffer. The usual way to perform circular addressing is to define two explicit parameters that set the upper and lower bounds of the assigned address range. In this way, the user has the flexibility to define buffers in unlimited locations of available memory. However, this method requires a register for storing the boundary and a relatively complicated logic for calculating the next address. Since address generation is on the critical path of a particular design, it is desirable to reduce the number of required parameters and simplify the logic.

Another proposal for address generation of circular buffers is described in US Pat. No. 4,800,524 by Roesgen. In the Resgen patent proposal, the buffer is defined by a single buffer length parameter and the current address of the circular buffer. The lower bound of the circular buffer is implied from the current address and buffer by replacing the low order N bits of the current address with zeros. Where N
Is the first (leftmost) when the buffer length is expressed in binary.
Is a bit position that has a 1. The upper bound of the circular buffer is defined as the implied lower bound plus the buffer length.
This method is easier to implement than the method that requires explicit parameters to set the upper and lower bounds. But,
Inefficient memory usage due to the limited set of boundaries available.

Other proposals relating to circular address generation are prior art: US Pat. No. 4,202,035 of the invention by Lane, US Pat. No. 4,809,156 of the invention by Taber, US Pat. No. 5,24, for invention by Catherwood et al.
9,148, and U.S. Pat. No. 5,381,360 by Shridhar et al.

[0006]

As digital signal processing applications that rely on circular addressing become more complex, there is an increasing need to improve flexibility and reduce the cost of address generators for such applications.

[0007]

SUMMARY OF THE INVENTION In accordance with the present invention, there is provided an apparatus for generating an address of a toroidal address buffer in memory, in which the upper bound of the toroidal buffer is implied from the current address. Applying this proposal alone and in combination with a circular buffer that relies on an implied lower bound, improves memory usage and flexibility in the circular buffer design of integrated circuits and processing systems.

One embodiment of an address generator according to the present invention comprises an input for receiving a current address A, an address offset M, a buffer length L, and a control signal and a first memory address and a first memory address indicating a location in memory. And a logic configured to calculate two memory addresses as a function of A, M, and L. One of the first and second memory addresses is provided in response to the control signal. The first memory address has an address boundary X, from X to (X +
L) corresponding to the sum of the current address A and the address offset M of the first circular buffer, the second memory address having an address boundary Y, from Y to (Y−L ) To the sum of the current address A and the address offset M of the second circular buffer.

The buffer length L is a value having a leading 1 at the bit position N when represented by a binary number. The implied lower address boundary X is calculated by replacing the low order N bits of the current address A with 0's. The implied upper address boundary Y is calculated by replacing the low order N bits of the current address A with ones. In various embodiments, the inputs include registers that store A, M and L. The control signal can also be stored in one register or in a register shared with one of the other parameters such as the offset value M.

In one embodiment, the logic used by the address generator is that the carry-out signal produces a first output equal to the sum A + M, and when the sign of M is positive. First wrap address sum (A +
M)-(L + 1), or when the sign of M is a negative number, the second wrap address sum (A + M) + (L
A second adder that produces a second output equal to +1) by the carry-out signal. The selection logic selects the first output or the second output according to the carry-out signal from the first and second adders. In one preferred embodiment, the first and second adders are shared logic used for a circular buffer having an implied lower address boundary and a circular buffer having an implicit upper address boundary.

In yet another embodiment, L has a leading 1 at bit position N and an implied lower address boundary X is calculated by replacing the lower N bits of said current address A with 0 to imply an upper limit. The address boundary Y is calculated by replacing the low order N bits of the current address A with ones. The first and second adders generate carry out signals for a plurality of bit positions and the selector is responsive to L to tell the adder used in this logic the carry out signal from the N th bit position. I will provide a. Therefore, in this embodiment, the selection logic depends on the carry out signal from the Nth bit position of the first and second adders, the first output or the second output.
Is operable to select the output of.

In an embodiment in which both an implied lower bound and an implied upper bound are used, the selection logic is such that the control signal is set to the first memory address and the address offset is a positive number. , The carry-out from the first adder and the carry-out from the second adder are not 1, or the control signal is set for the first memory address and the address offset Is a negative number and the carry out from the first adder is 1, or the control signal is set to the second memory address and the address offset is a positive number, and If the carry-out from the first adder is 0, or the control signal is set to the second memory address. Selecting the output of the first adder when the address offset is a negative number and the carry out from both the first adder and the second adder is 1; Is the first
Of the first adder or the second adder, the address offset being a positive number.
Said carry-out from at least one of said adders is 1, or said control signal is set for said first memory address and said address offset is a negative number, said first adder If the carry-out from is 0, or if the control signal is
, The address offset is a positive number, and the carry-out from the first adder is 1, or the control signal is for the second memory address. Set, selecting the output of the second adder if the address offset is negative and the carry out from at least one of the first adder or the second adder is 0. To be configured.

In an embodiment in which only an implied upper address boundary is used, the selection logic is such that the address offset is a positive number and the carry out from the first adder is 0, or the address is If the offset is a negative number and the carry out from both the first adder and the second adder is 1, then the output of the first adder is selected and the address offset is positive. A number and the carry-out from the first adder is 1, or the address offset is negative and from at least one of the first adder or the second adder. It is configured to select the output of the second adder if the carry out is zero.

The present invention is also embodied by an integrated circuit including a processor core, a register file for storing a current address A, an offset value M and a buffer length L, a memory and an address generator of the memory. In an embodiment according to the invention, as mentioned above, the address generator is configured to use only the implied upper address boundary or a combination of the implied upper address boundary and the implied lower address boundary. Further aspects and advantages of the invention are explained below with reference to the figures.

[0015]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a simplified diagram of an integrated circuit processor with an address generator of the present invention. The integrated circuit device 10 includes a program memory 11, a data memory 14, and a processor core 12. The processor core 12 includes a circular address generator 15 for a data memory address, a register file 13 including a circular buffer program register, And other logic elements such as an instruction decoder and ALU. The toroidal address generator 15 according to the invention manages a buffer of the data memory 14 having a length of (L + 1) and having a selectable boundary base which can comply with an implied upper bound or a combined implied upper and lower bound.

For example, processor 12 executes instructions from program memory 11. The instructions include direct address instructions and indirect address instructions. The indirect address instructions depend on the circular buffer program register in register file 13. In one embodiment, there are four sets of circular buffer program registers, each of which has a first register that stores the current address A, an offset value M.
And a third register for storing a buffer length value L. In this embodiment, which supports both upper and lower address boundaries, an upper / lower control signal is provided for each access indicating whether the upper or lower address boundary buffer is being used. The upper / lower limit control signal
Provided as part of an instruction that uses circular addressing, or independently as the high bit of a register that stores the offset value M, when the offset value M is limited to a value that uses only the low order bits of the register. good.

For example, the instruction "ldx1, ar2, m2"
Is interpreted by the decoder of the processor core 12, and the memory data is loaded into the register x1 of the register file.
This memory data is a register ar2 that stores the current address A of a set of circular buffer program registers.
Is incremented to the offset value M stored in the register m2 of the annular buffer program register from the address designated by the. A register l that stores the value L of the buffer length of this circular buffer program register
2 is preconfigured by the processor 12 or otherwise configured. In one embodiment, when the buffer length value L of a 16-bit address is set to hexadecimal ffff, a linear address is specified in accordance with an indirect address instruction that specifies a register of a corresponding set of circular buffer program registers. Addressing is used.

2 (a) to 2 (c) show embodiments of circular addressing using an implied lower limit address boundary, an implied upper limit address boundary, and a combined upper and lower limit address boundary, respectively. FIG. 2A is an implicit lower bound address boundary approach according to the prior art, in which the circular buffer 1
And 2. In this example, circular buffer 1 has length L + 1 = 10 and its allocation is 0a00.
(Hexadecimal) to 0a09 (Hexadecimal). Suppose the user wants the length L + 1 of the circular buffer 2 to be 6. The length of the address set between 0a0a (hexadecimal) and 0a0f (hexadecimal) is equal to 6, but this address set cannot be used for the circular buffer 2. This is because the address set must have an implied lower bound with lower bound 3 equal to 0. Therefore, the circular buffer 2 is arranged between 0a10 (hexadecimal) and 0a15 (hexadecimal), leaving an unused area between 0a0a (hexadecimal) and 0a0f (hexadecimal).

FIG. 2 (b) illustrates the implicit upper bound address boundary approach of the present invention. Annular buffers 1 and 2 are shown. In this case, the upper limit address boundary is implied. Therefore, the circular buffer 1 has a length L + 1 = 1.
Has 0 and its allocation is 0a06 (hexadecimal)
To 0a0f (hexadecimal). In this example, the user defines a circular buffer 2 having a length L + 1 = 6. The most compact allocation, closest to buffer 1, causes buffer 2 to be 0 by implied upper bound base.
It is placed between a17 (hexadecimal) and 0a12 (hexadecimal). Even with this, an unused area still remains between the buffers 1 and 2.

FIG. 2 (c) shows a circular buffer 1 having an implied lower limit address boundary and a circular buffer 2 having an implied upper limit address boundary, which has no unused area between them. In this example, the circular buffer 1 has a length L + 1 = 10. For the current address A between 0a00 (hexadecimal) and 0a09 (hexadecimal),
The annular address generator is 0a00 (hexadecimal) to 0a
The next address is generated within the range of 09 (hexadecimal).
In this example, circular buffer 2 of length L + 1 = 6 has an implied upper address boundary 0a0f (hexadecimal). The current address between 0a0f (hexadecimal) and 0a0a (hexadecimal) is used to access the circular buffer 2, and the circular address generator generates 0a0f (hexadecimal).
And generate the next address in the range 0a0a (hexadecimal). As can be seen, the two circular buffers can be configured so that there are no unused areas between them.

Address generation logic for buffers with implicit lower bounds and buffers with implicit upper bounds is described below with reference to FIGS. 3 and 4. When selecting a buffer with an implied lower bound, this implied lower bound is determined by inserting a 0 in the low N bits of the current address A. Here, the value N is the bit position where the leading “1” of the buffer length parameter L is located. This value N can also be represented by the formula 2̂ (N−1) <= L <2̂N. According to this method, the lower bound is 2 ^ N
Can be set to any multiple of. The lower bound of this buffer is specified by concatenating the high-order W-N bits of A on the left with a 0 on the low-order N bits of the right. here,
W is the number of address bits used in the memory. Once the lower bound is determined, it is determined by adding L to the lower bound of the buffer of length L + 1. That is, the upper boundary is the lower W-N bits of A on the left and the lower N bits of L on the right.
It is specified by concatenating bits.

For example: W = 16 and L is 00000000
00 0010 1011 (16 bits in binary), the current address A for this buffer is 0011 100
Consider the case of 10101 1110. Since the first 1 in L is at bit position 6, N = 6. The implied lower bound is 0011 1001 0100 0000 and the implied upper bound is 0011 1001 0110 1
It is 011.

For simplification of the description, the high-order W-N bits are excluded from A, the upper and lower bounds, I is used to represent the lower N bits of A, and 0 is used to represent the lower boundary. Then, L is used to represent the upper boundary. M is the offset between the current address I and the next destination address. M is a signed number and is a positive or negative number. If M is positive, there are three possible states for the logic used by the toroid address generator. (1) I
+ M> = 2 ^ N, (2) I + M> = L + 1, and (3) I + M <L + 1.

In the case of state 1 where M is a positive number and I + M> = 2 ^ N. The absolute address (I + M) exceeds the upper boundary L. The next address needs to be wrapped in the lower region of the circular buffer. The next target address I can be calculated by subtracting the buffer length (L + 1) from the absolute address (I + M). The equation is I + M- (L + 1), which is converted to I + M + (L \) in the 2's complement system.

In the case of state 2 where M is a positive number and I + M> = L + 1. The absolute address (I + M) is again the upper boundary L
Surpass. The next address needs to be wrapped in the lower area of the buffer. The next target address I can be calculated by subtracting the buffer length from the absolute address.
The formula is I + M- (L + 1) as in the case of the state (1).
And the complement system of 2 is I + M + (L \).

State 3 in which M is a positive number and I + M <L + 1
in the case of. The absolute address I + M does not exceed the upper boundary L. Therefore, the next target address I is equal to I + M. When hardware is executed, state 1 (I + M> = 2 ^
N) is indicated by the carry out generated from I + M, state 2 (I + M> = L + 1) is I + M + (L \)
Indicated by the carry out generated from. State 3 is shown when there is no carry out generated from I + M.

When M is negative, there are two possible states for the logic used by the toroid address generator.
(1) I + M <0, and (2) I + M> = 0. For state 1 where M is a negative number and I + M <0. The absolute address (I + M) is a negative number below the lower bound 0 of the circular buffer. The next address needs to be wrapped in the high region of the circular buffer. The next target address I is the absolute address (I + M) and the buffer length L +
It can be calculated by adding 1. The formula is I + M + L
It is +1.

In state 2 where M is a negative number and I + M> = 0. The absolute address (I + M) is above the lower bound 0.
Therefore, the target address I becomes equal to I + M.
When hardware is executed, M is a negative state 1 (I + M <
0) is indicated by the lack of carry out generated from I + M. State 2 (I + M> = 0) where M is a negative number is indicated by the carry out generated from I + M.

Therefore, the hardware implementation of the implicit lower bound address boundary circular buffer is logically performed as shown in FIG. The logic of FIG. 3 includes a first adder 201 and a second adder 202. At the input to the first adder 201 are the values I and M. The output of the first adder 201, called the absolute address, is
7 and is equal to I + M. The carry-out signal from adder 201 is provided on line 206. The input to the second adder 202 is the exclusive NOR gate 203.
And the output from the first adder 201 to line 207. The input to the exclusive NOR gate 203 is
There are sign bits for the length value L and the address offset M. The second adder 202 receives the M code bits as a carry-in from line 211. The output of the second adder 202, here called the wrap address, is provided on line 209. The multiplexer 213 receives the absolute address from the line 207 and the line 2 as an input.
09 receives the wrap address and supplies the next destination address on line 210. A control signal, which indicates whether the calculated absolute address or wrap address is provided as an output, is provided on line 212 to multiplexer 2
13 is supplied. The signal on line 212 comes from the output of multiplexer 214, which
14 operates according to the sign bit of M from line 211, where the sign bit of M is 1 (M is a negative number),
The logic is selected for when the sign bit of M is 0 (M is a positive number).

When the sign bit of M is 1, the output of inverter 205 is provided on line 212 as a control signal. The input of the inverter 205 is the first adder 2
Carry out signal from 01 to line 206.
Therefore, when the sign bit of M is 1, the wrap address is selected when the carry-out of the first adder 201 is 0, and the absolute address is selected when the carry-out of the first adder 201 is 1.

If the sign bit of M is 0, OR
The output of gate 204 is provided on line 212 as a control signal. The input of the OR gate 204 is the second adder 2
Carry out signal from line 02 to line 208, first
Carry-out signal from the adder 201 to the line 206. Therefore, if the sign bit of M is 0,
A wrap address is selected if at least one of the carry out signals on lines 206 and 208 is one. M
If the sign bit of 0 is 0, then an absolute address is selected if both carry out signals on lines 206 and 208 are 0.

If a buffer with an implied upper bound is selected, the implied upper bound is determined by concatenating a 1 to the low order N bits of the current address A. Here, N is a bit position where the leading "1" of the length parameter L is located. N can also be determined by the equation 2 ^ (N-1) <= L <2 ^ N. That is, the upper limit boundary can be set to an arbitrary multiple of 2 ^ N. Address A of this buffer containing the W bit can be used to locate the upper and lower bounds of this buffer. The upper bound of this buffer is specified by concatenating the high-order W-N bits of A on the left with a 1 on the low-order N bits of the right. Once the upper bound is determined, the lower bound is determined by subtracting L from the upper bound. Therefore, the lower bound is specified by concatenating the high-order W-N bits of A on the left with the low-order N bits of (L \) on the right. Here, L \ is the one's complement of L.

For example: W = 16 and L is 00000000
00 0010 1011 (16 bits in binary), the current address A for this buffer is 0011 100
Consider the case of 10101 1110. In this case N = 6 and the implied upper bound is 0011 1001 0
111 1111 and the implied lower bound is 001110
01 0101 0100.

As described above, for simplification of description, the high-order W-N bits are excluded from A, the upper limit boundary, and the lower limit boundary, and I is represented to represent the lower N bits of A, and the upper boundary is represented. , And (L \) to represent the lower bound. M is the offset between the current address I and the next destination address. M is a signed number and is a positive or negative number.

When M is a positive number, the following two states are possible with respect to the logic used by the annular address generator.
(1) When I + M> = F + 1, and (2) I + M <
This is the case of F + 1. In the case of state 1 in which M is a positive number and I + M> = F + 1. The absolute address (I + M) exceeds the upper boundary (F, all 1s). The next address needs to be wrapped in the lower area of the buffer. Objective (lap)
The address I can be calculated by subtracting the buffer length from the absolute address. The formula is I + M- (L + 1), which is equal to I + M + (L \) in the two complement system. In the case of state 2 where M is a positive number and I + M <F + 1. The absolute address (I + M) does not exceed the upper boundary F. Therefore, the target address I is equal to I + M.

During hardware execution, state 1 (I + M>
= F + 1) is indicated by the carryout generated from I + M, and state 2 (I + M> = L + 1) is indicated by the absence of the carryout generated from I + M. If M is negative, there are three possible states for the logic used by the toroid address generator. (1) I
+ M <0, (2) I + M <(L \) 0, and (3) I + M> = (L \).

For state 1 where M is a negative number and I + M <0. The absolute address (I + M) is a negative number and falls below the lower bound (L \) of the circular buffer. Therefore, it is necessary to wrap the next target address in the higher area of the buffer. The next target (wrap) address I can be calculated by adding the buffer length to the absolute address. The formula is I + M + L + 1. M is a negative number and I + M <(L
In case of state 2 which is \). The absolute address again falls below the lower bound (L \) of the circular buffer. Therefore, the next target (wrap) address I becomes I + M + L + 1.
For state 3 where M is a negative number and I + M> = (L \).
The absolute address (I + M) does not fall below the lower boundary (L \). Therefore, the target address I is equal to I + M.

For hardware execution, State 1 (I + M <0), where M is a negative number, can be indicated by the lack of carry out generated from I + M, and State 2 (M + N <(L \)) Is I + M + L + 1
It can be indicated by the lack of carry out generated from.

Therefore, the hardware implementation of the implicit upper bound address boundary circular buffer is logically performed as shown in FIG. The logic of FIG. 4 includes a first adder 301 and a second adder 302. At the input to the first adder 301 are the values I and M. The output of the first adder 301, called the absolute address, is
7 and is equal to I + M. The carry-out signal from adder 301 is provided on line 306. The input to the second adder 302 is the exclusive NOR gate 303.
And the output from the first adder 301 to line 307. The inputs to the exclusive NOR gate 303 are:
There are sign bits for the length value L and the address offset M. The second adder 302 receives the M code bits as a carry-in from line 311. The output of the second adder 302, here called the wrap address, is provided on line 309. Multiplexer 313 receives as input the absolute address from line 307, line 3
09 receives the wrap address and supplies the next destination address on line 310. A control signal, which indicates whether the calculated absolute address or wrap address is provided as an output, is provided from line 312 to multiplexer 3
13 is supplied. The signal on line 312 comes from the output of multiplexer 314, which
14 operates according to the sign bit of M from line 311, when the sign bit of M is 1 (M is a negative number),
The logic is selected for when the sign bit of M is 0 (M is a positive number).

If the sign bit of M is 1, NA
The output of the ND gate 305 is used as a control signal on the line 312.
Is supplied to. The inputs of NAND gate 305 include a carry-out signal from first adder 301 to line 306 and a carry-out signal from second adder 302 to line 308. Therefore, the sign bit of M is 1
, The first adder 301 and the second adder 302
Of at least one carry-out signal of 0, the wrap address is selected, and the first adder 301 and the second adder 301
If both carry-out signals of the adder 302 of 1 are 1, the absolute address is selected.

If the sign bit of M is 0, the first
The carry-out of the adder 301 of line 1 to line 306 is supplied to line 312 as a control signal. Therefore,
If the sign bit of M is 0, the wrap address is selected if the carry-out signal on line 306 is 1. If the sign bit of M is 0, the absolute address is selected if the carry out signal on line 306 is 0.

FIG. 5 is a block diagram of one possible embodiment in which two adders 401, 402 are shared by a lower bound scheme and an upper bound scheme.
The device has four inputs and one output. Input is: 1. Buffer length L409, which is a program value (actual buffer length is L + 1). 2. The boundary of the current access address A407, circular buffer is implicit in A and L. 3. Offset M408 between current address 407 and destination address 414. M is a signed value. M
The absolute value of is not greater than L. 4. Programmable control signal from line 431. This is used to select whether to use a buffer based on the implied lower bound or the implied upper bound. The output is: 1. Next destination address 414. This is used as the current address 407 for the next address generation.

The adder 401 executes addition of A407 and M408 to generate the sum 412-absolute address,
A carry out 419 is generated from each bit weight. X
NOR 403 is used to take the inverse of L409 when the sign bit 410 of M408 equals 0. M
If the sign bit 410 of 408 is equal to 1, then XN
The output 411 of the OR 403 becomes equal to L409. The adder 402 performs a carry-in addition equal to the sign bit 410 of M408 at the absolute address 412, the output 411 of the XNOR 403, and the least significant bit,
The carry-out 420 is generated from the sum 413-wrap address and each bit weight. Destination address 41
4 uses multiplexer 404 using control signal 418.
Depending on absolute address 412 or wrap address 41
It is selected from 3. The priority selector 421 is
The carry-out 419 of the adder 401 is selected as the output 415 from the carry-out 419 of the adder 401 by detecting the leading "1" of L409. The priority selector 422 selects the carry-out of the N-th bit from the carry-out 420 of the adder 402 as the output 416 according to L409. Wire 43
A 1 is used to select one of the two inputs of multiplexer 423, and if wire 431 is equal to 0, control signal 418 is the one received from wire 425. This also means that this buffer is defined as the lower boundary criterion. Also, if wire 424 is selected, its buffer is based on the upper bound.

When wire 431 is 0, this buffer is based on the lower bound. If M is a positive number, then wire 428 is selected as control signal 418 by multiplexer 426, wire 425, and multiplexer 423. The carry-out 415 generated by the adder 401 and passed through the priority selector 421, or generated by the adder 402 and transmitted by the priority selector 4
If at least one of the carry-outs 416 passed through 22 is set, the sum 413 (wrap address) of the adder 402 is selected as the target address 414 by the multiplexer 404. OR function is OR gate 430
Executed by Wire 428 is OR gate 430
Is also the input of multiplexer 426.
If M is negative, wire 427 causes multiplexer 4
26, wire 425, and multiplexer 423 to select as control signal 418. If the carry-out 415 generated by the adder 401 and passed through the priority selector 421 is clear, the adder 40
The target address 41 is the sum 413 (wrap address) of 2
Selected as 4. The inverter 429 uses the wire 41
Used to recognize the clear state of 5 and wire 427
Is the output of the inverter 429.

If the wire 431 is set to 1,
This buffer is the upper boundary criterion. If M is a positive number, then wire 415 is the multiplexer 406, wire 4
24 and control signal 4 by multiplexer 423
Selected as 18. Carry out 41 generated by adder 401 and passed through priority selector 421
5 is set, the sum 413 (wrap address) of the adder 402 is selected by the multiplexer 404 as the next target address 414, otherwise, the absolute address generated by the adder 401 is selected. To be done. If M is negative, wire 417 causes multiplexer 406, wire 424, and multiplexer 423.
Selected as control signal 418 by. Adder 40
If the carry-out 415 generated by 1 and passed through the priority selector 421 or at least one of the carry-outs 416 generated by the adder 402 and passed through the priority selector 422 is removed, the sum 413 (wrap Address) is selected as the next destination address 414 by the multiplexer 404, else the absolute address is selected.
The OR function is performed by NAND gate 405.
Wire 417 is the output of NAND gate 405 and the input of multiplexer 406.

In one embodiment of the invention, an implicit upper bounds scheme is used alone, as shown in FIG. Figure 6
Then, the adder 501 executes A507 + M508,
Generate an absolute address 512. XN if M508 is a positive number (sign bit 510 of M is equal to 0)
The OR gate 503 takes the opposite of L509. If M508 is a negative number (sign bit 510 of M equals 1), the output 511 of XNOR 503 equals L509. The adder 502 has an absolute address 512, XNOR5
The output 511 of 03 and the carry-in addition equal to the sign bit 510 of M in the least significant bit. The output 513 of adder 502 is a wrap address and is selected if the absolute address is above the buffer boundary. The desired output 514 is selected by the multiplexer 504 from the absolute address 512 or the wrap address 513 using the control signal 518.

If M is a positive number, signal 515 is selected by multiplexer 506 as control signal 518. The priority selector 521 selects the carry-out of the Nth bit from the carry-out 519 of the adder 501 as the output 515 by detecting the leading “1” of L509. The output 515 of the priority selector 521 represents the carry-out state of the Nth bit of the adder 501. N from the adder 501
A "1" in the second carry out means that the absolute address (A + M) is above the upper boundary of the buffer and the wrap address 513 is selected as the output 514. Otherwise, absolute address 512 is selected as output 514.

If M is a negative number, signal 517 is selected by multiplexer 506 as control signal 518. In this case, two Ns 515 and 516
The carry out signal of the th bit is used. Lines 515 and 516 are provided to NAND gate 505, which outputs as signal 517.
To supply. A value of "0" in signal 515 indicates that there is no carry out generated by A + M, which means that absolute address 512 is negative and below the lower bound of the buffer. Therefore, the wrap address 51
3 is considered the next destination address output 514. The priority selector 522 uses the leading “1” of L509.
The carry-out 520 of the adder 502 to output the carry-out of the Nth bit 51.
Select as 6. The value “0” of the signal 516 is A
It indicates that there is no carry out generated by the adder 502, which means + M <(L \), and the absolute address is below the lower bound of the buffer. In this case, wrap address 5
13 is selected as the next destination address output 514. If the two wrap states do not match, then absolute address 512 is selected as the next destination address output 514.

In summary, an address generator is provided that generates an address for accessing a circular buffer in linear memory space. This buffer has a programmed length (L + 1) and the buffer base is defined by an implied lower bound or an implied upper bound. If an implied lower bound is used to define a toroidal buffer, the lower bound will be the address of all low N bits of 0. Here, N is a bit position where the leading 1 of L is located. If an implied upper bound is used to define a toroidal buffer, then the upper bound will be an address with all 1s in the low N bits. The absolute address is calculated by adding the offset M to the current address A. Here, M is a signed number, and the absolute value of M is smaller than L. If the absolute address exceeds the buffer boundary,
Wrap on another side of the boundary by adding or subtracting the buffer length (L + 1). in this way,
The next target address is always in the buffer. Such address generators are used not only in digital signal processing applications, but also in other data processing applications.

While the present invention has been disclosed in detail above with reference to preferred embodiments and examples, it is to be understood that these examples are provided in an illustrative rather than a restrictive sense. . It is anticipated that modifications and combinations within the spirit and scope of the invention will readily occur to those skilled in the art.

[Brief description of drawings]

FIG. 1 is a simplified block diagram of an integrated circuit processor with an upper and lower ring address generator of the present invention.

FIG. 2A shows an address range of an implicit lower limit address boundary circular buffer according to the related art, FIG. 2B shows an address range of an implicit upper address boundary circular buffer according to an embodiment of the present invention, and FIG. ) Indicates an address range of a combination upper and lower limit address boundary according to the embodiment of the present invention.

FIG. 3 is a simplified logic diagram of address calculation by prior art implicit lower bound address boundary circular addressing.

FIG. 4 is a simplified logical diagram of address calculation by implicit upper limit address boundary circular addressing according to an embodiment of the present invention.

FIG. 5 is a logical diagram of address calculation by combined implicit upper and lower limit address boundary circular addressing according to an embodiment of the present invention.

FIG. 6 is a logical diagram of address calculation by implicit upper limit address boundary circular addressing, which is an embodiment of the present invention, and shows a priority selector block for selecting carry out at position N;

Claims (26)

[Claims] 1. A device for generating an address of a circular address buffer of a memory, the device comprising: an input for receiving a current address A, an address offset M, a buffer length value L and a control signal; and A, M and L. In response to the control signal, a first memory address and a second memory address for the memory location are calculated, and one of the first and second memory addresses is provided in response to the control signal. Logic and the first memory address has an address boundary X,
Matches the sum of the current address A and the address offset M of the first circular buffer containing addresses X to (X + L), the second memory address having an address boundary Y, and from Y to ( Y-L), which is equal to the sum of the current address A and the address offset M of the second circular buffer containing addresses. 2. The apparatus according to claim 1, wherein the L is a leading 1 at a bit position N when represented by a binary number.
The address boundary X is calculated by replacing the low order N bits of the current address A with 0, and the address boundary Y replaces the low order N bits of the current address A with 1. A device characterized by being calculated by. 3. The apparatus of claim 1, wherein the input comprises a register storing the A, M and L. 4. The apparatus of claim 1, wherein the inputs include registers for storing the A, M, L and the control signals. 5. The apparatus of claim 1, wherein the logic produces a first output equal to the sum A + M by a carry-out signal, and wherein the sign of M is positive. The second wrap address sum (A + M) is equal to the first wrap address sum (A + M)-(L + 1), or when the sign of M is a negative number.
A second adder that produces a second output equal to + (L + 1) by a carry-out signal; and the first output or the first output depending on the carry-out signal from the first and second adders. A selection logic for selecting the second output. 6. The apparatus according to claim 1, wherein the L is a leading 1 at a bit position N when represented by a binary number.
The address boundary X is calculated by replacing the low order N bits of the current address A with 0, and the address boundary Y replaces the low order N bits of the current address A with 1. A first adder for producing a first output equal to the sum A + M by the carry-out signal at the bit position N, and a first wrap when the sign of M is positive. The second wrap address sum (A + M) when the sum of the addresses is equal to (A + M)-(L + 1) or the sign of M is a negative number.
A second output equal to + (L + 1) is sent to the bit position N
In a second adder generated by a carry-out signal, the carry-out signal from the first and second adders, and the control signal, the first output or the second output. An apparatus comprising selection logic for selecting an output. 7. The apparatus according to claim 6, wherein the selection logic is configured such that the control signal is set to the first memory address, the address offset is a positive number, and the first offset is a positive number.
If neither the carry-out from the adder nor the carry-out from the second adder is 1, or the control signal is set for the first memory address and the address offset is a negative number. , The first
If the carry-out from the adder is 1, or the control signal is set to the second memory address and the address offset is a positive number,
If the carry-out from the adder is 0, or the control signal is set to the second memory address and the address offset is a negative number,
Select the output of the first adder when the carry-out from both the adder and the second adder is 1, and the control signal is set to the first memory address. And the address offset is a positive number, the first
The carry-out from at least one of the adders or the second adders is 1, or the control signal is set to the first memory address and the address offset is a negative number. , The first
If the carry-out from the adder is 0, or the control signal is set to the second memory address and the address offset is a positive number, the first
If the carry-out from the adder is 1, or the control signal is set to the second memory address and the address offset is a negative number,
Of the second adder or at least one of the second adders is 0, the apparatus is configured to select the output of the second adder. 8. A device for generating an address of an annular address buffer having an implied upper limit address boundary of a memory, the device comprising: an input for receiving a current address A, an address offset M, and a buffer length value L; , And L for calculating a memory address for the memory location and providing the memory address, the memory address having an address boundary Y, from Y to (Y A device which is equal to the sum of the current address A and the address offset M of the circular buffer containing addresses up to -L). 9. The apparatus according to claim 8, wherein the L is a leading 1 at a bit position N when represented by a binary number.
And the address boundary Y is calculated by replacing the low order N bits of the current address A with one. 10. The apparatus according to claim 8, wherein the input comprises a register for storing the A, M and L. 11. The apparatus of claim 8, wherein the logic is a first adder that produces a first output equal to the sum A + M according to a carry-out signal; and when the sign of M is positive. The second wrap address sum (A + M) is equal to the first wrap address sum (A + M)-(L + 1), or when the sign of M is a negative number.
A second adder that produces a second output equal to + (L + 1) by a carry-out signal; and the first output or the first output depending on the carry-out signal from the first and second adders. A selection logic for selecting the second output. 12. The apparatus according to claim 8, wherein the L is a leading 1 at a bit position N when represented by a binary number.
The address boundary X is calculated by replacing the low order N bits of the current address A with 0, and the address boundary Y replaces the low order N bits of the current address A with 1. A first adder for producing a first output equal to the sum A + M by the carry-out signal at the bit position N, and a first wrap when the sign of M is positive. The second wrap address sum (A + M) when the sum of the addresses is equal to (A + M)-(L + 1) or the sign of M is a negative number.
A second output equal to + (L + 1) is sent to the bit position N
A second adder generated by a carry-out signal, and a selection logic for selecting the first output or the second output according to the carry-out signal from the first and second adders. A device comprising: 13. The apparatus according to claim 12, wherein the selection logic is configured such that the address offset is a positive number and the carry-out from the first adder is 0, or the address offset. Is a negative number and the carry-out from both the first and second adders is 1, selecting the output of the first adder and the address offset is a positive number. And the carry-out from the first adder is 1, or the address offset is negative and the carry-out from at least one of the first adder or the second adder is A device configured to select the output of the second adder if the carry-out is zero. 14. An integrated circuit comprising: a processor, a register coupled to the processor for storing a current address A, an address offset M, and a buffer length value L; a memory; and an address of the memory. , An address generator coupled to the processor, the address generator calculating a first memory address and a second memory address for the memory location in response to the A, M, and L. , Configured to provide one of the first and second memory addresses in response to a control signal, the first memory address having an address boundary X,
Matches the sum of the current address A and the address offset M of the first circular buffer containing addresses X to (X + L), the second memory address having an address boundary Y, and from Y to ( Y-L), an integrated circuit which is equal to the sum of the current address A and the address offset M of the second circular buffer. 15. The integrated circuit according to claim 14, wherein the L is a leading 1 at a bit position N when represented by a binary number.
The address boundary X is calculated by replacing the low order N bits of the current address A with 0, and the address boundary Y replaces the low order N bits of the current address A with 1. An integrated circuit characterized by being calculated by. 16. The integrated circuit according to claim 14, wherein the processor includes a decoder responsive to an instruction to store the values A, M and L in the register. 17. The integrated circuit according to claim 14, wherein the value A and the control signal are stored in a single register of the register. 18. The integrated circuit according to claim 14, wherein the address generator generates a first output equal to a sum A + M according to a carry-out signal, and the sign of M is a positive number. Is equal to the first wrap address sum (A + M)-(L + 1), or when the sign of M is a negative number, the second wrap address sum (A + M)
A second adder that produces a second output equal to + (L + 1) by a carry-out signal; and the first output or the first output depending on the carry-out signal from the first and second adders. An integrated circuit including a selection logic for selecting a second output. 19. The integrated circuit according to claim 14, wherein the L is a leading 1 at a bit position N when represented by a binary number.
The address boundary X is calculated by replacing the low order N bits of the current address A with 0, and the address boundary Y replaces the low order N bits of the current address A with 1. A first adder for generating, at the bit position N, a first output equal to the sum A + M by the carry-out signal, the address generator calculating a first output when the sign of M is a positive number; Wrap address sum (A + M)-(L + 1), or the second wrap address sum (A + M) when the sign of M is negative.
A second output equal to + (L + 1) is sent to the bit position N
In a second adder generated by a carry-out signal, the carry-out signal from the first and second adders, and the control signal, the first output or the second output. An integrated circuit comprising selection logic for selecting an output. 20. The integrated circuit according to claim 19, wherein the selection logic is such that the control signal is set for the first memory address, the address offset is a positive number, and
If neither the carry-out from the adder nor the carry-out from the second adder is 1, or the control signal is set for the first memory address and the address offset is a negative number. , The first
If the carry-out from the adder is 1, or the control signal is set to the second memory address and the address offset is a positive number,
If the carry-out from the adder is 0, or the control signal is set to the second memory address and the address offset is a negative number,
Select the output of the first adder when the carry-out from both the adder and the second adder is 1, and the control signal is set to the first memory address. And the address offset is a positive number, the first
The carry-out from at least one of the adders or the second adders is 1, or the control signal is set to the first memory address and the address offset is a negative number. , The first
If the carry-out from the adder is 0, or the control signal is set to the second memory address and the address offset is a positive number, the first
If the carry-out from the adder is 1, or the control signal is set to the second memory address and the address offset is a negative number,
An adder or at least one of said second adders is 0, the integrated circuit is configured to select the output of said second adder. 21. An integrated circuit comprising: a processor, a register coupled to the processor for storing a current address A, an address offset M, a buffer length value L; a memory; and an implied upper limit address boundary of the memory. And an address generator for generating an address of a toroidal address buffer having:
Configured to calculate a memory address for a location of the memory and provide the memory address, the memory address having an address boundary Y, from Y to (Y-
An integrated circuit characterized by being equal to the sum of the current address A and the address offset M of a circular buffer containing addresses up to L). 22. The integrated circuit according to claim 21, wherein the L is a leading 1 at a bit position N when represented by a binary number.
An integrated circuit wherein the address boundary Y is calculated by replacing the low order N bits of the current address A by one. 23. The integrated circuit according to claim 21, wherein the processor includes a decoder responsive to an instruction to store the values A, M and L in the register. 24. The integrated circuit according to claim 21, wherein the address generator produces a first output equal to a sum A + M according to a carry-out signal, and the sign of M is a positive number. Is equal to the first wrap address sum (A + M)-(L + 1), or when the sign of M is a negative number, the second wrap address sum (A + M)
A second adder that produces a second output equal to + (L + 1) by a carry-out signal; and the first output or the first output depending on the carry-out signal from the first and second adders. An integrated circuit including a selection logic for selecting a second output. 25. The integrated circuit according to claim 21, wherein the L is a leading 1 at a bit position N when represented by a binary number.
The address boundary X is calculated by replacing the low order N bits of the current address A with 0, and the address boundary Y replaces the low order N bits of the current address A with 1. A first adder for generating, at the bit position N, a first output equal to the sum A + M by the carry-out signal, the address generator calculating a first output when the sign of M is a positive number; Wrap address sum (A + M)-(L + 1), or the second wrap address sum (A + M) when the sign of M is negative.
A second output equal to + (L + 1) is sent to the bit position N
A second adder generated by a carry-out signal, and a selection logic for selecting the first output or the second output according to the carry-out signal from the first and second adders. An integrated circuit comprising: 26. The integrated circuit according to claim 25, wherein the selection logic is such that the address offset is a positive number and the carry-out from the first adder is 0, or Selecting an output of the first adder when the offset is a negative number and the carry-out from both the first adder and the second adder is 1, and the address offset is positive. A number and the carry out from the first adder is 1, or the address offset is negative and from at least one of the first adder or the second adder. An integrated circuit configured to select the output of the second adder when the carry-out is zero.