JP2003219172A - Image processing apparatus and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a good image without enlarging a scale of a circuit. <P>SOLUTION: The image processing apparatus is provided with a plurality of pixels, imaging means including a plurality of output portions outputting signals from the plurality of pixels, and correction means performing a linearity correction of the signals output from the plurality of output portions. The image processing apparatus is characterized in that the correction means includes multiplication means for multiplying the signals from the plurality of output portions by a coefficient, and addition means for adding a coefficient to the signals from the plurality of output portions. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus having an image pickup means including a plurality of pixels and a plurality of output sections for outputting signals from the plurality of pixels.

[0002]

2. Description of the Related Art Due to recent advances in semiconductor processes and production technologies, A4 consumer scanners have a proven track record, are inexpensive, and require a small amount of light from a light source. In the reading device,
CIS using multiple sensor chips arranged in series
The use of (contact type image sensor) has come to be considered.

Further, in response to the speeding up of copying machines, CCD
A type of sensor in which the image sensor is divided into two blocks at the center and read from both ends has come into consideration.

[0004]

In the CIS, a plurality of chips are arranged in series. It is possible to match the black and white levels with a known shading correction. The white level is generally set for each pixel, and the black level is variously proposed for each chip, each pixel, and the like, and all are known. However, the known shading correction is a reading correction method on the assumption that the image reading signal has ideal linearity. Therefore, when the linearity characteristics of each chip of the multi-chips vary, the read signal level is not uniform in the halftone, a density difference occurs between adjacent chips, and a problem of significant quality deterioration occurs. It was

In the sensor of the type in which the CCD image sensor is divided into two blocks at the center and read from both ends, even if the black and white levels are matched by the known Shading correction, both ends are read, a plurality of amplifiers, etc. Due to the difference in the characteristics, the linearity characteristics are varied between the left and right of the divided center, the read signal levels are not uniform in the halftone, the density difference is generated, and the quality is remarkably deteriorated.
This was especially noticeable at the joints that were divided at the center.

For each of the above problems, generally known ROM and RA are used as linearity correction means.
The problem was solved by the LUT (look-up table) configured by M.

The LUT can arbitrarily realize a curve by giving an input signal as an address and reading the data stored in the address of the output signal as the output signal. Therefore, this is an ideal correction method when the number of signals to be corrected is small.

However, for example, in a CIS of 16 chips and further in color, if this structure is to be followed as it is, a total of 48 LUTs will be required for 16 chips × 3 colors, and thus it will be composed of a discrete memory. Moreover, I faced the problem that the circuit would become so large that it would be unrealistic to be built into the ASIC.

Further, in the CCD image sensor of the type that reads from both ends, when the ODD / EVEN output is from both ends as usual, four LUTs are required for monochrome, and for color, it is three times as many as 12 LUTs. An LUT is needed. This number cannot be overlooked.

That is, in a system having a plurality of signals having different linearity characteristics, which cannot be completely corrected by the known shading correction, specifically, the chip or block having different characteristics, that is, the linearity of the halftone between the outputs is obtained. As a result of aiming at multi-chip like CIS or aiming at multi-read out like high-speed CCD, the problem of variation has been highlighted.
Especially with color, it is 3 times more difficult.

Further, a chip that requires linearity correction,
If LUTs are prepared for the number of blocks and outputs, today's energy-saving and low-power consumption is claimed, and the reading unit such as a copying machine is normally turned off and wants to start reading as soon as possible. Even in the case, even if the simplest linear line is used, the use of many LUTs is not desirable from this point of view, since the curve calculation of the LUT by the CPU and the RAM writing alone consumes about 5 seconds, for example. I reached the conclusion.

[0012]

In order to solve the above-mentioned problems, an image pickup unit including a plurality of pixels and a plurality of output units for outputting signals from the plurality of pixels, and an output from the plurality of output units Correction means for performing linearity correction of the generated signal, wherein the correction means adds a coefficient to the signals from the plurality of output units and a coefficient to the signals from the plurality of output units. There is provided an image processing device including an adding unit.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a diagram showing an image processing apparatus according to a first embodiment of the present invention.

Reference numeral 202 designates a CIS (contact image sensor) module having a multi-chip image sensor which is an image pickup means including a plurality of pixels and a plurality of output sections for outputting signals from the plurality of pixels. is there. As shown in FIG. 2, in the multi-chip sensor 2024, a plurality of sensor chips in which a plurality of pixels are arranged in one direction (main scanning direction) are arranged on a mounting board 2024-5 in the same direction as the arrangement of the pixels (chip).
1 to 16) are arranged.

FIG. 3 shows a multi-chip image sensor 20.
The details of one sensor chip (for example, chip1) of 24 are shown.

Each rectangle represents a read pixel. Since this is a multi-chip sensor for reading at the same size of 600 dpi, the interval of one pixel is 42 × 42 μm.
2024-1 is a pixel column for reading red (R) light, and 2024-2 and 2024-3 are pixel columns for sequentially reading green (G) light and blue (B) light.

Each pixel in the pixel column 2024-1 has an R
Color filter, each pixel of the pixel row 2024-2 is provided with a G color filter, and each pixel of the pixel row 2024-2 is provided with a B color filter,
A photodiode, which is a photoelectric conversion unit, is formed under each color filter. Here, the three pixel rows are formed at an interval of 42 μm per pixel in the sub-scanning direction (direction in which the document or the multi-chip image sensor moves). Pixel pitches in the main scanning direction are also arranged at 42 μm intervals.

Electric charges corresponding to the amount of incident light are generated in this photodiode during the accumulation time.

The above-mentioned three pixel rows having different optical characteristics are arranged on the same silicon chip so that the R, G and B pixel rows are arranged in parallel with each other so as to read the same line of the original. It has a monolithic structure.

Reference numeral 2024-4 is a CCD shift register which is a charge transfer section, and a shift pulse is given at the timing of the beginning of one line, whereby 2024-1 and 2024-
The charges move from the openings of 2, 2024-3 to the charge transfer unit.

The charges moved to the charge transfer section 2024-4 are applied with a transfer clock to generate GBRGBR.multidot.
.. are sequentially transferred to the output amplifier unit 2024-5 in time division. The output amplifier unit 2024-5 converts the charges into a voltage, and then outputs signals in the order of GBRGBR as a voltage output.

The analog signal processing unit 101 has a gain offset adjusting circuit for performing gain offset adjustment on the signals from the respective output units (OS1 to 16) and an AD converter for converting into a digital signal.

Further, the analog signal processing section 101 has a structure having two analog processors (AP1, 2), each of which inputs an analog signal of 8 ch, is multiplexed and time-division digital of 1 ch. Output as a signal.

The rearrangement unit 102 converts the input digital signal into an appropriately rearranged RGB digital signal. That is, first, a signal for each pixel in the R pixel row of chip1, a signal for each pixel in the G pixel row, and a signal for each pixel in the B pixel row are output in parallel, and then, In addition, the sensor chip is configured such that the signal for each pixel of the R pixel column of chip2, the signal for each pixel of the G pixel column, and the signal for each pixel of the B pixel column are output in parallel. Signals are output in sequence for each.

The shading correction unit 103 performs shading correction for each color.

The CPU 108, which is a control means, controls the entire image processing apparatus.

The linearity correction unit 104 is a characteristic part of the present embodiment, and for the digital signal after shading correction, for each sensor chip, for each color, that is, for a plurality of image signals having different linearity characteristics. Perform linearity correction. In the present embodiment, one linearity correction circuit (a total of three) for each color (104a-
c) is provided.

The above configuration is the best in consideration of the balance between the circuit scale and the processing speed, but not limited to the above configuration, one linearity correction circuit for each sensor chip (total of 1
6) may be provided, or a linearity correction circuit (48 in total) may be provided for each sensor chip and for each color (in the case of this configuration, a main scanning position determination unit described later). Does not have to be).

In the case of monochrome, it is desirable to provide one linearity correction circuit for the whole in consideration of the balance between the circuit scale and the processing speed, but it is possible to provide one linearity correction circuit for each sensor chip. good.

FIG. 4 is a diagram for explaining the concept of linearity correction.

The input signal is represented by the x coordinate, and the output signal corresponding to it is represented by the y coordinate. x-axis is 4 in the figure
It is divided into two domains. Input signal is 10 bits
Therefore, the value is 0 to 1023.

Here, a linear function is given to each domain as follows.

0 ≦ x <x1: Y = A1 * X + B1; x1 ≦ x <x2: Y = A2 * X + B2; x2 ≦ x <x3: Y = A3 * X + B3; x3 ≦ x <x4: Y = A4 * X + B4; where X is an input signal, Y is an output signal, and A1 to A4
Is a multiplication coefficient, and B1 to B4 are addition factors of the Y intercept of the linear function. Each linear function can be represented by a straight line,
Since the definition area is fixed, it becomes a line segment, and each line segment is determined by the CPU 108 as a control means so as to be continuous.

As a result, as shown in the graph of FIG. 4, coordinates (0,
A slightly upward convex three-point line graph that passes through 0) and (1023, 1023) is realized.

By providing the linearity correction function in this way, linearity correction can be performed. In addition,
There is no doubt that a curve graph can be better corrected than a line graph, but in actual measurement, the deviation of the linearity of each signal from the ideal straight line is not significant and
At 0 bit, the center has about 8 levels, and at 8 bit, there are about 2 levels, and the correction by the line graph is sufficient.

In order to correct the linearity with a three-point polygonal line, the domain is divided into four areas for description. However, in the configuration of the present embodiment, the number of arbitrary points is determined by connecting the line segments continuously. A polygonal line can be realized.

A method of obtaining the linearity correction function as shown in FIG. 4 will be described below.

A halftone chart is read in order to correct halftone. First, a density D0.3 chart is prepared and read after shading correction, and the reading level of each chart is obtained for each color of 16 chips. The average value of the reading is obtained for each of the RGB colors. Using the obtained average value as the target value for each color, D
0.3 CPU 108 draws the graph so that the same reading can be obtained for each chip when reading the chart.
Will be done at.

Next, the density D is corrected to correct the dark portion.
1.1 Prepare a chart and perform reading after shading correction, and find the reading level of each chart for each color of each of 16 chips. The average value of the reading is obtained for each of the RGB colors. With the obtained average value as the target value for each color, the CPU 108 draws the graph so that the same reading value for each chip can be obtained when the D1.1 chart is read.

Next, in order to correct the brighter part, the density D
A 0.2 chart is prepared and read after shading correction, and the read level of each chart is obtained for each color of each of 16 chips. The average value of the reading is obtained for each of the RGB colors. Using the obtained average value as the target value for each color, the CPU 108 draws the graph so that the same read value for each chip can be obtained when the D0.2 chart is read.

As a result, black, D1.1, D0.3, D
The linearity can be corrected so that the reading levels of the respective chips are equal to 0.2 and white.

The above-described operation of obtaining the linearity correction function may be carried out at the time of factory shipment (the same value is used thereafter), or may be carried out every time of the operation of reading the original.

FIG. 5 is a diagram showing details of the linearity correction section. Here, one linearity correction circuit (for example, for R) is shown, but other linearity correction circuits have the same configuration.

The X-axis section discriminating unit 1041 discriminates the section of the X-axis in FIG. 4 and discriminates which of the four linear functions is to be applied. The determined output is given by n and sent to the coefficient selection unit 1042. Main scanning position determination unit 1046
Outputs the main scanning position signal k indicating which sensor chip of the plurality of sensor chips arranged in the main scanning direction the signal to be processed is. The delay unit 1043 matches the clock phase.

In the coefficient selection unit 1042, the section discrimination signal n
And the main scanning position signal k, the multiplication coefficient Akn and the addition factor Bkn are selected, and the multiplication circuit 1044 and the addition circuit 10 are selected.
Give to 45. As a result, Y = Akn * X + Bkn is calculated, and the linearity correction described in FIG.
It is realized for each chip.

Since the coefficients Akn and Bkn of the present embodiment are different coefficients depending on the signal level of the signal to be corrected and the sensor chip that outputs the signal to be corrected, each linearity correction circuit has 64 (4) X16) will have different coefficients.

The coefficient selecting unit of the present embodiment has a configuration in which one linearity correction circuit is provided with 64 registers constituted by flip-flops for multiplication circuits and 64 registers constituted by flip-flops for addition circuits. Is. Then, the coefficient is output from each register.
Appropriate values are written in the registers from the CPU when the power is turned on. The coefficients Akn and Bkn are given as register setting values, and it goes without saying that the writing time is shortened without comparing with writing all curves in the LUT.

The present invention is not limited to the above configuration,
For example, the value of each coefficient may be stored in a ROM or SRAM. However, the capacity of each coefficient is not so large, and ROM or SRAM
Since many of the addresses are wasted and expensive when stored in the memory, it is necessary to configure them with registers.
This is the most suitable structure in consideration of price and the like.

As described above, it is possible to obtain the effect of eliminating the difference in the read density in the halftone by adjusting the niality of the image signals having different linearities.

The clock generator 121 generates a clock VCLK for each pixel. Further, the main scanning address counter 122 counts the clocks from the clock generator 121 and generates a pixel address output for one line. Then, the decoder 123 uses the main scanning address counter 12
The main scanning address from 2 is decoded to generate a line unit sensor drive signal such as a shift pulse (φSH) and a reset pulse (φR), and a line synchronization signal HSYNC. The main scanning address counter 122 is HSYNC.
It is cleared by a signal and the counting of the main scanning address of the next line is started.

Next, the operation of the image processing apparatus shown in FIG. 1 will be described.

First, an analog signal is output from the multi-chip sensor. FIG. 6 is a diagram illustrating the timing of analog signals from the multi-chip image sensor.

This timing chart shows the same timing for each sensor chip. φSH is a line synchronization signal and is also a charge transfer pulse from the photodiode to the CCD analog shift register. φM is a transfer pulse of the CCD analog shift register, and the sequentially transferred charges are G1, B1, R after dummy output as shown in the figure.
1, G2, B2, R2, ... And output from the output amplifier like OS1 to OS16. ΦRS is a reset pulse that gives a reset signal for the CCD.

The analog signal output from the multi-chip sensor 202 is input to the analog signal processing unit 101, where gain adjustment and offset adjustment are performed, and then A
/ D converted. The rearrangement unit 102 appropriately rearranges and converts each color signal into 10-bit digital image signals R1, G1, and B1.

Next, the shading correction unit 103 inputs the shading correction for each color using the read signal of the standard white plate 206.

The details of the shading correction operation will be described with reference to the drawing showing the shading correction section in FIG. For simplicity, only one of RGB is shown.

In the shading data sampling operation, first, the light source is turned off, and the black reference data B is set for each pixel.
Sample k (i) and store in line memory 1. Next, at the position of the white reference plate, the light source is turned on and the white reference data WH (i) is sampled and stored. Further, the calculation 1 / (WH (i) -Bk (i)) for converting into white shading correction data is performed and stored in the line memory 2.

At the time of actual image reading, OUT (I) =
(IN (i) -Bk (i)) × 1 / (WH (i) -Bk
The calculation such as (i) is performed for each pixel in real time, and the data after shading correction is output.

IN (i) is the i-th input data, OUT (i) is the i-th output data, and Bk (i) is the i-th black reference data in the line memory 1. 1 / (WH
(I) -Bk (i)) is the i-th white shading correction data.

In general, in the case of CIS, black noise is large because the pixel is large, and the offset value is different for each of a plurality of chips. Therefore, even in the case of black shading, correction for each pixel is performed. There is a feature that it is desirable to have a memory to store the values. On the other hand, in the case of CCD, it is common to have a register for uniformly subtracting for such ODD / EVEN.

In the case where cost is prioritized even in the CIS, the cost may be reduced by having a black correction value for each chip.

FIG. 8 is a diagram for explaining the timing of the images rearranged by the rearrangement unit 102. R for simplicity
Only one color of GB is shown.

After the line synchronization signal HSYNC, a dummy signal peculiar to the sensor appears for a while. Next, in the effective pixel area, the signals of n sensor chips are sequentially output from the head chip, such as Chip1, Chip2, ..., ChipN. In this example, N = 16. Each Chip has 468 pixels and 468 × 16
= 7,488 effective pixels are obtained. Next, the dummy pixel is output again. While the signal of each chip is being output, the corresponding main scanning position signal k is output from the main scanning position discriminating unit shown in the figure.

The signal from the shading correction unit is input to the linearity correction unit and linearity correction is performed. Here, one linearity correction circuit will be described as an example.

First, the signal from the shading correction section is input in parallel to the delay section 1043 and the X-axis section determination section 1041. Then, the X-axis section determination unit determines the magnitude of the signal level of the signal (determines which section described in FIG. 4), and outputs the corresponding section determination signal n.

Further, the main scanning position discriminating section outputs the main scanning position signal k indicating which sensor chip the signal input from the above-mentioned shading correcting section is. .

From the coefficient selecting section, the coefficient Akn and the coefficient Bk selected according to the section discrimination signal n and the main scanning position signal k are selected.
n is output, the multiplication circuit 1043 multiplies the signal from the delay unit 1043 by the coefficient Akn, and the addition circuit 1045 adds the signal from the multiplication circuit and the coefficient Bkn.

Thereafter, the signal from the linearity correction section is input to an image processing circuit (not shown) and various corrections such as color correction and gamma correction are made.

Next, an image forming apparatus equipped with the image processing apparatus described above will be described.

In FIG. 9, an image scanner unit 200 reads a document and performs digital signal processing here. A printer unit 300 prints an image corresponding to the original image read by the image scanner unit 200 on paper in full color.

First, the CIS module 202 used in this embodiment will be described.

As shown in FIG. 10, the cover glass 202
1, an illumination light source 2022 formed of an LED, an equal-magnification imaging lens 2023 formed of a SELFOC lens, and a multi-chip image sensor 2024 are mounted on a substrate 2025, and they are integrated by being attached to a mold 2026. The CIS module 202 is formed.

FIG. 11 is a perspective view of the configuration of FIG.

In the image scanner section 200, AD
Platen glass (platen) 20 with the original platen of F203
The original 204-1 placed on the sheet 5 is illuminated with the light from the illumination light source 2022 in the CIS module shown in the figure. The light reflected from the original 204 forms an image on the multi-chip image sensor 2024 by the lens 2023.

The CI is placed at the position of the flow reading glass 208.
By bringing S module 202, ADF2
Documents can be continuously supplied and read from No. 03.

The multi-chip image sensor 2024 is
After the light information from the manuscript is color-separated and the red (R), green (G), and blue <B> components of the full-color information are read, the signal processing unit 100 (in the circuit parts after 101 in FIG. 1). Equivalent) to send. Each of the color component read resensor rows of the multi-chip image sensor 2024 has 7
It is composed of 500 pixels. As a result, the maximum size of the documents placed on the platen glass 205, which is 297 mm in the lateral direction of an A3 size document, is 600d.
Read at pi resolution.

The CIS module 202 has a speed V
Then, the entire surface of the original 204 is scanned by being mechanically moved in the sub-scanning direction.

The white reference plate 206 is a multi-chip image.
R, G, B sensor 2024 formed on the di-sensor
The white correction data of the read data in -1 to 210-3 is generated. The white reference plate 206 has a substantially uniform reflection characteristic with visible light, and has a white color visually. Using this white reference plate 206, the R, G, B sensors 2024
The output data from -1 to 2024-3 are corrected.

In the subsequent stage of the signal processing section, the read signal is electrically processed and decomposed into magenta (M), cyan (C), yellow (Y) and black (Bk) components, It is sent to the printer unit 200. In addition, one component of M, C, Y, and Bk is sent to the printer unit 300 for one document scanning (scan) in the image scanner unit 201, and the copy printout is completed.

In the printer unit 300, M, C, Y, Bk
Each image signal of is sent to the laser driver 312. The laser driver 312 uses the semiconductor laser 31 according to the image signal.
3 is modulated and driven. Then, the laser light scans the photosensitive drum 317 via the polygon mirror 314, the f-θ lens 315, and the mirror 316.

The developing device is composed of a magenta developing device 319, a cyan developing device 320, a yellow developing device 321, and a black developing device 322. These four developing devices are alternately in contact with the photosensitive drum 317, and are placed on the photosensitive drum 317. The formed M, C, Y and Bk electrostatic latent images are developed with corresponding toners. The transfer drum 323 is used for the paper cassette 2
The sheet 24 or the sheet fed from the sheet cassette 325 is wound around the transfer drum 323, and the toner image developed on the photosensitive drum 317 is transferred to the sheet.

In this way, after the toner images for the four colors of M, C, Y, and Bk are sequentially transferred, the paper passes through the fixing unit 326 and is discharged.

(Embodiment 2) Embodiment 2 will be described. In the following, parts different from those of the first embodiment will be described, and description of the same parts will be omitted.

FIG. 12 is a diagram showing an image processing apparatus according to the second embodiment of the present invention.

Reference numeral 213 denotes a central division end readout type CCD image sensor which is an image pickup means including a plurality of pixels and a plurality of output sections for outputting signals from the plurality of pixels.

FIG. 13 shows a CCD image sensor 213.
It is a figure explaining the detail of.

, P7500 denote photodiodes which are photoelectric conversion units, and read and store image information of 7500 pixels in the main scanning direction. The sensor is split left and right between the central 3750 and 3751 pixels. The charge of the photodiode is transferred to the CCD analog shift register by a shift pulse (not shown).

Odd-numbered pixels P1 to P3749 are CCDs.
It is transferred to the analog shift register 2131 and is output as OS1 from the output buffer 2132 according to the transfer clock.

P2 to P3750 even-numbered pixels are CCDs.
The data is transferred to the analog shift register 2133 and sequentially output as the OS2 from the output buffer 2134 according to the transfer clock.

The odd numbered pixels of P3751 to P7499 are transferred to the CCD analog shift register 2135, and are sequentially output from the output buffer 2136 to the OS in accordance with the transfer clock.
It is output as 3.

The even-numbered pixels of P3752 to P7500 are transferred to the CCD analog shift register 2137, and the OS is sequentially output from the output buffer 2138 according to the transfer clock.
It is output as 4.

In this way, the signal of the monochrome 7500 pixels is divided into left and right and also divided into odd and even numbers, and is taken out as four output signals. Therefore, OS1 to OS
4, the same linearity variation as in the first embodiment occurs. In particular, since the image is divided at the central portion, a halftone read density step is generated on the left and right of the dividing line, resulting in deterioration of image quality.

In this embodiment, the description is made in monochrome, but in the case of color, it is realized by forming RGB filters on the photodiode and arranging three CCD image sensors in parallel.

The analog signals of OS1 to OS4 output from the CCD image sensor 213 are gain-offset adjusted by the analog processor unit 151, and A / D conversion is performed.
It is converted and output as two digital signals DS1 and DS2. In the rearrangement unit 152, DS1 and DS2
The image reading direction is corrected by 180 degrees, and the rearrangement is performed so that the central 3750th pixel and the 3751st pixel are properly connected. The R1 signal is a red signal after rearrangement. The shading unit 153 performs shading correction as in the first embodiment.

The linearity correction section 154 corrects the linearity in the same manner as described in the first embodiment with reference to FIGS. 4 and 5.

Although FIG. 12 shows only the red signal, green and blue processing circuits are arranged in parallel in the same manner as in the case of color.

FIG. 14 is a timing chart for explaining the image signal after the rearrangement section 152. HSYNC is a line sync signal. P1 to P7500 are image signals, and rearrangement is performed so that P3750 and P3751 in the center are adjacent to each other. Corresponding to each pixel, the main scanning position signal k is k = for odd-numbered pixels P1 to P3749.
1, P2 to P3750 in even pixels, k = 2, P3
For odd-numbered pixels 751 to P7499, k = 3, P37
It is generated with k = 4 for the even pixels of 52 to P7500.

The main scanning position signal k for k = 1 to 4 is shown in FIG.
Occurs in the main scanning position determination unit 1046.

Hereinafter, similar to the embodiment, the configuration of the reality correction unit in FIG. 5 and the configuration shown in FIG.
By linearity correction of 0, left and right divided at the center,
With odd and even pixels, we succeeded in suppressing the reading density difference and improving the image quality.

FIG. 15 is a diagram showing a cross-sectional structure of an image forming apparatus equipped with the above-described image processing apparatus. In the figure, reference numeral 200 denotes an image scanner unit, which reads a document and performs digital signal processing here.
A printer unit 300 prints out an image corresponding to the original image read by the image scanner unit 201 on paper in full color.

The light source 209 is composed of a xenon lamp and illuminates the original. The first mirror 210 bends the optical information of the document obtained by being illuminated by 90 degrees, and the second mirror 2
Send to 11. The second mirror 211 is a set of two, and the optical information is folded back by 180 degrees, and the reduction and formation lens 2
It is incident on 12. The lens 212 images the optical information on the CCD image sensor 213. The first mirror 209 and the light source 209 as a set scan the document at the speed V, and the second mirror 211 moves in the same direction at half the speed.

The above structure is generally called a reduction optical system type image forming apparatus.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0104]

According to the present invention, it is possible to obtain a good image without increasing the circuit scale.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an image processing device according to a first embodiment.

FIG. 2 is a diagram showing a multi-chip image sensor.

FIG. 3 is a diagram showing details of one sensor chip constituting a multi-chip image.

FIG. 4 is a diagram illustrating linearity correction.

FIG. 5 is a diagram illustrating details of a linearity correction unit.

FIG. 6 is a diagram illustrating timing of a multi-chip image sensor.

FIG. 7 is a diagram illustrating shading correction.

FIG. 8 is a diagram illustrating image timing after rearrangement.

FIG. 9 is a diagram illustrating an image forming apparatus including the image processing apparatus according to the first embodiment.

FIG. 10 is a diagram showing CIS.

11 is a perspective view of the CIS of FIG.

FIG. 12 is a diagram illustrating an image processing device according to a second embodiment.

FIG. 13 is a diagram showing a centrally divided both-end reading CCD image sensor.

FIG. 14 is a diagram illustrating image timing after rearrangement.

FIG. 15 is a diagram illustrating an image forming apparatus equipped with the image processing apparatus according to the second embodiment.

[Explanation of symbols]

202 CIS 213 Central split both-end read CCD image sensor 101, 151 analog signal processing unit 102, 152 sorting section 153 Shading correction unit 154 Linearity correction unit

Continued front page    F term (reference) 5B047 AA01 AB04 BB03 BC14 CB22                       DA10 DC20                 5B057 BA02 CA01 CA02 CA08 CA12                       CA16 CB01 CB02 CB08 CB12                       CB16 CC01 CE11 CH07 CH08                 5C051 AA01 BA04 DA02 DB01 DB07                       DC03 DE11 FA01                 5C072 AA01 BA08 CA04 CA05 DA02                       DA04 DA09 EA05 EA07 FB12                       FB17 FB18 QA05 UA02 UA03                       WA07 XA01                 5C077 LL04 LL17 MP01 MP08 PP10                       PQ12 PQ23 SS01 TT06

Claims (12)

[Claims] 1. An image pickup unit including a plurality of pixels and a plurality of output units that output signals from the plurality of pixels, and a correction unit that performs linearity correction of the signals output from the plurality of output units. The image processing, wherein the correction means includes a multiplication means for multiplying the signals from the plurality of output sections by a coefficient, and an addition means for adding a coefficient to the signals from the plurality of output sections. apparatus. 2. The correcting means includes a coefficient selecting means for selectively outputting a plurality of coefficients, and a first judging means for judging a signal level of a signal from the plurality of output sections, and the first judging means. The image processing apparatus according to claim 1, wherein the coefficient is selected in accordance with a discrimination result by the discrimination unit of No. 1. 3. The correction means is commonly provided for signals output from the plurality of output sections, and determines which output section of the plurality of output sections outputs the signal. 3. The image processing according to claim 2, further comprising a second discriminating unit for selecting a coefficient according to a discriminating result of the first discriminating unit and a discriminating result of the second discriminating unit. apparatus. 4. A rearrangement unit that rearranges the signals output from the plurality of output units so as to sequentially output the signals in the order of pixel arrangement, and the correction unit includes the signals from the rearrangement unit. 4. Inputting the input.
The image processing device according to any one of 1. 5. The image pickup means has a plurality of pixel rows for obtaining different color information, and the correction means is provided one for each color. The image processing device according to item 1. 6. The image processing apparatus according to claim 1, wherein the correction unit is provided for each of the output units of the plurality of output units. 7. The image pickup unit has a plurality of pixel columns that obtain different color information, and the correction unit is provided one for each color of each output unit of the plurality of output units. The image processing apparatus according to claim 1, wherein the image processing apparatus is an image processing apparatus. 8. The image processing apparatus according to claim 2, wherein the coefficient selecting unit includes a register that outputs a coefficient. 9. The image processing according to claim 1, wherein the imaging unit has a plurality of sensor chips in which a plurality of pixels are arranged in a predetermined direction. apparatus. 10. The image processing apparatus according to claim 1, wherein the image pickup unit is a sensor chip that outputs signals from a plurality of pixels from the plurality of output units. . 11. The image processing according to claim 1, further comprising an image forming unit that forms an image from a subject on the image capturing unit, and a light source that emits light. apparatus. 12. An image processing apparatus according to claim 1, further comprising: a printer unit that transfers an image onto paper based on a signal output from the image processing apparatus. Image forming apparatus.