JP2003218222A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can prevent leakage out of ripple component contained in electric source to resistors and capacitors and which can stabilize output voltage. <P>SOLUTION: In this circuit, an occurrence of a parasitic capacity among a n-type semiconductor substrate 40, a resistor R1, and a capacitor C1 can be prevented by forming a p-type well at the position which forms at least one of the resistor R1 and the capacitor C1 on the n-type semiconductor substrate 40 and connecting p-type wells 41, 48 to a specified electric potential of low impedance condition, so that it is possible to prevent leakage out of ripple component contained in electric source to the resistor R1 and the capacitor C1. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit formed on an n-type semiconductor substrate.

[0002]

2. Description of the Related Art FIG. 4 shows a circuit configuration of a constant voltage power supply circuit which is an example of a semiconductor integrated circuit. This semiconductor integrated circuit is a constant voltage power supply circuit that stabilizes and outputs a DC voltage.

In the figure, a DC power supply Vcc is externally supplied to the input terminal 10. The input terminal 10 has a depletion type n-channel FET (field effect transistor) M1.
Of the depletion type n-channel FET M2 is connected to the source and the source of the FET M1. The gate and drain of the FET M2 are connected to the gate and drain of the enhancement type n-channel FET M3, and the source of the FET M3 is grounded to form a reference voltage source. The reference voltage Vref generated at the drain of the FET M3 is supplied to the inverting input terminal of the error amplifier 14.

The input terminal 10 is connected to the source and back gate of a p-channel FET M4 as an output transistor. The FET M4 has its gate connected to the error amplifier 14
Is connected to the output terminal of the
The drain is connected to the output terminal 16. Output terminal 1
6 is grounded via bleeder resistors R1 and R2 connected in series, and the connection point of the resistors R1 and R2 is connected to the non-inverting input terminal of the error amplifier 14. A capacitor C1 for phase compensation is connected between the connection point of the bleeder resistors R1 and R2 and the output terminal 16.

The error amplifier 14 differentially amplifies a voltage obtained by dividing the output voltage Vo by the bleeder resistors R1 and R2 and a reference voltage Vref to generate an error voltage. This error voltage is supplied to the gate of the FET M4, and the FET M4 is drive-controlled so that the output voltage Vo becomes constant.

In the semiconductor integrated circuit shown in FIG. 4, the bleeder resistors R1 and R2 and the capacitor C1 are formed of, for example, polysilicon resistors. FIG. 5 (A) is a cross-sectional structural diagram of the bleeder resistor R1 portion and the capacitor C1 portion when this semiconductor integrated circuit is formed on an n-type semiconductor substrate.
It shows in (B).

In FIG. 5A, an n-type semiconductor substrate 20
An insulating film 21 such as SiO ₂ is formed on the surface of the insulating film 2
A polysilicon resistor 22 is formed on top of the first resistor. The polysilicon resistor 22 is insulated by an insulating film 23 such as SiO ₂ , and both ends of the polysilicon resistor 22 are connected to the output terminal 16 and one end of the bleeder resistor R2 by metal wirings 24 and 25, respectively.

In FIG. 5B, an n-type semiconductor substrate 20
An insulating film 21 such as SiO ₂ is formed on the surface of the insulating film 2
A low-resistance polysilicon layer 24 is formed on the surface 1. The polysilicon layer 24 is insulated by an insulating film 25 such as SiO ₂ .
A low resistance polysilicon layer 26 is formed on the insulating film 25 and is insulated by the insulating film 27. The polysilicon layers 24 and 26 are connected to the output terminal 16 and one end of the bleeder resistor R2 by metal wirings 28 and 29, respectively, and the insulating film 25 is formed.
A capacitor C1 having a dielectric is formed.

[0009]

When a semiconductor integrated circuit is formed on the n-type semiconductor substrate 20 as shown in FIGS. 5A and 5B, the n-type semiconductor substrate 20 is connected to the power supply Vcc. In this case, the n-type semiconductor substrate 2 is interposed via the insulating film 21.
A parasitic capacitance Cp0 is generated between 0 and the polysilicon resistor 22, and a parasitic capacitance Cp1 is generated between the n-type semiconductor substrate 20 and the polysilicon layer 24.

When the power supply Vcc includes a ripple component, the potential of the n-type semiconductor substrate 20 changes due to the ripple component, and the ripple component is input to the error amplifier 12 via the parasitic capacitance Cp0 and amplified, so that the output voltage Vo is output. There was a problem that fluctuated. In addition, the n-type semiconductor substrate 20
There is a problem in that the potential of V fluctuates due to the ripple component, the ripple component leaks to the output terminal 16 through the parasitic capacitance Cp1, and the output voltage Vo fluctuates.

The present invention has been made in view of the above points, and provides a semiconductor integrated circuit capable of preventing a ripple component contained in a power source from leaking out to a resistor and a capacitor and stabilizing an output voltage. The purpose is to

[0012]

According to a first aspect of the invention, in a semiconductor integrated circuit formed on an n-type semiconductor substrate (40), a resistor (R1) and a capacitor ( A p-type well is formed at a position where at least one of C1) is formed, and the p-type well (4
1, 48) to a predetermined potential in a low impedance state to connect the n-type semiconductor substrate (40) and the resistor (R1).
It is possible to prevent a parasitic capacitance from being generated between the capacitor and the capacitor (C1), and the ripple component included in the power source is a resistor (R
1) and the capacitor (C1) can be prevented from leaking out.

According to a second aspect of the present invention, in the semiconductor integrated circuit of the first aspect, the resistor (R1) is a constant voltage power supply circuit for controlling the voltage of the output terminal (16) to be constant. Since it is a bleeder resistor that divides the voltage of the terminal, the n-type semiconductor substrate (40) and the resistor (R1)
It is possible to prevent a parasitic capacitance from being generated between the input terminal and the output terminal, and it is possible to prevent the ripple component included in the power source from leaking to the resistor (R1) and changing the voltage of the output terminal (16).

According to a third aspect of the present invention, in the semiconductor integrated circuit according to the second aspect, the capacitor (C1) is
With the phase compensation capacitor connected in parallel with the bleeder resistor, it is possible to prevent parasitic capacitance from occurring between the n-type semiconductor substrate (40) and the capacitor (C1), and to prevent ripple components contained in the power supply. Capacitor (C1)
It is possible to prevent the output terminal voltage from leaking out and fluctuating.

It should be noted that the reference numerals in the above parentheses are given for easy understanding and are merely examples, and the present invention is not limited to the illustrated modes.

[0016]

1A and 1B are cross-sectional structural views of an embodiment of a semiconductor integrated circuit of the present invention. 4A is a sectional structural view of the bleeder resistor R1 portion in FIG. 4, and FIG. 4B is a sectional structural view of a capacitor C1 portion in FIG.

In FIG. 1A, an n-type semiconductor substrate 40
A p-type well 41 is formed by diffusion of p-type impurities. The p-type well 41 is an n-channel FET of FIG.
They are simultaneously formed in the step of forming the p-type wells of M1 to M3.

N-type semiconductor substrate 40 including p-type well 41
An insulating film 42 such as SiO ₂ is formed on the surface of the
A polysilicon resistor 43 is formed on the surface 2. The polysilicon resistor 43 is insulated by an insulating film 44 such as SiO ₂ , and both ends of the polysilicon resistor 44 are connected to the output terminal 16 and one end of the bleeder resistor R2 by metal wirings 45 and 46, respectively.

Further, one end of a metal wiring 47 is connected to the p-type well 41, and the other end of the metal wiring 47 is grounded. The metal wiring 47 is not limited to the ground level and may have a predetermined potential with low impedance. Further, the n-type semiconductor substrate 40 is connected to the power supply Vcc.

As described above, since the grounded p-type well 41 is interposed between the n-type semiconductor substrate 40 and the polysilicon resistor 44, a parasitic capacitance is generated between the n-type semiconductor substrate 40 and the polysilicon resistor 44. Power source V
When cc includes a ripple component, the n-type semiconductor substrate 4
Even if the potential of 0 fluctuates due to the ripple component, the fluctuation of the output voltage Vo due to the ripple component being input to the error amplifier 12 and being amplified can be prevented.

In FIG. 1B, an n-type semiconductor substrate 40
A p-type well 48 is formed by diffusion of p-type impurities. The p-type well 48 is an n-channel FET of FIG.
They are simultaneously formed in the step of forming the p-type wells of M1 to M3.

N-type semiconductor substrate 40 including p-type well 48
An insulating film 42 such as SiO ₂ is formed on the surface of the
A low-resistance polysilicon layer 49 is formed on the surface 2. The polysilicon layer 49 is insulated by an insulating film 50 such as SiO ₂ .
A low resistance polysilicon layer 51 is formed on the insulating film 50 and is insulated by the insulating film 52. The polysilicon layers 49 and 51 are connected to the output terminal 16 and one end of the bleeder resistor R2 by metal wirings 53 and 54, respectively, and the insulating film 50 is formed.
A capacitor C1 having a dielectric is formed.

Further, one end of the metal wiring 55 is connected to the p-type well 41, and the other end of the metal wiring 55 is grounded. Further, the n-type semiconductor substrate 40 is connected to the power supply Vcc. As described above, since the grounded p-type well 48 is interposed between the n-type semiconductor substrate 40 and the polysilicon layer 49, parasitic capacitance is generated between the n-type semiconductor substrate 40 and the polysilicon layer 49. When the power supply Vcc includes a ripple component, even if the potential of the n-type semiconductor substrate 40 varies due to the ripple component, the ripple component can be prevented from leaking to the output terminal 16 and varying the output voltage Vo. .

Therefore, the frequency / ripple rejection characteristic of the constant voltage power supply circuit of FIG. 4 deteriorates from a low frequency in the conventional semiconductor integrated circuit as shown by the broken line of FIG. The frequency / ripple rejection characteristic of the semiconductor integrated circuit does not deteriorate up to the high frequency range as shown by the solid line and broken line.

By the way, the present invention is not limited to the constant voltage power supply circuit, and may be applied to an amplifier circuit, a comparator and the like as shown in FIG. In FIG. 3, the operational amplifier 60 and the resistor R1
0, R11 and the capacitor C10 constitute an inverting amplifier circuit. The capacitor C10 does not necessarily have to be provided.

Here, the resistors R10 and R11 are as shown in FIG.
Similar to the bleeder resistor R1 in (A), the n-type semiconductor substrate 4
0, a p-type well 41 is formed, and a polysilicon resistor is formed on the p-type well 41 via an insulating film. Further, the capacitor C10 is configured similarly to the capacitor C1 in FIG.

[0027]

As described above, the invention according to claim 1 is
A p-type well is formed at a position where at least one of a resistor (R1) and a capacitor is formed on the n-type semiconductor substrate,
By connecting the p-type well to a predetermined potential in the low impedance state, it is possible to prevent parasitic capacitance from occurring between the n-type semiconductor substrate and the resistor and capacitor, and the ripple component contained in the power supply leaks to the resistor and capacitor. You can prevent it.

According to the second aspect of the present invention, the resistor is a bleeder resistor that divides the voltage of the output terminal by a constant voltage power supply circuit that controls the voltage of the output terminal to be constant. It is possible to prevent generation of parasitic capacitance between the resistor and the resistor, and it is possible to prevent ripple components contained in the power supply from leaking to the resistor and varying the voltage of the output terminal.

According to the third aspect of the invention, the capacitor is a capacitor for phase compensation which is connected in parallel with the bleeder resistor, so that parasitic capacitance can be prevented from occurring between the n-type semiconductor substrate and the capacitor. It is possible to prevent the ripple component contained in the power supply from leaking to the capacitor and fluctuating the voltage at the output terminal.

[Brief description of drawings]

FIG. 1 is a sectional structural view of an embodiment of a main part of a semiconductor integrated circuit of the present invention.

FIG. 2 is a diagram showing frequency / ripple rejection characteristics of the semiconductor integrated circuit of the present invention.

FIG. 3 is a circuit configuration diagram of an amplifier circuit which is another example of a semiconductor integrated circuit.

FIG. 4 is a circuit configuration diagram of a constant voltage power supply circuit which is an example of a semiconductor integrated circuit.

FIG. 5 is a partial cross-sectional structural diagram of a conventional semiconductor integrated circuit.

[Explanation of symbols]

40 n-type semiconductor substrate 41,48 p-type well 42,44,50,52 Insulating film 43 Polysilicon resistor 45, 46, 47, 53, 54, 55 Metal wiring 49,51 Polysilicon layer C1, C10 capacitors M1 to M4 FET (field effect transistor) R1, R2 bleeder resistance R10, R11 resistance

Claims (3)

[Claims] 1. A semiconductor integrated circuit formed on an n-type semiconductor substrate, wherein a p-type well is formed at a position where at least one of a resistor and a capacitor is formed on the n-type semiconductor substrate, and the p-type well is in a low impedance state. A semiconductor integrated circuit characterized by being connected to a predetermined potential of 2. The semiconductor integrated circuit according to claim 1, wherein the resistor is a bleeder resistor that divides the voltage of the output terminal with a constant voltage power supply circuit that controls the voltage of the output terminal to be constant. Semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 2, wherein the capacitor is a phase compensation capacitor connected in parallel to the bleeder resistor.