JP2003218219A - Semiconductor capacitor and method of manufacturing the same - Google Patents

Semiconductor capacitor and method of manufacturing the same

Info

Publication number
JP2003218219A
JP2003218219A JP2002012655A JP2002012655A JP2003218219A JP 2003218219 A JP2003218219 A JP 2003218219A JP 2002012655 A JP2002012655 A JP 2002012655A JP 2002012655 A JP2002012655 A JP 2002012655A JP 2003218219 A JP2003218219 A JP 2003218219A
Authority
JP
Japan
Prior art keywords
film
dielectric film
lower electrode
insulating film
semiconductor capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002012655A
Other languages
Japanese (ja)
Inventor
Hiroaki Tsutsui
宏彰 筒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP2002012655A priority Critical patent/JP2003218219A/en
Publication of JP2003218219A publication Critical patent/JP2003218219A/en
Pending legal-status Critical Current

Links

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor capacitor with a high withstand voltage obtained by laminating a lower electrode, a dielectric film and an upper electrode, with which current leakage can be prevented from generating between the upper and the lower electrodes, and to provide a method of manufacturing the same. <P>SOLUTION: A lower electrode 3 is formed on a semiconductor substrate 2. A first insulating film 4 having a hole is formed on the lower electrode 3. A dielectric film 5 is formed in a depressed shape on the lower electrode 3 and the first insulating film 4. Furthermore, a second insulating film 6 is selectively formed on a sidewall of the depressed portion of the dielectric film 5. An upper electrode 7 is formed so as to cover the dielectric film 5 and the second insulating film 6. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、プレーナ型ICな
どの半導体素子で、特に基板上にトランジスタ素子など
と共に形成される半導体キャパシタの構造とその製造方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element such as a planar IC, and more particularly to a structure of a semiconductor capacitor formed on a substrate together with a transistor element and a manufacturing method thereof.

【0002】[0002]

【従来の技術】プレーナ型ICにおける半導体キャパシ
タの多くは、MIM(Metal Insulator Metal)型で
ある。このMIM型キャパシタは、MIS(Metal Ins
ulatorSemiconductor)型と比較して、低抵抗のキャパ
シタ電極構造を容易に設計できるので、高速動作のキャ
パシタンスを必要とする半導体素子に多く採用されてい
る。また、このMIM型構造の半導体キャパシタは、こ
のほかにも電圧や温度によるキャパシタンス変化率が低
く、安定した電気的特性を有するため、精密なアナログ
半導体装置にも多く採用されている。
2. Description of the Related Art Most of semiconductor capacitors in a planar type IC are of a MIM (Metal Insulator Metal) type. This MIM type capacitor is a MIS (Metal Ins
Since it is easier to design a capacitor electrode structure with a lower resistance than that of a semiconductor (SemiconductorSemiconductor) type, it is often used in semiconductor devices that require high-speed operation capacitance. In addition, the MIM type semiconductor capacitor has a low rate of change in capacitance due to voltage and temperature and has stable electrical characteristics, and is therefore often used in precision analog semiconductor devices.

【0003】図4は、従来のMIM型半導体キャパシタ
41の製造方法を示す図である。半導体キャパシタ41
の製造方法は、先ず、図4(a)に示すようにシリコン
などの半導体基板42上にPtなどの金属からなる下部
電極43をDCスパッタ法により形成し、Ar等の希ガ
スを用いたイオンミリングによりパターニングする。次
いで、図4(b)に示すように下部電極43上にSiO
などの層間絶縁体膜44をCVD法により形成し、反
応性ガスを用いたプラズマエッチングによりホールを形
成する。次いで、図4(c)に示すように下部電極43
および層間絶縁体膜44上にSrTiOなどの誘電体
膜45をイオンビームスパッタ法により形成した後、P
tなどの上部電極46をDCスパッタ法により形成す
る。最後に、図4(d)に示すように誘電体膜45と上
部電極46を同時に、Ar等の希ガスを用いたイオンミ
リングによりパターニングして半導体キャパシタ41を
得る。
FIG. 4 is a diagram showing a method of manufacturing a conventional MIM type semiconductor capacitor 41. Semiconductor capacitor 41
4A, first, as shown in FIG. 4A, a lower electrode 43 made of a metal such as Pt is formed on a semiconductor substrate 42 such as silicon by a DC sputtering method, and an ion using a rare gas such as Ar is used. Pattern by milling. Then, as shown in FIG. 4B, SiO 2 is formed on the lower electrode 43.
An interlayer insulating film 44 such as 2 is formed by a CVD method, and holes are formed by plasma etching using a reactive gas. Then, as shown in FIG.
After the dielectric film 45 such as SrTiO 3 is formed on the interlayer insulating film 44 by the ion beam sputtering method, P
The upper electrode 46 such as t is formed by the DC sputtering method. Finally, as shown in FIG. 4D, the dielectric film 45 and the upper electrode 46 are simultaneously patterned by ion milling using a rare gas such as Ar to obtain the semiconductor capacitor 41.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、従来の
半導体キャパシタ41には、以下のような問題があっ
た。図4(c)に示すように、下部電極43および層間
絶縁体膜44上に誘電体膜45を形成する際、層間絶縁
体膜44のホール側壁底部において、誘電体膜45の膜
厚が他の部分よりも薄く形成されるという問題がある。
これは、層間絶縁体膜44にプラズマエッチングにより
ホールを形成する際に、マスクとなるレジストの側壁に
加工残渣が生じてレジスト除去後も加工パターン周辺で
凸形状になることや、誘電体膜45をイオンビームスパ
ッタ法などの物理的成膜手法により形成する際に、ステ
ップカバレッジが悪くなることに起因する。
However, the conventional semiconductor capacitor 41 has the following problems. As shown in FIG. 4C, when the dielectric film 45 is formed on the lower electrode 43 and the interlayer insulating film 44, the film thickness of the dielectric film 45 at the bottom of the hole sidewall of the interlayer insulating film 44 is different. There is a problem that it is formed thinner than the part.
This is because when a hole is formed in the interlayer insulating film 44 by plasma etching, a processing residue is generated on the side wall of the resist serving as a mask, and a convex shape is formed around the processing pattern even after the resist is removed, and the dielectric film 45. This is because the step coverage is deteriorated when the film is formed by a physical film forming method such as an ion beam sputtering method.

【0005】図4(d)のB部を拡大した図5に示すよ
うに、誘電体膜平坦部45aの膜厚を100とした場
合、誘電体膜側壁底部45bの膜厚は60〜70まで薄
くなる。従って、この部分にかかる電界が局所的に高く
なり、リーク電流が増大して半導体キャパシタ41の絶
縁耐圧を低下させる原因となる。さらに上述した問題
は、半導体キャパシタ41の容量を増加させるために電
極間隔つまり誘電体膜45の膜厚を薄くするほど、リー
ク電流を増大させることにもなる。
As shown in FIG. 5 in which the portion B of FIG. 4D is enlarged, when the film thickness of the dielectric film flat portion 45a is 100, the film thickness of the dielectric film side wall bottom portion 45b is from 60 to 70. Become thin. Therefore, the electric field applied to this portion is locally increased, which increases the leak current and causes the breakdown voltage of the semiconductor capacitor 41 to decrease. Further, the above-mentioned problem also increases the leak current as the electrode interval, that is, the film thickness of the dielectric film 45 is reduced in order to increase the capacitance of the semiconductor capacitor 41.

【0006】本発明の目的は、下部電極と誘電体膜と上
部電極が積層された半導体キャパシタにおいて、上下電
極間でリーク電流の生じることのない絶縁耐圧の高い半
導体キャパシタおよびその製法を提供することにある。
An object of the present invention is to provide a semiconductor capacitor in which a lower electrode, a dielectric film and an upper electrode are laminated, and which has a high withstand voltage in which a leak current does not occur between the upper and lower electrodes and a manufacturing method thereof. It is in.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体キャパシタは、半導体基板あるいは
半導体基板上に形成された絶縁体膜上に、下部電極と誘
電体膜と上部電極が積層された半導体キャパシタであっ
て、誘電体膜は下部電極上に凹部状に形成され、この誘
電体膜凹部の側壁部に絶縁体膜が形成されていることを
特徴とする。
In order to achieve the above object, a semiconductor capacitor of the present invention has a lower electrode, a dielectric film and an upper electrode on a semiconductor substrate or an insulating film formed on the semiconductor substrate. In the laminated semiconductor capacitor, the dielectric film is formed in a concave shape on the lower electrode, and the insulating film is formed on the side wall of the concave portion of the dielectric film.

【0008】また、本発明の半導体キャパシタの製造方
法は、半導体基板あるいは半導体基板に形成された絶縁
体膜上に下部電極を形成する工程と、下部電極を含む半
導体基板上に第1絶縁体膜を形成し、第1絶縁体膜の下
部電極上の部分にホールを形成する工程と、第1絶縁体
膜のホールに露呈する下部電極と第1絶縁体膜上に誘電
体膜を凹部状に形成する工程と、この誘電体膜凹部の側
壁部に第2絶縁体膜を形成する工程と、誘電体膜と第2
絶縁体膜上に上部電極を形成する工程を有することを特
徴とする。
The method of manufacturing a semiconductor capacitor according to the present invention comprises a step of forming a lower electrode on a semiconductor substrate or an insulating film formed on the semiconductor substrate, and a first insulating film on the semiconductor substrate including the lower electrode. And forming a hole in a portion of the first insulator film above the lower electrode, and forming a concave portion of the dielectric film on the lower electrode and the first insulator film exposed in the hole of the first insulator film. A step of forming, a step of forming a second insulator film on the side wall of the dielectric film recess, a step of forming the dielectric film and the second
The method is characterized by including a step of forming an upper electrode on the insulator film.

【0009】本発明の半導体キャパシタによれば、下部
電極上に形成される誘電体膜凹部の側壁部に第2絶縁体
膜が形成してあり、誘電体膜の薄くなる部分が第2絶縁
体膜でカバーされるので、誘電体膜を通して流れるリー
ク電流成分が抑えられ、絶縁耐圧の高い半導体キャパシ
タを提供することができる。
According to the semiconductor capacitor of the present invention, the second insulator film is formed on the side wall of the recess of the dielectric film formed on the lower electrode, and the thinned portion of the dielectric film is the second insulator. Since it is covered with the film, the leak current component flowing through the dielectric film is suppressed, and a semiconductor capacitor having a high withstand voltage can be provided.

【0010】また、本発明の半導体キャパシタの製造方
法によれば、第2絶縁体膜を異方性エッチングにより選
択的に誘電体膜凹部の側壁部に形成できるので、高歩留
りで安定して製造できる。
Further, according to the method of manufacturing a semiconductor capacitor of the present invention, since the second insulating film can be selectively formed on the side wall of the concave portion of the dielectric film by anisotropic etching, the second insulating film can be stably manufactured with high yield. it can.

【0011】[0011]

【発明の実施の形態】以下、本発明の実施の形態の半導
体キャパシタについて、図1〜図3を参照して説明す
る。
BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor capacitor according to an embodiment of the present invention will be described below with reference to FIGS.

【0012】図1(a)、(b)は本発明の実施の形態
における半導体キャパシタ1の断面図および要部拡大断
面図である。図1(a)に示すように、本発明の半導体
キャパシタ1は、半導体基板2上に下部電極3が形成さ
れ、下部電極3上にホールを有する第1絶縁体膜4が形
成され、下部電極3および第1絶縁体膜4上に誘電体膜
5が凹部状に形成されている。さらに、誘電体膜5凹部
の側壁部に第2絶縁体膜6が選択的に形成され、その誘
電体膜5および第2絶縁体膜6を覆うように上部電極7
が形成されているものである。
1A and 1B are a sectional view and an enlarged sectional view of an essential part of a semiconductor capacitor 1 according to an embodiment of the present invention. As shown in FIG. 1A, in a semiconductor capacitor 1 of the present invention, a lower electrode 3 is formed on a semiconductor substrate 2, a first insulating film 4 having holes is formed on the lower electrode 3, and the lower electrode 3 is formed. A dielectric film 5 is formed in a concave shape on the first insulating film 3 and the first insulating film 4. Further, the second insulating film 6 is selectively formed on the side wall of the concave portion of the dielectric film 5, and the upper electrode 7 is formed so as to cover the dielectric film 5 and the second insulating film 6.
Are formed.

【0013】かかる半導体キャパシタ1の製造方法を図
2を用いて説明する。先ず、図2(a)に示すようにシ
リコンからなる半導体基板2上に、Ptからなる下部電
極3をDCスパッタ法にて形成し、Ar等の希ガスを用
いたイオンミリングにてパターニングする。さらに、パ
ターニングされた下部電極3全体を覆うように、素子間
を絶縁するためのSiOからなる第1絶縁体膜4をC
VD法により形成した後、反応ガスを用いたドライエッ
チングによりホールを形成する。次いで、図2(b)に
示すようにSrTiOからなる誘電体膜5をイオンビ
ームスパッタ法により形成した後、誘電体膜5全面を覆
うようにSiからなる第2絶縁体膜6をCVD法
により形成する。次いで、図2(c)に示すようにRI
E法等の異方性エッチングにより、第2絶縁体膜6の水
平面のみを選択的にエッチングし、誘電体膜5凹部の側
壁部のみに第2絶縁体膜6を残す。次いで、図2(d)
に示すようにPtからなる上部電極7をDCスパッタ法
により、誘電体膜5および第2絶縁体膜6上に形成す
る。最後に、図2(e)に示すように、Ar等の希ガス
を用いたイオンミリングにて誘電体膜5と上部電極7を
同時にパターニングして、半導体キャパシタ1を得る。
A method of manufacturing the semiconductor capacitor 1 will be described with reference to FIG. First, as shown in FIG. 2A, a lower electrode 3 made of Pt is formed on a semiconductor substrate 2 made of silicon by a DC sputtering method, and patterned by ion milling using a rare gas such as Ar. Further, a first insulator film 4 made of SiO 2 for insulating between elements is formed so as to cover the entire patterned lower electrode 3 by C.
After forming by the VD method, holes are formed by dry etching using a reaction gas. Next, as shown in FIG. 2B, a dielectric film 5 made of SrTiO 3 is formed by an ion beam sputtering method, and then a second insulator film 6 made of Si 3 N 4 is formed so as to cover the entire surface of the dielectric film 5. Are formed by the CVD method. Then, as shown in FIG.
By anisotropic etching such as the E method, only the horizontal surface of the second insulating film 6 is selectively etched, and the second insulating film 6 is left only on the side wall of the concave portion of the dielectric film 5. Then, FIG. 2 (d)
The upper electrode 7 made of Pt is formed on the dielectric film 5 and the second insulating film 6 by the DC sputtering method as shown in FIG. Finally, as shown in FIG. 2E, the dielectric film 5 and the upper electrode 7 are simultaneously patterned by ion milling using a rare gas such as Ar to obtain the semiconductor capacitor 1.

【0014】このようにして製造した半導体キャパシタ
1は、図1(a)A部の要部拡大断面図である図1
(b)に示すように、誘電体膜5の薄くなる部分5aが
第2絶縁体膜6で覆われているために、上部電極7と下
部電極3間の距離が長くなることに加えて、第2絶縁体
膜6に誘電率の低い材料を使用し、誘電体膜5aにかか
る電圧配分を小さくすることにより、絶縁耐圧が向上す
ることになる。
The semiconductor capacitor 1 manufactured in this manner is an enlarged cross-sectional view of the main part of the portion A in FIG.
As shown in (b), since the thinned portion 5a of the dielectric film 5 is covered with the second insulator film 6, in addition to the long distance between the upper electrode 7 and the lower electrode 3, By using a material having a low dielectric constant for the second insulator film 6 and reducing the voltage distribution applied to the dielectric film 5a, the withstand voltage is improved.

【0015】図3は本発明と従来の半導体キャパシタの
電流−電圧特性を比較した図である。上部電極と下部電
極に印加する電圧を増加させながら、誘電体膜に流れる
リーク電流を測定したものである。図3から明かなよう
に、印加電圧10Vにおいて、従来の半導体キャパシタ
のリーク電流が10−5A/cm以上であるのに対
し、本発明の半導体キャパシタのリーク電流は10−6
A/cm以下であり、電圧印加時のリーク電流が極め
て少なく良好な絶縁性を示している。
FIG. 3 is a diagram comparing the current-voltage characteristics of the present invention and a conventional semiconductor capacitor. The leak current flowing through the dielectric film was measured while increasing the voltage applied to the upper electrode and the lower electrode. As is clear from FIG. 3, the leak current of the conventional semiconductor capacitor is 10 −5 A / cm 2 or more at an applied voltage of 10 V, whereas the leak current of the semiconductor capacitor of the present invention is 10 −6.
It is A / cm 2 or less, and the leak current when a voltage is applied is extremely small, and good insulation is exhibited.

【0016】なお、本実施例では誘電体膜としてSrT
iOを使用したが、これに限定されるものではなく、
例えばSiO、Si等でも良いし、また(B
a、Sr)TiO、(Pb、Zr)TiO等のペロ
ブスカイト型酸化物の高誘電体膜でも良い。さらには、
これらを混合または積層したものでも良い。
In this embodiment, SrT is used as the dielectric film.
Although iO 3 was used, it is not limited to this.
For example, SiO 2 , Si 3 N 4 or the like may be used, or (B
Alternatively, a high dielectric film of a perovskite type oxide such as a, Sr) TiO 3 or (Pb, Zr) TiO 3 may be used. Moreover,
A mixture or a laminate of these may be used.

【0017】また、実施例ではシリコン基板に直接、下
部電極を形成する例について説明したが、シリコン基板
上にSiOやSiからなる絶縁体膜を形成した
後、下部電極を形成しても良い。このようにすれば、導
電性を有するシリコン基板と下部電極の絶縁を図ること
ができる。下地電極を接地したい場合には、本実施例の
ように直接シリコン基板に下部電極を形成すれば良い。
また、シリコン基板の代わりにGaAs、InP、Ga
Pからなる化合物基板を使用することも可能である。
Further, although the example in which the lower electrode is formed directly on the silicon substrate has been described in the embodiment, the lower electrode is formed after forming an insulating film made of SiO 2 or Si 3 N 4 on the silicon substrate. May be. By doing so, it is possible to insulate the conductive silicon substrate from the lower electrode. When the ground electrode is desired to be grounded, the lower electrode may be directly formed on the silicon substrate as in this embodiment.
Also, instead of the silicon substrate, GaAs, InP, Ga
It is also possible to use a compound substrate made of P.

【0018】また、電極材料としてPtについて説明し
たが、Al、Ti、Au、W、Mo、Ni、Cr、Pd
をはじめ、通常導電物として半導体素子に使用されてい
る物質であれば特に限定されないが、誘電体膜としてS
rTiO、BaSrTiO 等のペロブスカイト型酸
化物を用いる場合は、導電体膜と誘電体膜との界面に反
応生成物を形成しないような安定したPt、Au、Pd
等の貴金属が好ましい。
Further, Pt will be explained as an electrode material.
But Al, Ti, Au, W, Mo, Ni, Cr, Pd
, Which is usually used in semiconductor devices as a conductive material.
There is no particular limitation as long as it is a substance
rTiOThree, BaSrTiO ThreePerovskite type acid
If a compound is used, it must be removed from the interface between the conductor film and the dielectric film.
Stable Pt, Au, Pd that does not form reaction products
Noble metals such as

【0019】[0019]

【発明の効果】以上説明したように、本発明の半導体キ
ャパシタおよびその製造方法によれば、誘電体凹部の側
壁部に第2絶縁体膜を形成したことにより、誘電体膜の
薄くなる部分に電界が集中することがなく、リーク電流
の増加を抑制することができ、絶縁耐圧の高い半導体キ
ャパシタを高歩留りで安定して製造できる。
As described above, according to the semiconductor capacitor and the method of manufacturing the same of the present invention, since the second insulating film is formed on the side wall of the dielectric recess, it is possible to reduce the thickness of the dielectric film. An electric field is not concentrated, an increase in leak current can be suppressed, and a semiconductor capacitor having a high withstand voltage can be stably manufactured with a high yield.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の半導体キャパシタを示す断面図およ
び要部拡大断面図
FIG. 1 is a sectional view showing a semiconductor capacitor of the present invention and an enlarged sectional view of essential parts.

【図2】 本発明の半導体キャパシタの製造方法を示す
断面図
FIG. 2 is a sectional view showing a method for manufacturing a semiconductor capacitor of the present invention.

【図3】 本発明の半導体キャパシタと従来の半導体キ
ャパシタの電流−電圧特性を示す図
FIG. 3 is a diagram showing current-voltage characteristics of a semiconductor capacitor of the present invention and a conventional semiconductor capacitor.

【図4】 従来の半導体キャパシタの製造方法を示す断
面図
FIG. 4 is a sectional view showing a conventional method for manufacturing a semiconductor capacitor.

【図5】 従来の半導体キャパシタの要部拡大断面図FIG. 5 is an enlarged sectional view of a main part of a conventional semiconductor capacitor.

【符号の説明】[Explanation of symbols]

1 半導体キャパシタ 2 半導体基板 3 下部電極 4 第1絶縁体膜 5 誘電体膜 5a 誘電体膜側壁底部 6 第2絶縁体膜 7 上部電極 41 半導体キャパシタ 42 半導体基板 43 下部電極 44 層間絶縁体膜 45 誘電体膜 45a 誘電体膜平坦部 45b 誘電体膜側壁底部 46 上部電極 1 Semiconductor capacitor 2 Semiconductor substrate 3 Lower electrode 4 First insulator film 5 Dielectric film 5a Bottom of sidewall of dielectric film 6 Second insulator film 7 Upper electrode 41 Semiconductor Capacitor 42 Semiconductor substrate 43 Lower electrode 44 Interlayer insulator film 45 Dielectric film 45a Dielectric film flat portion 45b Bottom of sidewall of dielectric film 46 Upper electrode

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】半導体基板あるいは半導体基板に形成され
た絶縁体膜上に、下部電極と誘電体膜と上部電極が積層
された半導体キャパシタであって、前記誘電体膜は前記
下部電極上に凹部状に形成され、前記誘電体膜凹部の側
壁部に絶縁体膜が形成されていることを特徴とする半導
体キャパシタ。
1. A semiconductor capacitor in which a lower electrode, a dielectric film and an upper electrode are laminated on a semiconductor substrate or an insulating film formed on the semiconductor substrate, wherein the dielectric film is recessed on the lower electrode. A semiconductor capacitor, which is formed in a rectangular shape and has an insulating film formed on a side wall of the recess of the dielectric film.
【請求項2】半導体基板あるいは半導体基板に形成され
た絶縁体膜上に下部電極を形成する工程と、前記下部電
極を含む前記半導体基板上に第1絶縁体膜を形成し、前
記第1絶縁体膜の前記下部電極上の部分にホールを形成
する工程と、前記第1絶縁体膜の前記ホールに露呈する
前記下部電極と前記第1絶縁体膜上に前記誘電体膜を凹
部状に形成する工程と、この誘電体膜凹部の側壁部に第
2絶縁体膜を形成する工程と、前記誘電体膜と前記第2
絶縁体膜上に上部電極を形成する工程を有することを特
徴とする半導体キャパシタの製造方法。
2. A step of forming a lower electrode on a semiconductor substrate or an insulating film formed on the semiconductor substrate; and a step of forming a first insulating film on the semiconductor substrate including the lower electrode, the first insulating film Forming a hole in a portion of the body film on the lower electrode, and forming the dielectric film in a concave shape on the lower electrode and the first insulator film exposed in the hole of the first insulator film. And a step of forming a second insulating film on the side wall of the concave portion of the dielectric film, the dielectric film and the second insulating film.
A method of manufacturing a semiconductor capacitor, comprising the step of forming an upper electrode on an insulating film.
JP2002012655A 2002-01-22 2002-01-22 Semiconductor capacitor and method of manufacturing the same Pending JP2003218219A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002012655A JP2003218219A (en) 2002-01-22 2002-01-22 Semiconductor capacitor and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002012655A JP2003218219A (en) 2002-01-22 2002-01-22 Semiconductor capacitor and method of manufacturing the same

Publications (1)

Publication Number Publication Date
JP2003218219A true JP2003218219A (en) 2003-07-31

Family

ID=27649808

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002012655A Pending JP2003218219A (en) 2002-01-22 2002-01-22 Semiconductor capacitor and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP2003218219A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007005719A (en) * 2005-06-27 2007-01-11 Renesas Technology Corp Semiconductor device, transmitter-receiver using same and method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007005719A (en) * 2005-06-27 2007-01-11 Renesas Technology Corp Semiconductor device, transmitter-receiver using same and method for manufacturing semiconductor device
US8183616B2 (en) 2005-06-27 2012-05-22 Renesas Electronics Corporation Semiconductor device, RF-IC and manufacturing method of the same

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