JP2003216094A - Method and device for driving plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the driving method and the driving device of a plasma display panel capable of suppressing power consumption. <P>SOLUTION: In the driving method and the driving device of a plasma display panel, the number of times of applying a display pulse to discharge cells per a unit time is calculated based on the average luminance of an input video and the illuminance of the periphery of a PDP (plasma display panel). Display pulses are applied to respective discharge cells according to the calculated number of the applying times. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method and driving apparatus for a matrix display type plasma display panel.

[0002]

2. Description of the Related Art In recent years, a thin type display device has been required along with an increase in screen size of the display device, and various thin type display devices have been put into practical use. An AC discharge type plasma display panel (hereinafter referred to as PDP) has been noted as one of the thin display devices. The PDP has a plurality of column electrodes and a pair of electrodes arranged orthogonally to the column electrodes.
And a plurality of row electrodes forming scan lines. Each of the row electrodes and the column electrodes is covered with a dielectric layer with respect to the discharge space, and a discharge cell that serves as a pixel is formed at each intersection of the pair of row electrodes and column electrodes.

Here, a subfield method (or subframe method) is known as one of the methods for performing halftone display on such a PDP. In the subfield method, the display period of one field is divided into a plurality of subfields, and each discharge cell is driven to emit light in each subfield. Each subfield is assigned a light emitting period corresponding to the weighting of the subfield. For example, when the pixel data for each pixel based on the input video signal is 8 bits, the period of one field is divided into eight subfields, and a simultaneous reset process and a pixel data writing process are performed in each subfield. , The light emission maintaining process is sequentially executed.

In the simultaneous reset process, wall discharge is formed in all the discharge cells by simultaneously discharge-exciting (reset discharge) all the discharge cells of the PDP. In the pixel data writing process, a discharge (selective erase discharge) is selectively generated in each discharge cell according to the logic level of the pixel data bit corresponding to the subfield. At this time, the wall charges are extinguished in the discharge cells in which the selective erasing discharge has occurred, and the discharge cells are set to the non-light emitting cell state.
On the other hand, since the wall charges remain in the discharge cells in which the selective erasing discharge has not occurred, the discharge cells are set in the light emitting cell state. In the light emission maintenance process,
Only the discharge cells set in the light emitting cell state are repeatedly discharged (sustained discharge) over a period corresponding to the weighting of each subfield. At this time, the brightness corresponding to the total number of sustain discharges generated in the light emission sustaining process of each of the eight subfields is visually recognized. That is, 1: 2: 4: 8: 16: 32: 6 in each of the eight subfields.
If the number of sustain discharges is assigned at a ratio of 4: 128,
256 (= 2 ⁸ ) depending on how to combine the subfields in which sustain discharge occurs within one field display period
It is possible to express the intermediate brightness corresponding to the gradation.

Therefore, when a video signal representing a high-brightness image is supplied, the number of sustain discharges generated per unit time to realize the high-brightness image display is increased, and accordingly power consumption is increased. There was a problem that

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide a driving method and a driving device for a plasma display panel which can suppress power consumption.

[0007]

In a method of driving a plasma display panel according to the present invention, a display pulse is repeatedly applied to each of the discharge cells of a plasma display panel having a plurality of discharge cells for display pixels to cause discharge. A method of driving a plasma display panel that performs display corresponding to an input video signal according to, an average brightness calculation step of calculating an average brightness of an image represented by the input video signal, and an illuminance around the plasma display panel. Illuminance detection step to detect and drive step of calculating the application frequency of the display pulse to be applied by a conversion function having the average luminance and the illuminance as a parameter and applying the display pulse to each of the discharge cells according to the application frequency. And.

Also, the plasma display panel driving apparatus according to the present invention applies a display pulse repeatedly to each of the discharge cells of the plasma display panel having a plurality of discharge cells for display pixels to discharge the input video signal. An apparatus for driving a plasma display panel that performs a display corresponding to, an average brightness calculating unit that calculates an average brightness of an image represented by the input image signal, and an illuminance detection unit that detects an illuminance around the plasma display panel. And a driving means for calculating an application frequency of the display pulse to be applied by a conversion function having the average luminance and the illuminance as parameters, and applying the display pulse to each of the discharge cells according to the application frequency.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of a plasma display device equipped with a plasma display panel (hereinafter referred to as PDP). As shown in Figure 1,
The plasma display device includes a PDP 10 as a plasma display panel and a drive unit including various functional modules.

The PDP 10 includes m column electrodes D _{1 to} D _m as address electrodes, and n row electrodes X _{1 to} X _n and row electrodes Y ₁ arranged to intersect with each of these column electrodes. ~ Y _n
Is equipped with. These row electrodes X _{1 to} X _n and row electrodes Y ₁ to
Y _n is a pair of row electrodes X _i (1 ≦ i ≦ n) and Y _i (1 ≦ i ≦ n), respectively.
In n), the first to nth display lines in the PDP 10 are carried. A discharge space filled with a discharge gas is formed between the column electrode D and the row electrodes X and Y. Then, a discharge cell corresponding to a pixel is formed at each intersection of each row electrode pair and column electrode including this discharge space. That is, the column electrode D is on one display line.
, There are m discharge cells.

The drive unit includes an A / D converter 1, a drive control circuit 2, a memory 4, an address driver 6, a first sustain driver 7, a second sustain driver 8, a data conversion circuit 30, an average brightness calculation circuit 50, and an external device. Optical sensor 51 and AB
It is composed of an L characteristic memory 52. The A / D converter 1 is
The input video signal is sampled, converted into, for example, 8-bit pixel data PD corresponding to each pixel, and this is supplied to each of the data conversion circuit 30 and the average luminance calculation circuit 50. The data conversion circuit 30 performs 8-bit pixel driving in which each discharge cell of the PDP 10 should be set to a light emitting cell state or a non-light emitting cell state for each subfield after performing multi-gradation processing on the pixel data PD. It is converted into data GD and is supplied to the memory 4.

FIG. 2 is a diagram showing an example of the internal configuration of the data conversion circuit 30. In FIG. 2, the multi-gradation processing circuit 31 performs error diffusion processing and dither processing on the 8-bit pixel data PD. For example, in the error diffusion process, first, the upper 6 bits of the pixel data PD are regarded as display data, and the remaining lower 2 bits are regarded as error data. Then, the pixel data P corresponding to each of the peripheral pixels
The weighted addition of each error data of D is reflected in the display data. By such an operation, the luminance of the lower 2 bits of the original pixel is pseudo-expressed by the peripheral pixels, and therefore, the display data of 6 bits less than 8 bits is equivalent to the pixel data of 8 bits. It becomes possible to express brightness gradation. Then, dither processing is applied to the 6-bit error diffusion processed pixel data obtained by this error diffusion processing. In the dither processing, a plurality of pixels that are adjacent to each other are set as one pixel unit, and the error diffusion processing pixel data corresponding to each pixel in the one pixel unit are respectively assigned dither coefficients having different coefficient values and added. To obtain dither addition pixel data. According to the addition of the dither coefficients, when viewed in the unit of one pixel, it is possible to express the luminance corresponding to 8 bits by only the upper 4 bits of the dither addition pixel data. Therefore, the multi-gradation processing circuit 31 sets the upper 4 bits of the dither addition pixel data to the multi-gradation pixel data PD.
_It is supplied to the data conversion circuit 32 as _S.

The data conversion circuit 32 converts the 4-bit multi-gradation pixel data PD _S into 8-bit pixel drive data GD according to the data conversion table as shown in FIG. 3, and supplies this to the memory 4. The pixel drive data G
The 1st to 8th bits of D correspond to subfields SF1 to SF8, which will be described later, respectively. The memory 4 sequentially writes the pixel drive data GD according to the write signal supplied from the drive control circuit 2. Then, the pixel drive data G corresponding to one screen, that is, the pixels in the first row and the first column
When the writing of (n × m) pieces of pixel drive data GD from D ₁₁ to the pixel drive data GD _nm corresponding to the pixels of the nth row and the mth column is completed, the memory 4 performs the following read operation. I do.

First, in the memory 4, the written pixel drive data GD _{11 to} GD _{nm for} one screen is written in each bit digit.
It is regarded as pixel drive data bits DB1 to DB8 divided for each (first bit to eighth bit). That is, DB1 _{11 to} DB1 _nm : GD _{11 to} GD _nm each first bit DB2 _{11 to} DB2 _nm : GD _{11 to} GD _nm each 2nd bit DB3 _{11 to} DB3 _nm : GD _{11 to} GD _nm each 3rd bit DB4 _{11 to} DB4 _nm : GD _{11 to} GD _nm 4th bit DB5 _{11 to} DB5 _nm : GD _{11 to} GD _nm 5th bit DB6 _{11 to} DB6 _nm : GD _{11 to} GD _nm 6th bit DB7 ₁₁ ~DB7 _nm: GD _{11 ~GD nm} each of the 7-bit DB8 ₁₁ ~DB8 _nm: a first 8-bit GD ₁₁ to GD _nm, respectively.

Then, the memory 4 reads the pixel drive data bits DB1 _{11 to} DB1 _nm one display line at a time in the pixel data writing process Wc of the subfield SF1 described later and supplies them to the address driver 6. Next, the memory 4 reads out the pixel drive data bits DB2 _{11 to} DB2 _nm one display line at a time in a pixel data writing process Wc of a subfield SF2 described later and supplies them to the address driver 6. Thereafter, similarly, the memory 4 reads the pixel drive data bits DB3 to DB8 one display line at a time in each pixel data writing process Wc of subfields SF3 to SF8, which will be described later, and supplies them to the address driver 6. Of.

The average brightness calculation circuit 50 is provided for each field.
The above pixel data PD for one field for each (each frame)
Based on the above, the average brightness level of the image by the input video signal is calculated, and the average brightness signal APL indicating the calculated average brightness level is supplied to the drive control circuit 2. External light sensor 51
Is an optical sensor provided around the PDP 10, detects the brightness around the PDP 10, and supplies an illuminance signal LL having a signal level corresponding to the brightness to the drive control circuit 2.

The ABL (automatic brightness control) characteristic memory 52 converts the average brightness signal APL into the number of sustain pulses (described later) to be applied to the discharge cells in each field, that is, the application frequency, as shown in FIG. A data conversion table corresponding to each of the three ABL characteristics A to C as shown is stored. At this time, according to the data conversion table based on the ABL characteristic A, when the average luminance signal APL is smaller than the first lower limit value V1, for example, the number of applied sustain pulses of “1530” is obtained, while the above first number When it is larger than the lower limit value V1, the larger the average luminance signal APL, the smaller the number of applications. According to the ABL characteristic A, the power consumed by the sustain discharge falls within the predetermined first power consumption regardless of the average brightness of the input image. Further, according to the data conversion table based on the ABL characteristic B, when the average brightness signal APL is smaller than the second lower limit value V2 (V1> V2), the number of sustain pulse application such as “1530” is obtained. If the average luminance signal APL is larger than the second lower limit value V2, the smaller the number of application is obtained. According to the ABL characteristic B, the power consumption consumed by the sustain discharge falls within the predetermined second power consumption regardless of the average brightness of the input image. Further, according to the data conversion table based on the ABL characteristic C, the average luminance signal APL
Is smaller than the third lower limit value V3 (V2> V3), "
While the sustain pulse application number of 1530 "is obtained, when the average brightness signal APL is larger than the third lower limit value V3, the larger the average brightness signal APL is, the smaller the application number is. According to C, the power consumption consumed by the sustain discharge falls within the predetermined third power consumption regardless of the average luminance of the input image.

As described above, the ABL characteristics A to C should be applied to the discharge cells in each field in order to limit the power consumed by the sustain discharge within the predetermined power consumption set individually. The number of sustain pulses applied, that is, the frequency of application, is changed to a smaller number as the average brightness of the input image is higher. The lower limit value of the average luminance signal APL on which the power limiting action as described above in the ABL characteristics A to C works is shown in FIG.
As shown in, the first lower limit value V1 in the ABL characteristic A is the highest, and then the second lower limit value V2 in the ABL characteristic B,
It is the third lower limit value V3 in the ABL characteristic C. Therefore, the second power consumption due to the ABL characteristic B is smaller than the first power consumption due to the ABL characteristic A, and the third power consumption due to the ABL characteristic C is smaller than the second power consumption. Become.

The ABL characteristic memory 52 includes ABL characteristics A ...
From C, the data conversion table of the ABL characteristic indicated by the ABL characteristic read signal supplied from the drive control circuit 2 is selectively read and supplied to the drive control circuit 2. The drive control circuit 2 sends various timing signals for driving and controlling the PDP 10 according to the light emission drive format shown in FIG. 6 to the address driver 6 and the first sustain driver 7.
And the second sustain driver 8 respectively.

In the emission drive format shown in FIG. 6, the display period of each field (hereinafter, also including a frame) is divided into eight subfields SF1 to SF8.
Split into. Then, within each subfield, PDP1
The pixel data writing process Wc for setting each of the discharge cells of 0 to either the light emitting cell state or the non-light emitting cell state and the discharge cells in the light emitting cell state to the frequency ratio described in FIG. The light emission sustaining step Ic for repeatedly emitting light for the number indicated by Further, the simultaneous reset process Rc for initializing the wall charge amount in all the discharge cells of the PDP 10 is executed only in the first subfield SF1, and in the last subfield SF14, the wall charges in all the discharge cells are simultaneously deleted. The erasing process E for erasing is executed.

FIG. 7 shows each of the address driver 6, the first sustain driver 7 and the second sustain driver 8 in each of the simultaneous reset process Rc, the pixel data writing process Wc, the light emission sustaining process Ic and the erasing process E. FIG. 3 is a diagram showing various drive pulses applied to the PDP 10 and their application timings. First, in the simultaneous reset process Rc executed only in the subfield SF1, each of the first sustain driver 7 and the second sustain driver 8 is
The reset pulse RP _x and RP _Y having such waveform shown in FIG. 7 simultaneously applies the PDP10 in the row electrode X ₁ to X _n and Y ₁ to Y _n. By the simultaneous application of these reset pulses RP _x and RP _Y , all discharge cells in the PDP 10 are reset-discharged, and immediately after the reset discharge, a predetermined amount of wall charge is uniformly formed in each discharge cell. By this reset discharge, all the discharge cells are initialized to the light emitting cell state.

Next, in the pixel data writing process Wc of each subfield, the address driver 6 generates a pixel data pulse having a voltage corresponding to the logic level of the pixel drive data bit DB supplied from the memory 4. . For example, the address driver 6 uses the pixel drive data bit D
When the logic level of B is "1", a high voltage pixel data pulse is generated, and when it is "0", a low voltage (0 volt) pixel data pulse is generated. At this time, the address driver 6 applies the pixel data pulse generated as described above to the column electrodes D _{1 to} D _m for each row (m pieces). For example, the pixel data writing process Wc of the subfield SF1
Then, from the memory 4 to the pixel drive data bits DB1 _{11 to} D
Since B1 _nm is supplied, the address driver 6 first corresponds to the first row, that is, DB1 ₁₁
~ Extract DB1 _1m . Then, the address driver 6
Of the m number of DB1 ₁₁ to DB1 _1m respectively corresponding to the logic level of the m number of pixel data pulses DP1 _{11 to} D1
P1 _1m , and these are simultaneously applied to the column electrodes D _{1 to} D _m as shown in FIG. Next, the address driver 6 selects the second from the pixel drive data bit group DB1 _{11 to} DB1 _nm .
DB1 ₂₁ to DB1 _2m corresponding to the line are extracted. Then, the address driver 6 uses the m DB1 _{21 to} D DBs.
Each of B1 _2m is converted into _m pixel data pulses DP1 _{21 to} DP1 _2m corresponding to the logic level, and these are converted into FIG.
Simultaneously, as shown in (4), the voltage is applied to the column electrodes D _{1 to} D _m . Thereafter, in the same manner, the address driver 6 determines that the subfield SF1
In the pixel data writing process Wc, is going to the column electrodes D ₁ to D _m pixel data pulses DP1 corresponding to pixel driving data bits DB1 supplied from the memory 4 for each row.

Further, in the pixel data writing process Wc, the second
Sustain driver 8, at an applied the same timing of the pixel data pulse DP of each row as mentioned above, it generates a scanning pulse SP of negative polarity as shown in FIG. 7, which row electrodes Y ₁ ~ The voltage is sequentially applied to Y _n . At this time, discharge (selective erase discharge) occurs only in the discharge cell at the intersection of the row electrode to which the scan pulse SP is applied and the column electrode to which the high-voltage pixel data pulse is applied, and the discharge cell remains in the discharge cell. The wall charges that have been removed are selectively erased. By this selective erase discharge, the discharge cells initialized in the light emitting cell state in the simultaneous reset process Rc are set in the non-light emitting cell state. On the other hand, the discharge cells in which the selective erasing discharge has not occurred maintain the state just before that. That is, the discharge cells in the light emitting cell state are directly set to the light emitting cell state, and the discharge cells in the non-light emitting cell state are directly set to the non-light emitting cell state.

Next, the light emission sustaining process I of each subfield
In c, the first sustain driver 7 and the second sustain driver 8 alternately maintain the sustaining pulse IP of the positive polarity with respect to the row electrodes X _{1 to} X _n and Y _{1 to} Y _n as shown in FIG.
_{Apply X} and IP _Y. Here, subfield SF1
The number of times the sustain pulse IP is repeatedly applied in each of the sustaining steps Ic to SF8 is equal to the average luminance signal A.
PL, the illuminance signal LL, and the data conversion table read from the ABL characteristic memory 52.

For example, when the illuminance signal LL is lower than the illuminance L1 as shown in FIG. 5, the drive control circuit 2 outputs A
An ABL characteristic read signal for reading the data conversion table corresponding to the BL characteristic C is supplied to the ABL characteristic memory 52. As a result, the ABL characteristic memory 52 supplies the data conversion table corresponding to the ABL characteristic C as shown in FIG. 4 to the drive control circuit 2. At this time, the drive control circuit 2 obtains the number of applied sustain pulses corresponding to the average luminance signal APL based on the data conversion table corresponding to the ABL characteristic C. Then, the drive control circuit 2 sets the number of sustain pulses to be applied within this one-field display period at a frequency ratio as shown in FIG.
c and assign the sustain pulse timing signal to the first
It is supplied to each of the sustain driver 7 and the second sustain driver 8. As a result, when the average luminance signal APL is "40" as shown in FIG. 4, for example, according to the ABL characteristic C, "510" is obtained as the total number of sustain pulses to be applied within one field display period. Therefore, the pulse number "510" of the sustain pulse is set to the light emission sustaining process Ic of each of the subfields SF1 to SF8 at the frequency ratio as shown in FIG.
8 to SF1,2 SF2: 12 SF3: 32 SF4: 48 SF5: 70 SF6: 92 SF7: 114 SF8: 140 as shown in FIG. Therefore, each of the first sustain driver 7 and the second sustain driver 8 has the subfields SF1 to S1.
In each light emission sustaining process Ic of F8, the sustaining pulses IP _X and IP _Y are repeatedly applied to each discharge cell as many times as described above.

Further, when the illuminance signal LL is higher than the illuminance L1 and lower than the illuminance L2 as shown in FIG. 5, the drive control circuit 2 should read the ABL characteristic reading to read the data conversion table corresponding to the ABL characteristic B. The signal is supplied to the ABL characteristic memory 52. As a result, the ABL characteristic memory 52
Supplies the data conversion table corresponding to the ABL characteristic B as shown in FIG. 4 to the drive control circuit 2. At this time, the drive control circuit 2 obtains the number of sustain pulses applied (which should be applied within one field display period) corresponding to the average luminance signal APL based on the data conversion table corresponding to the ABL characteristic B. Then, the drive control circuit 2 sets the number of sustain pulses to be applied within this one-field display period to the number of sustain pulse application as shown in FIG.
The timing signal of each sustain pulse is supplied to the first sustain driver 7 and the second sustain driver 8 respectively. With this operation, for example, when the average luminance signal APL is "40" as shown in FIG. 4, according to the ABL characteristic B, "765" is obtained as the total number of sustain pulses to be applied within one field display period. . Therefore, if the pulse number "765" of this sustain pulse is assigned to the light emission sustaining process Ic of each of the subfields SF1 to SF8 at the frequency ratio shown in FIG. 6, as shown in FIG. 8, SF1: 3 SF2: 18 SF3 : 48 SF4: 72 SF5: 105 SF6: 138 SF7: 171 SF8: 210. Therefore, each of the first sustain driver 7 and the second sustain driver 8 has the subfields SF1 to S1.
In each light emission sustaining process Ic of F8, the sustaining pulses IP _X and IP _Y are repeatedly applied to each discharge cell as many times as described above.

When the illuminance signal LL is higher than the illuminance L2 shown in FIG. 5, the drive control circuit 2 causes the ABL
A that should read the data conversion table corresponding to characteristic A
The BL characteristic read signal is supplied to the ABL characteristic memory 52.
As a result, the ABL characteristic memory 52 supplies the data conversion table corresponding to the ABL characteristic A as shown in FIG. 4 to the drive control circuit 2. At this time, the drive control circuit 2 is
Based on the data conversion table corresponding to the BL characteristic A, the number of applied sustain pulses (should be applied within one field display period) corresponding to the average luminance signal APL is obtained. And
The drive control circuit 2 allocates the number of sustain pulses to be applied within this one-field display period to the light emission sustaining process Ic of each subfield at the frequency ratio shown in FIG. 6, and outputs the timing signal of each sustain pulse. It is supplied to each of the first sustain driver 7 and the second sustain driver 8. By this operation, when the average luminance signal APL is "40" as shown in FIG. 4, for example, according to the ABL characteristic A, "1020" is obtained as the total number of sustain pulses to be applied within one field display period. Therefore, when the sustain pulse application number "1020" is assigned to the light emission sustaining process Ic of each of the subfields SF1 to SF8 at the frequency ratio shown in FIG. 6, as shown in FIG. 8, SF1: 4 SF2: 24 SF3 : 64 SF4: 96 SF5: 140 SF6: 184 SF7: 228 SF8: 280. Therefore, each of the first sustain driver 7 and the second sustain driver 8 has the subfields SF1 to S1.
In each light emission sustaining process Ic of F8, the sustaining pulses IP _X and IP _Y are repeatedly applied to each discharge cell as many times as described above.

Here, the sustain pulses IP _X and IP _Y are applied only to the discharge cells in which the wall charges remain, that is, the discharge cells set to the light emitting cell state in the pixel data writing process Wc. Sustain discharge every time
For the number of discharges assigned to each subfield,
The light emission state due to the sustain discharge is maintained. As described above, whether or not each discharge cell is set to the light emitting cell state depends on the pixel drive data GD. At this time, the patterns that can be taken as the pixel drive data GD are 9 patterns as shown in FIG. Then, except for the pixel drive data GD corresponding to the multi-gradation pixel data PD _S of “1000” representing the highest brightness, only one bit of the first to eighth bits has a logical level “1”. And all the other bits are at the logic level "0". Therefore, the selective erase discharge is generated only in the pixel data writing process Wc of the subfield corresponding to the bit digit of the logic level "1", and the discharge cell is set to the non-light emitting cell state. on the other hand,
In the pixel data writing process Wc of the subfield corresponding to each bit digit of the logic level "0", selective erasing discharge is not generated, so the discharge cell holds the state up to immediately before. At this time, according to the driving as shown in FIG. 6, the process in which the wall charge is formed in the discharge cell and the discharge cell can be transited from the non-light emitting cell state to the light emitting cell state is the first subfield SF1. It is only the simultaneous reset process Rc. Therefore, according to the driving using the pixel driving data GD of FIG. 3, the discharge cells are selectively erased in the pixel data writing process Wc of the subfields marked with black dots in FIG. 3 from the beginning of each field. The light emitting cell is maintained until the light emission occurs. Then, once the selective erasing discharge is generated, thereafter, the discharge cell holds the non-light emitting cell state until the end of one field. Therefore, each discharge cell is maintained in the light emitting cell state until the selective erase discharge is first generated in each field, and is continuously performed in the light emission sustaining process Ic of each subfield (indicated by a white circle) existing therebetween. Then, a sustain discharge is generated.

Therefore, when the pixel drive data GD as shown in FIG. 3 is used to drive in accordance with the light emission drive format as shown in FIG. 6, the sustain discharge generated in each light emission sustaining step Ic through SF1 to SF8. The intermediate luminance display for 9 gradations corresponding to the total number of is performed. At this time, PDP
When the illuminance around 10 is relatively high, AB shown in FIG.
Based on the L characteristic A, within one field display period (SF1-
At SF8), the number of sustain pulses to be applied to each discharge cell is determined. Therefore, for example, as shown in FIG. 4, when the average luminance level of the input image is "40", the number of sustain pulses to be applied to each discharge cell in the one-field display period is "1020". Therefore, 9 shown in FIG.
The brightness level of each of the intermediate brightnesses of 9 gradations obtained by the different light emission drive patterns is {0, 4, 28, 92, 188, 328, 512,
740, 1020}.

Similarly to the above, when the illuminance around the PDP 10 is relatively high and the average luminance level of the input image is "50" as shown in FIG. The number of sustain pulses to be applied to the discharge cells is “765”. Therefore, the brightness levels of the respective intermediate brightnesses of 9 gradations obtained by the 9 kinds of light emission drive patterns shown in FIG. 3 are {0, 3, 21, 69, 141, 246, 384, 555, 76.
5}.

That is, according to the ABL characteristic A, the higher the average brightness level of the input image, the smaller the number of sustain pulses applied to each discharge cell in one field display period. That is, even if the average brightness level of the input image increases from "40" to "50", the power limiting action works so that the power consumption falls within the first power consumption.

On the other hand, when the illuminance around the PDP 10 is relatively low, the number of sustain pulses to be applied to each discharge cell within one field display period is determined based on the ABL characteristic C shown in FIG. Therefore, for example, as shown in FIG. 4, when the average luminance level of the input image is "40", the number of sustain pulses to be applied to each discharge cell in one field display period is "510". Therefore, the brightness level of each of the intermediate brightnesses for 9 gradations obtained by the 9 kinds of light emission drive patterns shown in FIG. 3 is {0, 2, 14, 46, 94, 164, 2
56, 370, 510}.

Therefore, as described above, the brightness of the entire screen is lower than that when the illuminance around the PDP 10 is high. That is, an appropriate screen brightness corresponding to the brightness of the place where the plasma display device is installed can be provided. Further, according to the ABL characteristic C, even if the average brightness level of the input image becomes high, the power consumption thereof falls within the third power consumption. At this time, A
The third power consumption by the BL characteristic C is smaller than the first power consumption by the ABL characteristic A used when the illuminance around the PDP 10 is high. Therefore, when the illuminance around the PDP 10 is low, the power consumption is reduced as compared with the case where the illuminance is high.

As described above, the ABL characteristics A to C are one conversion function for obtaining the number of sustain pulses to be applied in each field, that is, the application frequency, using the average brightness of the input image and the illuminance around the PDP 10 as parameters. Can be understood as. At this time, the conversion function is a superposition of a first conversion function that converts the average brightness into a smaller application frequency of sustain pulses as the average brightness increases, and a second function that decreases the application frequency as the illuminance decreases. Can be represented by Therefore, according to the brightness limiting operation using the ABL characteristics A to C, the power consumption is set to a predetermined value regardless of the brightness level of the input video while maintaining the appropriate screen brightness that follows the illuminance around the PDP. It is possible to limit the power consumption.

If the frequency of sustain pulse application is reduced to reduce the number of sustain discharge occurrences, the amount of priming particles generated with the discharge is reduced.
It becomes impossible to reliably generate (selective erase discharge, sustain discharge). Therefore, various discharges are reliably generated by increasing the pulse width of each sustain pulse or the pulse width of each of the scan pulse and the pixel data pulse by the amount by which the sustain pulse is applied less frequently.

For example, when the number of sustain pulses to be applied to the discharge cells in each field is "510",
The address driver 6 and the second sustain driver 8 are
In the pixel data writing step Wc, the pixel data pulse and the scan pulse SP having the pulse width T1 as shown in FIG.
To occur. At this time, the first sustain driver 7 and the second sustain driver 8 generate the sustain pulses IP _X and IP _Y having the pulse width P1 and the cycle S1 as shown in FIG. 10A in the light emission sustaining process Ic.

When the number of sustain pulses to be applied to the discharge cells in each field is, for example, "765", the address driver 6 and the second sustain driver 8 are used.
In the pixel data writing step Wc, as shown in FIG. 9B, a pixel data pulse and a scan having a pulse width T2 narrower than the pulse width T1 and a cycle shorter than that of the pulse width T1. Generate a pulse SP. At this time, the first sustain driver 7 and the second sustain driver 8 have a pulse width P2 narrower than the pulse width P1 and smaller than the period S1 as shown in FIG. 10B in the light emission sustaining process Ic. The sustain pulses IP _X and IP _Y having a short cycle S2 are generated.

When the number of sustain pulses to be applied to the discharge cells in each field is, for example, "1020", the address driver 6 and the second sustain driver 8 are used.
In the pixel data writing step Wc, as shown in FIG. 9 (c), has a pulse width T3 narrower than the pulse width T2 and has a shorter period than the pulse width T2. Generate a pulse SP. At this time, the first sustain driver 7 and the second sustain driver 8 have a pulse width P3 narrower than the pulse width P2 and smaller than the cycle S2 as shown in FIG. 10C in the light emission sustaining process Ic. The sustain pulses IP _X and IP _Y having a short cycle S3 are generated.

As described above, the smaller the number of sustain pulses to be applied to the discharge cells in each field is, the wider the pulse widths of the scan pulse, the pixel data pulse, and the sustain pulse are. Of. Thereby, even if the amount of priming particles present in the discharge cell is small because the number of sustain discharges is small, it is possible to surely cause the discharge.

[0040]

As described above, according to the present invention, the unit time is calculated based on the average brightness of the input image and the illuminance around the PDP.
Display pulse to be applied per (1 field display period)
The application frequency of the (sustain pulse) is calculated, and the display pulse is applied to each discharge cell according to the application frequency.

Therefore, according to the present invention, the power consumption is kept within the predetermined power consumption regardless of the brightness level of the input image while maintaining the appropriate screen brightness following the illuminance around the plasma display panel. It becomes possible to limit it.

[Brief description of drawings]

FIG. 1 is a diagram showing a plasma display device for driving a plasma display panel according to a driving method of the present invention.

FIG. 2 is a diagram showing an internal configuration of a data conversion circuit 30 shown in FIG.

FIG. 3 is a diagram showing a data conversion table of a data conversion circuit 32 and a light emission drive pattern.

FIG. 4 is a diagram showing ABL characteristics A to C.

5 is a diagram showing a correspondence relationship between illuminance around the PDP 10 and ABL characteristics A to C. FIG.

6 is a diagram showing an example of a light emission drive format adopted in the plasma display device shown in FIG.

FIG. 7 is a diagram showing an example of various drive pulses applied to the PDP 10 and their application timings.

FIG. 8 shows the number of sustain pulses to be applied within one field display period and the number of application within each subfield when the average luminance level of the input image is “40”,
It is a figure shown for every illuminance around P10.

FIG. 9 is a diagram showing pulse widths of a pixel data pulse and a scan pulse SP, which are changed according to the number of sustain pulses to be applied within one field display period.

FIG. 10 is a diagram showing a pulse width of a sustain pulse, which is changed according to the number of sustain pulses to be applied within one field display period.

[Explanation of symbols]

2 Drive control circuit 6 Address driver 7 First sustain driver 8 Second sustain driver 10 PDP 50 Average brightness calculation circuit 51 Ambient light sensor 52 ABL characteristic memory

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 642 H04N 5/66 101B 3/288 G09G 3/28 K H04N 5/66 101 B F term ( Reference) 5C058 AA11 BA01 BA05 BA07 BA26 BB03 BB11 BB14 5C080 AA05 BB05 DD03 DD26 EE29 HH04 HH05 JJ02 JJ04 JJ05

Claims (12)

[Claims] 1. A drive for a plasma display panel, which performs display corresponding to an input video signal by repeatedly applying a display pulse to each of the discharge cells of a plasma display panel having a plurality of discharge cells that carry display pixels to cause discharge. A method, wherein an average brightness calculation step of calculating an average brightness of an image represented by the input video signal, an illuminance detection step of detecting an illuminance around the plasma display panel, and the average brightness and the illuminance as parameters. And a drive step of applying the display pulse to each of the discharge cells according to the application frequency by calculating the application frequency of the display pulse to be applied by the conversion function. . 2. The conversion function includes a first conversion function that converts the average brightness into the application frequency that decreases as the average brightness increases, and a second function that decreases the application frequency as the illuminance decreases. The method for driving a plasma display panel according to claim 1, wherein the driving method is represented by superimposing 3. The driving method of the plasma display panel according to claim 1, wherein the calculation of the application frequency is performed for each frame period of the input video signal. 4. The driving method of a plasma display panel according to claim 1, wherein the conversion function obtains the application frequency of a fixed value in a range where the average brightness is lower than a predetermined brightness level. 5. The method of driving a plasma display panel according to claim 4, wherein the predetermined brightness level decreases as the illuminance decreases. 6. A driving method of a plasma display panel, which performs a display corresponding to an input video signal by repeatedly applying a display pulse to each of the discharge cells of a plasma display panel having a plurality of discharge cells that carry display pixels to cause discharge. In the method, an average luminance calculation step of calculating an average luminance of an image represented by the input image signal, an illuminance detection step of detecting an illuminance around the plasma display panel, and the average luminance is the average luminance. A first brightness limiting step of converting the display pulse into a lower application frequency as the higher, and the average brightness so that the application frequency obtained with respect to the average brightness is lower than the first brightness limiting step. The second conversion is performed such that the higher the average luminance is, the smaller the application frequency is.
Brightness limiting step, and when the illuminance is relatively high, while applying the display pulse to each of the discharge cells according to the application frequency obtained by the first brightness limiting step, when the illuminance is relatively low A driving step of applying the display pulse to each of the discharge cells according to the application frequency obtained by the second brightness limiting step, the driving method of the plasma display panel. 7. A driving method of a plasma display panel, which performs a display corresponding to an input video signal by repeatedly applying a display pulse to each of the discharge cells of a plasma display panel having a plurality of discharge cells that carry display pixels to cause discharge. An apparatus, comprising: an average brightness calculating means for calculating an average brightness of an image represented by the input video signal; an illuminance detecting means for detecting an illuminance around the plasma display panel; and the average brightness and the illuminance as parameters. Driving means for calculating the application frequency of the display pulse to be applied by the conversion function and applying the display pulse to each of the discharge cells according to the application frequency. . 8. The conversion function includes a first function for converting the average brightness to the application frequency that becomes smaller as the average brightness becomes higher, and a second function that makes the application frequency smaller as the illuminance becomes lower.
The driving device for the plasma display panel according to claim 7, wherein the driving device is represented by superposition with a function. 9. The driving device of the plasma display panel according to claim 7, wherein the calculation of the application frequency is performed for each frame period of the input video signal. 10. The driving device of the plasma display panel according to claim 7, wherein the conversion function obtains the application frequency of a fixed value in a range in which the average brightness is lower than a predetermined brightness level. 11. The driving device of the plasma display panel according to claim 10, wherein the predetermined brightness level becomes smaller as the illuminance becomes smaller. 12. A plasma display panel drive for performing display corresponding to an input video signal by repeatedly applying a display pulse to each of the discharge cells of a plasma display panel having a plurality of discharge cells that carry display pixels to cause discharge. In the device, an average brightness calculating unit that calculates an average brightness of an image represented by the input video signal, an illuminance detecting unit that detects an illuminance around the plasma display panel, and the average brightness is the average brightness. A first brightness limiting means for converting the display pulse into a smaller frequency of application of the display pulse; and the average brightness so that the application frequency obtained with respect to the average brightness is smaller than that of the first brightness limiting means. A second brightness limiting means for converting the display pulse to a smaller application frequency as the average brightness is higher; and the illuminance is relatively high. In the case where the illuminance is relatively low, the display pulse is applied to each of the discharge cells according to the application frequency obtained by the first brightness limiting means, while the display pulse is obtained by the second brightness limiting means when the illuminance is relatively low. A driving unit that applies the display pulse to each of the discharge cells in accordance with the application frequency.