JP2003209401A - High frequency circuit - Google Patents

High frequency circuit

Info

Publication number
JP2003209401A
JP2003209401A JP2002004236A JP2002004236A JP2003209401A JP 2003209401 A JP2003209401 A JP 2003209401A JP 2002004236 A JP2002004236 A JP 2002004236A JP 2002004236 A JP2002004236 A JP 2002004236A JP 2003209401 A JP2003209401 A JP 2003209401A
Authority
JP
Japan
Prior art keywords
carrier
high frequency
carriers
frequency circuit
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002004236A
Other languages
Japanese (ja)
Inventor
Katsumi Tanaka
勝己 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Kokusai Electric Inc
Original Assignee
Hitachi Kokusai Electric Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Kokusai Electric Inc filed Critical Hitachi Kokusai Electric Inc
Priority to JP2002004236A priority Critical patent/JP2003209401A/en
Publication of JP2003209401A publication Critical patent/JP2003209401A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high frequency circuit having a packaging structure in which satisfactory high frequency characteristics can be obtained by closely and easily connecting carriers. <P>SOLUTION: In the high frequency circuit having a first carrier 3 packaged with an IC (LNA1 and LNA2) to be used for the high frequency circuit, a second carrier 6 packaged with an IC (PA 8) to be used for the high frequency circuit, a wire 9 for bonding the IC packaged on the first carrier 3 and the IC packaged on the second carrier 6, and a conductive substance 10 for connecting the first and second carriers, the conductive substance 10 is provided between the first and second carriers while making the distances and the lengths of grounds to the wire 9 approximately equal. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、高周波回路に関
し、特に、マイクロ波帯、ミリ波帯等の高周波領域で用
いられる高周波回路の実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency circuit, and more particularly to a mounting structure of a high frequency circuit used in a high frequency region such as a microwave band and a millimeter wave band.

【０００２】[0002]

【従来の技術】近年、周波数資源の枯渇により、これま
で利用されていないマイクロ波・ミリ波帯のシステム応
用が期待されている。マイクロ波・ミリ波帯において
は、その特性から大容量の情報を高速に伝送するのに適
した高速無線ＬＡＮシステム、画像モニタシステム、高
速無線ネットワーク等の実用化が急激に進められてい
る。2. Description of the Related Art In recent years, due to depletion of frequency resources, application of microwave / millimeter wave band systems, which have not been used so far, is expected. In the microwave / millimeter wave band, practical application of a high-speed wireless LAN system, an image monitor system, a high-speed wireless network, etc. suitable for high-speed transmission of a large amount of information due to their characteristics has been rapidly advanced.

【０００３】このようなシステムを実現するために、Ｍ
ＩＣ（Microwave IC）等の高周波回路が使用されてい
る。ＭＩＣには、アルミナなどの誘電体基板上に伝送路
を形成し、その上にチップ部品を搭載したハイブリッド
ＭＩＣ（ＨＭＩＣ）、および半導体基板上に能動素子と
受動素子を一括生成したモノリシックＭＩＣ（ＭＭＩ
Ｃ：Monolithic Microwave IC）がある。In order to realize such a system, M
A high frequency circuit such as an IC (Microwave IC) is used. The MIC includes a hybrid MIC (HMIC) in which a transmission path is formed on a dielectric substrate such as alumina, and chip components are mounted thereon, and a monolithic MIC (MMI) in which active elements and passive elements are collectively generated on a semiconductor substrate.
C: Monolithic Microwave IC).

【０００４】現在、これらマイクロ波帯、ミリ波帯のシ
ステムにおいて、パワーアンプ（以後ＰＡと言う）系の
ＭＭＩＣは、発熱の問題等から他のＭＭＩＣと実装方法
が違う。すなわち、ＰＡ系のＭＭＩＣは、放熱性・耐熱
性・低電気抵抗率が必要なため、金スズ共晶ハンダを用
いてダイボンディングを行うことが多く、その他の熱に
弱い部品は、導電接着剤（Ａｇペース卜等）によりダイ
ボンディングを行うことが多い。このため、他のＭＭＩ
Ｃ（ＬＮＡ（ローノイズアンプ）やスイッチ回路、ミキ
サ等）とは別のキャリアに実装し、そのキャリアを他の
部品を実装したキャリアと接続する、という実装方法を
取る。Currently, in these microwave band and millimeter wave band systems, a power amplifier (hereinafter referred to as PA) type MMIC is different in mounting method from other MMICs due to problems such as heat generation. That is, since PA-based MMICs require heat dissipation, heat resistance, and low electrical resistivity, die-bonding is often performed using gold-tin eutectic solder, and other heat-sensitive parts are conductive adhesives. Die bonding is often performed by (Ag pace etc.). Therefore, other MMI
The mounting method is that the C (LNA (low noise amplifier), switch circuit, mixer, etc.) is mounted on a carrier different from that, and the carrier is connected to a carrier on which other components are mounted.

【０００５】接続は、ＭＭＩＣの入出力端子間を、Ａｕ
ワイヤなどでワイヤボンディングにより直接接続する場
合と、マイクロストリップラインを設けたプリント基板
やセラミック基板をＭＭＩＣ間に配置し、ＭＭＩＣの入
出力端子とマイクロストリップラインをワイヤボンディ
ングする場合がある。The connection is made between the input and output terminals of the MMIC by Au.
There are cases where the wires are directly connected by wire bonding, and cases where a printed circuit board or a ceramic substrate provided with microstrip lines are arranged between MMICs and the input / output terminals of the MMICs and the microstrip lines are wire bonded.

【０００６】[0006]

【発明が解決しようする課題】しかしながら、その際に
問題になるのが、キャリアを別にすることで、ＰＡキャ
リア（ＰＡのＭＭＩＣを実装したキャリア）と他のキャ
リアとの間に隙間ができることである。このようにキャ
リア間に隙間ができることで、キャリア間を接続したと
きの整合がくずれ大きな損失になる。However, a problem in this case is that a separate carrier forms a gap between the PA carrier (the carrier on which the MMIC of PA is mounted) and another carrier. . Since a gap is formed between the carriers in this way, the alignment when the carriers are connected is broken, resulting in a large loss.

【０００７】図２に、従来の実装方法で２つのキャリア
を実装した状態の模式図を示す。ローノイズアンプのＭ
ＭＩＣであるＬＮＡ１とＬＮＡ２は、同一キャリア３に
Ａｇペースト４により接着されて実装されており、これ
らＬＮＡ１とＬＮＡ２を繋ぐＡｕワイヤ５の長さとＬＮ
Ａ１とＬＮＡ２間のグランドの距離Ａがほぼ等しいため
に、インピーダンスのズレが小さく、損失がほとんどな
い。ただし、Ａｕワイヤ５で繋いでいる部分のインピー
ダンスがＭＭＩＣの入出力インピーダンスと整合が取れ
ているわけではないので、ＭＭＩＣ間の距離が離れてし
まうと、損失は大きくなる。FIG. 2 is a schematic view showing a state where two carriers are mounted by a conventional mounting method. Low noise amplifier M
The MICs LNA1 and LNA2 are mounted on the same carrier 3 by being adhered with Ag paste 4, and the length and LN of the Au wire 5 that connects these LNA1 and LNA2.
Since the ground distance A between A1 and LNA2 is substantially equal, the impedance shift is small and there is almost no loss. However, since the impedance of the portion connected by the Au wire 5 does not match the input / output impedance of the MMIC, the loss increases as the distance between the MMICs increases.

【０００８】それに対し、２つのキャリア３と６間のＭ
ＭＩＣ、つまりＬＮＡ１とＰＡキャリア６にＡｕ−Ｓｎ
ペースト７により接着されて実装されたＰＡ（ＭＭＩ
Ｃ）８とを繋ぐ場合は、グランドが図１の点線Ｂのよう
な経路になり、両ＭＭＩＣ間で信号を繋ぐＡｕワイヤ９
に対するグランドの距離と長さが違うためにインピーダ
ンスが大きくずれ、不整合（ミスマッチ）状態になり、
大きな損失となる。On the other hand, M between the two carriers 3 and 6
MIC, that is, Au-Sn for LNA1 and PA carrier 6
PA (MMI
C) When connecting with 8, the ground becomes a route as shown by the dotted line B in FIG. 1, and the Au wire 9 for connecting signals between both MMICs
Since the distance and the length of the ground with respect to are different, the impedance greatly shifts, resulting in a mismatch (mismatch) state.
It will be a big loss.

【０００９】本発明の目的は、上述した従来技術に係る
問題点を解決し、キャリア間を隙間なく容易に接続し
て、良好な高周波特性を得ることができる実装構造を有
する高周波回路を提供することにある。An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a high frequency circuit having a mounting structure capable of easily connecting carriers without gaps and obtaining good high frequency characteristics. Especially.

【００１０】[0010]

【課題を解決するための手段】上記目的を達成するため
に、本発明に係る高周波回路は、高周波回路に用いられ
るＩＣを搭載した第一のキャリアと、高周波回路に用い
られるＩＣを搭載した第二のキャリアと、前記第一のキ
ャリアに搭載されたＩＣと前記第二のキャリアに搭載さ
れたＩＣをボンディングするワイヤと、前記第一と第二
のキャリアを結ぶ導電性物質とを有する高周波回路であ
って、前記導電性物質は、前記ワイヤに対するグランド
の距離と前記ワイヤの長さをほぼ同じにして前記第一と
第二のキャリア間に設けることを特徴とするものであ
る。上記構成によれば、キャリア間を隙間なく容易に接
続することができるため、両ＭＭＩＣ間をつなぐＡｕワ
イヤ９に対するグランドの距離と長さが同じとなり、整
合がとりやすくなる。そのため、良好な高周波特性を得
ることができる。In order to achieve the above-mentioned object, a high frequency circuit according to the present invention includes a first carrier having an IC used in the high frequency circuit and a first carrier having an IC used in the high frequency circuit. A high frequency circuit having a second carrier, a wire for bonding the IC mounted on the first carrier and the IC mounted on the second carrier, and a conductive substance connecting the first and second carriers. The conductive material is provided between the first and second carriers such that the distance between the ground and the wire is substantially equal to the length of the wire. According to the above configuration, since it is possible to easily connect the carriers without a gap, the distance and the length of the ground with respect to the Au wire 9 connecting both MMICs are the same, and the matching can be easily achieved. Therefore, good high frequency characteristics can be obtained.

【００１１】また、前記導電性物質を前記第一と第二の
キャリア間に隙間無く埋めることにより前記第一と第二
のキャリア間をつなげることを特徴とするものである。
上記構成によれば、キャリア間を隙間なく容易に接続し
て、良好な高周波特性を得ることができる。Further, the present invention is characterized in that the electrically conductive substance is filled between the first and second carriers without any gap so that the first and second carriers are connected to each other.
According to the above configuration, it is possible to easily connect the carriers without a gap and obtain good high frequency characteristics.

【００１２】[0012]

【発明の実施の形態】実施の形態１．図１（ａ），
（ｂ）は、本発明の実施の形態に係る高周波回路を示す
斜視図と側面図を示し、図２と同一部分は同一符号を付
して示している。図１に示すように、２つのキャリア３
と６間に導電性物質として導電性シート１０を挟むこと
により、キャリア３と６間のグランドが点線Ｂのような
経路になることがなくＣの経路となり、この距離はＬＮ
Ａ１−ＬＮＡ２間の接続（距離Ａ）と同様になる。BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. Figure 1 (a),
2B is a perspective view and a side view showing the high-frequency circuit according to the embodiment of the present invention, in which the same parts as those in FIG. 2 are denoted by the same reference numerals. As shown in FIG. 1, two carriers 3
By sandwiching the conductive sheet 10 as a conductive material between the carrier 3 and the carrier 6, the ground between the carriers 3 and 6 does not become the route of the dotted line B but the route of C, and this distance is LN.
It becomes the same as the connection (distance A) between A1 and LNA2.

【００１３】ここで、挟み込む導電性シート１０は、銅
版（箔）等の金属版では固いために点での接触になって
しまうため、本発明の効果は得られ難い。したがって、
弾力性のある導電性テープ等がよい。さらに、接着性の
あるテープを使用すると、キャリア側面に接着するため
固定が容易にでき、キャリアに密着しやすいものとな
る。Here, since the conductive sheet 10 to be sandwiched is a metal plate such as a copper plate (foil) and is hard, it is in point contact with each other, so that it is difficult to obtain the effect of the present invention. Therefore,
A conductive tape having elasticity is preferable. Furthermore, when an adhesive tape is used, the tape is adhered to the side surface of the carrier, so that the tape can be easily fixed and easily adheres to the carrier.

【００１４】本発明は、構内無線関連技術に適用でき、
２５Ｇ帯等の高周波の製品に用いられ、使用周波数はミ
リ波となる。従来例のようにキャリア間が非接触の場合
は、Ａｕワイヤに対するグランドの距離とＡｕワイヤの
長さが違うため、インピーダンスが大きく崩れ、不整合
となってしまい、大きな損失となってしまうが、本発明
では、キャリア間を導電性物質でつなぐことにより、距
離と長さを同じにし、従来例の問題点を解決することが
できる。この場合、キャリア間が０．１〜０．２ｍｍと
なり、例えばキャリア間を蓋のようなもので覆う技術は
困難となり、キャリア間を導電性物質で埋めることで解
決できる。なお、従来、ＰＡを載せたキャリアは熱が出
るために一般のキャリアより離していたが、本発明では
キャリアを導電性物質で接触させることになる。このと
き熱の問題が生じるが、ＰＡを載せているキャリアを熱
伝導性の良いものにして熱を逃がすようにすれば良く、
熱の影響は多少はあるにしてもほとんど問題はない。INDUSTRIAL APPLICABILITY
It is used for high frequency products such as 25G band, and the used frequency is millimeter wave. When the carriers are not in contact with each other as in the conventional example, the distance between the ground with respect to the Au wire and the length of the Au wire are different, so that the impedance is largely collapsed and mismatch occurs, resulting in a large loss. In the present invention, by connecting the carriers with a conductive substance, the distance and length can be made the same, and the problems of the conventional example can be solved. In this case, the distance between the carriers is 0.1 to 0.2 mm, and it is difficult to cover the spaces between the carriers with something like a lid. This can be solved by filling the spaces between the carriers with a conductive substance. Conventionally, the carrier on which the PA is mounted is separated from the ordinary carrier because heat is generated, but in the present invention, the carrier is brought into contact with a conductive substance. At this time, a problem of heat arises, but it suffices if the carrier on which the PA is mounted has good thermal conductivity so that the heat can escape.
There is little problem if it is affected by heat.

【００１５】実施の形態２．図３は本発明の実施の形態
２を示す断面図である。図３に示すように、本発明の他
の実施の形態として、導電性物質１０ＡをＡｕワイヤ９
に対して下方に開放するような略コ字状として、内部を
空洞状にしても良い。なお、導電性物質の形状は実施の
形態１、２に示したが、それに限定されるものではな
く、Ａｕワイヤ９の長さと、それに対するグランドの距
離がほぼ同じであればよい。Embodiment 2. FIG. 3 is a sectional view showing a second embodiment of the present invention. As shown in FIG. 3, as another embodiment of the present invention, the conductive material 10A is replaced by the Au wire 9
Alternatively, the inside may be formed in a hollow shape so as to open downward. Although the shape of the conductive material is shown in the first and second embodiments, the shape is not limited thereto, and the length of the Au wire 9 and the distance to the ground thereof may be substantially the same.

【００１６】[0016]

【発明の効果】以上の説明のように、本発明によれば、
導電性物質により容易にキャリア間の隙間を埋めること
ができ、良好な高周波特性を得ることができる。また、
導電性物質を用いてキャリア間を隙間なく容易に接続し
て、良好な高周波特性が得られる高周波回路を提供する
ことができる。As described above, according to the present invention,
The gap between the carriers can be easily filled with the conductive substance, and good high frequency characteristics can be obtained. Also,
It is possible to provide a high-frequency circuit in which good carrier-frequency characteristics can be obtained by easily connecting carriers using a conductive material without leaving a gap.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の実施の形態に係る高周波回路を示す
斜視図と側面図である。FIG. 1 is a perspective view and a side view showing a high frequency circuit according to an embodiment of the present invention.

【図２】 従来の実装方法で２つのキャリアを実装した
状態の模式図（側面図）である。FIG. 2 is a schematic diagram (side view) showing a state where two carriers are mounted by a conventional mounting method.

【図３】 本発明の他の実施の形態における高周波回路
を示す断面図である。FIG. 3 is a sectional view showing a high-frequency circuit according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ ＭＭＩＣ ２ ＭＭＩＣ ３ キャリア ４ Ａｇペースト ５ Ａｕワイヤ ６ ＰＡキャリア ７ Ａｕ−Ｓｎペースト ８ ＰＡ（ＭＭＩＣ） ９ Ａｕワイヤ １０，１０Ａ 導電性物質 1 MMIC 2 MMIC 3 career 4 Ag paste 5 Au wire 6 PA carrier 7 Au-Sn paste 8 PA (MMIC) 9 Au wire 10,10A conductive material

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 高周波回路に用いられるＩＣを搭載した
第一のキャリアと、 高周波回路に用いられるＩＣを搭載した第二のキャリア
と、 前記第一のキャリアに搭載されたＩＣと前記第二のキャ
リアに搭載されたＩＣをボンディングするワイヤと、 前記第一と第二のキャリアを結ぶ導電性物質とを有する
高周波回路であって、 前記導電性物質は、前記ワイヤに対するグランドの距離
と前記ワイヤの長さをほぼ同じにして前記第一と第二の
キャリア間に設けることを特徴とする高周波回路。1. A first carrier on which an IC used for a high frequency circuit is mounted, a second carrier on which an IC used for a high frequency circuit is mounted, an IC mounted on the first carrier and the second carrier. A high frequency circuit having a wire for bonding an IC mounted on a carrier, and a conductive material connecting the first and second carriers, wherein the conductive material is a ground distance to the wire and a wire of the wire. A high-frequency circuit characterized in that it is provided between the first and second carriers with substantially the same length. 【請求項２】 請求項１に記載の高周波回路において、 前記導電性物質を前記第一と第二のキャリア間に隙間無
く埋めることにより前記第一と第二のキャリア間をつな
げることを特徴とする高周波回路。2. The high frequency circuit according to claim 1, wherein the electrically conductive substance is filled between the first and second carriers without any gap, thereby connecting the first and second carriers. High frequency circuit to do.
JP2002004236A 2002-01-11 2002-01-11 High frequency circuit Withdrawn JP2003209401A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002004236A JP2003209401A (en) 2002-01-11 2002-01-11 High frequency circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002004236A JP2003209401A (en) 2002-01-11 2002-01-11 High frequency circuit

Publications (1)

Publication Number Publication Date
JP2003209401A true JP2003209401A (en) 2003-07-25

Family

ID=27643612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002004236A Withdrawn JP2003209401A (en) 2002-01-11 2002-01-11 High frequency circuit

Country Status (1)

Country Link
JP (1) JP2003209401A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101938882A (en) * 2009-06-30 2011-01-05 日立电线株式会社 High speed transmission circuit board connection structure
CN108321124A (en) * 2018-01-24 2018-07-24 电子科技大学 A kind of millimeter-wave monolithic gold wire bonding impedance discontinuity device and installation method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101938882A (en) * 2009-06-30 2011-01-05 日立电线株式会社 High speed transmission circuit board connection structure
JP2011014643A (en) * 2009-06-30 2011-01-20 Hitachi Cable Ltd High-speed transmission circuit board connection structure
US8395906B2 (en) 2009-06-30 2013-03-12 Hitachi Cable, Ltd. High-speed transmission circuit board connection structure
CN108321124A (en) * 2018-01-24 2018-07-24 电子科技大学 A kind of millimeter-wave monolithic gold wire bonding impedance discontinuity device and installation method

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