JP2003209350A - Electronic circuit device and its manufacturing method - Google Patents

Electronic circuit device and its manufacturing method

Info

Publication number
JP2003209350A
JP2003209350A JP2002005001A JP2002005001A JP2003209350A JP 2003209350 A JP2003209350 A JP 2003209350A JP 2002005001 A JP2002005001 A JP 2002005001A JP 2002005001 A JP2002005001 A JP 2002005001A JP 2003209350 A JP2003209350 A JP 2003209350A
Authority
JP
Japan
Prior art keywords
solder
alloy
circuit device
electronic circuit
melting point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002005001A
Other languages
Japanese (ja)
Inventor
Hitoshi Takeuchi
均 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP2002005001A priority Critical patent/JP2003209350A/en
Publication of JP2003209350A publication Critical patent/JP2003209350A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

<P>PROBLEM TO BE SOLVED: To achieve Pb-free solder mounting when an IC with a bump is mounted and then solder mounted in an electronic circuit device. <P>SOLUTION: As the solder used in a solder mounting step, a solder containing any of an Sn-Zn or Sn-Zn-Bi alloy having a melting point near 200°C or an Sn-Bi alloy having a melting point near 140°C as a main component is used. Thus, as compared with the case when a conventional solder containing an Sn-Pb eutectic alloy as a main component is used, the melting point and a reflowing temperature can be lowered or can be restricted to a rise of the lowest limit. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、携帯機器等や、電
子手帳または、液晶表表示装置に使用されているドライ
バーICやメモリーIC,コントローラIC等のベアチ
ップと、はんだ付け表面実装部品が混載さている電子回
路装置及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bare chip such as a driver IC, a memory IC, a controller IC used in a portable device, an electronic notebook or a liquid crystal display device, and a soldering surface mounting component. The present invention relates to an electronic circuit device and a manufacturing method thereof.

【0002】[0002]

【従来の技術】従来の電子回路装置の製造方法において
は、以下のようなことが知られている。
2. Description of the Related Art The following is known in a conventional method for manufacturing an electronic circuit device.

【0003】フレキシブル基板上に、バンプを形成した
ICをフェイスダウンで接合する第1の工程は、ICの
電極にAu(金)で形成された、バンプと呼ばれる突起
電極と、フレキシブル基板の導体パターン表面にAuメ
ッキが施されたものを、異方性導電接着剤、絶縁性接着
剤と電極間の接触(メカニカルコンタクト)、導電性接
着剤+樹脂封止、または金属間(Au:Au)の拡散+
樹脂封止、等により接合する。
The first step of joining a bump-formed IC on a flexible substrate in a face-down manner is a bump electrode, which is formed of Au (gold) on the IC electrode, and a conductor pattern on the flexible substrate. The surface of which is plated with Au is used for anisotropic conductive adhesive, contact between insulating adhesive and electrode (mechanical contact), conductive adhesive + resin sealing, or between metals (Au: Au). Spread +
Join by resin sealing or the like.

【0004】また、フレキシブル基板の導体パターン表
面にSn(錫)メッキが施されたものを、金属間(A
u:Sn)の拡散+樹脂封止、により接合する場合もあ
る。
In addition, a conductor pattern surface of a flexible substrate plated with Sn (tin) is used as an intermetallic (A
In some cases, they are joined by diffusion of u: Sn) + resin sealing.

【0005】上記の異方性導電接着剤、絶縁性接着剤、
樹脂封止に用いられる主成分にはエポキシ系樹脂、アク
リル系樹脂、等の樹脂が含まれている。
The above-mentioned anisotropic conductive adhesive, insulating adhesive,
The main components used for resin sealing include resins such as epoxy resins and acrylic resins.

【0006】各種表面実装用部品を接合する第2の工程
は、第1の工程の終了後に行う。
The second step of joining various surface mounting parts is performed after the end of the first step.

【0007】接合材料は一般的にはSn−37重量%P
b(鉛)の共晶組成を中心とする融点183℃付近のは
んだを使用する。量産時は、フラックスとはんだボール
を混練した半田ペーストを基板上に印刷し、表面実装用
部品をチップマウンター等で搭載し、リフロー炉によ
り、加熱溶融・再凝固させることにより接合する。リフ
ロー時の部品の最高温度は融点に対して約40℃のマー
ジンをとり、220℃付近になるように設定する。
The bonding material is generally Sn-37 wt% P
A solder having a eutectic composition of b (lead) and a melting point of about 183 ° C. is used. At the time of mass production, solder paste in which flux and solder balls are kneaded is printed on a substrate, surface mounting components are mounted by a chip mounter or the like, and they are joined by heating, melting and resolidifying in a reflow furnace. The maximum temperature of the component during reflow is set to about 220 ° C with a margin of about 40 ° C to the melting point.

【0008】また近年はPbを含まない、融点が220
℃付近のSn−Ag−Cu系はんだが使用される場合も
ある。この場合、リフロー時の部品の最高温度は250
〜260℃が必要になる。
In recent years, the melting point of Pb-free is 220.
In some cases, Sn-Ag-Cu based solder having a temperature of around 0 ° C is used. In this case, the maximum temperature of parts during reflow is 250
~ 260 ° C is required.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、従来の
技術においては以下のような問題点がある。Pb含有は
んだを使用する場合は、Pbが毒性の大きい金属であり
環境汚染等を生ずる。
However, the conventional techniques have the following problems. When using Pb-containing solder, Pb is a highly toxic metal and causes environmental pollution.

【0010】Sn−Ag−Cu系はんだを使用する場合
は、下記(1)〜(3)のような問題を生ずる。 (1)融点が高くなり、リフロー温度も上昇するため、
リフロー時の熱ストレスが大きくなり、IC接合部自体
や封止樹脂が劣化し、接続不良、強度低下、信頼性低
下、等が発生する場合がある。また、ICや表面実装部
品の性能が劣化する場合がある。 (2)従来のSn−Pb系はんだ用のリフロー炉が能力
不足で使えなくなる場合がある。 (3)貴金属であるAgを含むため、はんだの材料コス
トが上がる。 本発明は上記のような課題を解決するものであり、Pb
を使用することなく、かつ、フレキシブル基板上へのI
C並びに表面実装部品の接合を実現することにある。
When Sn-Ag-Cu based solder is used, the following problems (1) to (3) occur. (1) Since the melting point is high and the reflow temperature is high,
In some cases, the thermal stress during reflow increases, the IC joint portion itself and the sealing resin deteriorate, and connection failure, strength reduction, reliability deterioration, etc. may occur. In addition, the performance of ICs and surface mount components may deteriorate. (2) The conventional reflow furnace for Sn-Pb-based solder may be unusable due to insufficient capacity. (3) Since the precious metal Ag is included, the material cost of the solder increases. The present invention solves the above problems, and
I on a flexible substrate without using
It is to realize the joining of C and surface mount components.

【0011】[0011]

【課題を解決するための手段】前記課題を解決する手段
として、本発明では、フレキシブル基板上に、バンプを
形成したICをフェイスダウンで接合する第1の工程
と、各種表面実装用部品を接合する第2の工程を含む電
子回路装置の製造方法において、第2の工程で用いる接
合材料に、融点200℃付近のSn−Zn系、Sn−Z
n−Bi系、または融点140℃付近のSn−Bi系合
金のいずれかを主成分とするはんだを使用することにし
た。
As means for solving the above problems, in the present invention, the first step of face-down bonding of ICs having bumps formed thereon and the bonding of various surface mounting components are performed on a flexible substrate. In the method for manufacturing an electronic circuit device including the second step, the bonding material used in the second step is a Sn—Zn-based or Sn—Z-based material having a melting point of about 200 ° C.
It has been decided to use a solder whose main component is either an n-Bi-based alloy or a Sn-Bi-based alloy having a melting point of about 140 ° C.

【0012】従って、Pbを含有することなしに、従来
のSn−Pb系共晶合金を主成分とするはんだを用いた
場合に比べ、融点及びリフロー温度を低下させる、また
は最小限の上昇に留めることが可能となる。また、Ag
を含有しないのでSn−Ag−Cu系に比べ、はんだ材
料のコストを抑えることも可能となる。
Therefore, the melting point and the reflow temperature are lowered, or the increase is kept to a minimum, as compared with the case of using the conventional solder containing Sn-Pb eutectic alloy as a main component without containing Pb. It becomes possible. Also, Ag
Since it does not contain Sn, the cost of the solder material can be suppressed as compared with the Sn-Ag-Cu system.

【0013】[0013]

【発明の実施の形態】以下に本発明を図面に基づいて説
明する。
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to the drawings.

【0014】図1から図4で説明するのは、本発明にか
かる電子回路装置の一種である小型表示素子の駆動回路
ブロックの製造方法を模式的に示したものである。
1 to 4 schematically show a method of manufacturing a drive circuit block for a small display element, which is a kind of electronic circuit device according to the present invention.

【0015】図1は本発明にかかる電子回路装置の製造
方法の第1の工程を示す上面図、図2は本発明にかかる
電子回路装置の製造方法の第1の工程を示す断面図であ
る。基板1にはポリイミド上に銅箔の導体配線(図示さ
れていない)が形成され、さらに接合部近傍配線表面に
Snメッキ処理が施されたフレキシブル基板である。
FIG. 1 is a top view showing a first step of a method of manufacturing an electronic circuit device according to the present invention, and FIG. 2 is a sectional view showing a first step of a method of manufacturing an electronic circuit device according to the present invention. . The substrate 1 is a flexible substrate in which copper foil conductor wiring (not shown) is formed on polyimide, and the wiring surface in the vicinity of the joint is Sn-plated.

【0016】IC2はベアチップの電極上に、Auのバ
ンプ(突起電極)が100〜1000個程度、形成さ
れ、基板1の電極(図示されていない)とIC2のバン
プ間を位置合わせし、200〜500℃の温度、1電極
あたり数〜100gの荷重で熱圧着することにより、A
uとSnが金属間拡散し、IC接合部4が形成される。
The IC 2 has about 100 to 1000 Au bumps (protruding electrodes) formed on the electrodes of the bare chip, and the electrodes (not shown) of the substrate 1 and the bumps of the IC 2 are aligned to each other. By thermocompression bonding at a temperature of 500 ° C. and a load of several to 100 g per electrode, A
u and Sn diffuse between the metals, and the IC joint portion 4 is formed.

【0017】IC2と基板1の接合は、これ以外にも、
異方性導電接着剤、絶縁性接着剤と電極間の接触(メカ
ニカルコンタクト)、導電性接着剤+樹脂封止、または
金属間(Au:Au)の拡散+樹脂封止、等の様々な方
法で行うことが可能で、基板1の導体配線及びその表面
処理や、バンプの仕様もそれぞれに最適なものを選択可
能である。
In addition to this, the IC 2 and the substrate 1 are joined together.
Various methods such as anisotropic conductive adhesive, contact between insulating adhesive and electrode (mechanical contact), conductive adhesive + resin sealing, or diffusion between metals (Au: Au) + resin sealing It is possible to select the optimum one for the conductor wiring of the substrate 1, the surface treatment thereof, and the specifications of the bumps.

【0018】IC接合部4の形成後、IC接合部4や半
導体素子の保護、及び補強のため、基板1、IC2、I
C接合部4の隙間および周辺に封止樹脂3を供給し、硬
化する。
After the formation of the IC joint portion 4, the substrate 1, the IC 2 and the substrate I, I, are provided to protect and reinforce the IC joint portion 4 and the semiconductor element.
The sealing resin 3 is supplied to the gap of the C-bonding portion 4 and its periphery and cured.

【0019】封止樹脂3は液体の状態でIC2の周辺に
塗布することで供給され、流動することによってIC2
と基板1の隙間およびIC2の周辺に充填され、熱・U
V・光・嫌気状態・2液の反応、等の単独または組み合
わせにより硬化する。封止樹脂3にはエポキシ系やアク
リル系または両者を併せた樹脂が使用され、熱膨張や粘
度、硬化条件等の各種特性に併せた添加剤、フィラー等
が含まれる場合もある。また、塗布時の粘度調整のた
め、基板1や樹脂自身に熱を加える場合もある。
The sealing resin 3 is supplied by being applied to the periphery of the IC 2 in a liquid state, and is supplied by flowing to the IC 2
Is filled in the gap between the substrate 1 and the substrate 1 and around the IC 2,
It cures by V, light, anaerobic condition, reaction of 2 liquids, etc. alone or in combination. An epoxy resin, an acrylic resin, or a combination of both resins is used as the sealing resin 3, and there are cases in which additives, fillers, etc., which meet various characteristics such as thermal expansion, viscosity, and curing conditions, are included. In addition, heat may be applied to the substrate 1 and the resin itself in order to adjust the viscosity during coating.

【0020】図3は本発明にかかる電子回路装置の製造
方法の第2の工程を示す上面図、図4は本発明にかかる
電子回路装置の製造方法の第2の工程を示す断面図であ
る。
FIG. 3 is a top view showing a second step of the method for manufacturing an electronic circuit device according to the present invention, and FIG. 4 is a sectional view showing a second step of the method for manufacturing an electronic circuit device according to the present invention. .

【0021】基板1のIC2実装部周辺には、6ピンの
SOP5が1個及びチップ抵抗6が6個を実装するため
の電極(図示されていない)が形成されている。
Electrodes (not shown) for mounting one 6-pin SOP 5 and six chip resistors 6 are formed around the IC 2 mounting portion of the substrate 1.

【0022】次に、電極上にフラックスを含有する半田
ペーストをディスペンス法や印刷法で供給する。はんだ
供給は、半田ペーストによる方法以外にも、導体配線側
またはリード端子側またはIC電極側に、電気メッキ、
無電解メッキ、溶融メッキ(はんだコート)や、半田ボ
ールのマウント等の方法で供給されたものを単独、また
は組み合わせて用いる場合や、糸はんだを手動・自動で
送りながら供給する場合などがある。
Next, a solder paste containing flux is supplied on the electrodes by a dispensing method or a printing method. In addition to the solder paste method, solder is supplied to the conductor wiring side, the lead terminal side or the IC electrode side by electroplating,
There are cases in which electroless plating, hot dip plating (solder coating), solder ball mounting, and other methods that are supplied are used alone or in combination, and when thread solder is supplied manually or automatically.

【0023】半田供給後、SOP5及びチップ抵抗6の
電子部品を基板側電極上にマウントする。半田ペースト
による方法以外の半田供給方法のときは、半田供給より
も前に接着剤等を用いて電子部品を供給する場合もあ
る。
After the solder is supplied, the electronic parts of the SOP 5 and the chip resistor 6 are mounted on the board-side electrodes. In the case of a solder supply method other than the method using solder paste, an electronic component may be supplied using an adhesive or the like before the solder supply.

【0024】電子部品マウント後、熱風、赤外線、レー
ザ、熱圧着、ハンダコテ、等の単独あるいは併用によ
り、加熱・溶融し、その後自然または強制的な冷却によ
る再凝固により、基板1とSOP5並びにチップ抵抗6
の電極間にはんだ接合部7が形成される。
After mounting the electronic parts, they are heated and melted by hot air, infrared rays, laser, thermocompression bonding, soldering iron, etc., alone or in combination, and then re-solidified by natural or forced cooling. 6
Solder joints 7 are formed between the electrodes.

【0025】この場合、接合部の雰囲気を窒素置換する
等して酸素濃度が低い状態にすることにより、フラック
スの劣化や、はんだ表面の酸化を抑制できる。
In this case, it is possible to suppress the deterioration of the flux and the oxidation of the solder surface by making the atmosphere in the joint part nitrogen-replaced so that the oxygen concentration is low.

【0026】ここで小型表示素子の駆動回路ブロックが
完成する。この後、LCD等の表示素子と駆動回路ブロ
ックを接合することにより、表示モジュールが完成す
る。
The drive circuit block for the small display element is completed here. Then, the display module is completed by joining the display element such as the LCD and the drive circuit block.

【0027】この工程で使用されるはんだには、融点2
00℃付近のSn−Zn系、Sn−Zn−Bi系、また
は融点140℃付近のSn−Bi系合金のいずれかを主
成分とするはんだを使用する。リフロー炉で加熱する場
合の部品の最高温度は、Sn−Zn系、並びにSn−Z
n−Bi系合金を主成分とするはんだの場合で、従来の
Sn−Pb共晶はんだ並の220℃程度、Sn−Bi系
合金を主成分とするはんだの場合は、180℃程度で安
定した接合を実現することが可能となる。
The solder used in this process has a melting point of 2
A solder containing a Sn-Zn-based alloy, a Sn-Zn-Bi-based alloy near 00 ° C, or a Sn-Bi-based alloy near a melting point of 140 ° C as a main component is used. The maximum temperature of parts when heated in a reflow furnace is Sn-Zn system, as well as Sn-Z.
In the case of a solder containing an n-Bi alloy as a main component, it was stable at about 220 ° C, which is comparable to that of a conventional Sn-Pb eutectic solder, and in the case of a solder containing an Sn-Bi alloy as a main component, it was stable at about 180 ° C. It becomes possible to realize joining.

【0028】これにより、Pbを含有することなしに、
従来のSn−Pb系共晶合金を主成分とするはんだを用
いた場合に比べ、融点及びリフロー温度を低下させる、
または最小限の上昇に留めることが可能となる。
As a result, without containing Pb,
The melting point and the reflow temperature are reduced as compared with the case of using a solder containing a conventional Sn-Pb-based eutectic alloy as a main component.
Or it is possible to keep the rise to the minimum.

【0029】従って、第1の工程で作成されたIC接合
部4及び封止樹脂3の劣化を防ぎ、IC2の接合品質を
確保・維持出来る。また、従来のSn−Pb系はんだ用
のリフロー炉が流用でき、かつ材料に高価なAgを含有
しないのでSn−Ag−Cu系に比べ、はんだ材料のコ
ストを抑えることが可能となる。
Therefore, deterioration of the IC bonding portion 4 and the sealing resin 3 created in the first step can be prevented, and the bonding quality of the IC 2 can be secured and maintained. Further, since the conventional reflow furnace for Sn-Pb solder can be used and the material does not contain expensive Ag, the cost of the solder material can be suppressed as compared with the Sn-Ag-Cu solder.

【0030】Sn−Zn系はんだはSn−9重量%Zn
共晶(融点198℃)を基礎としたもので、Znは7〜
10重量%の範囲が良い。
Sn-Zn based solder is Sn-9 wt% Zn.
It is based on a eutectic (melting point 198 ° C), and Zn is 7-
A range of 10% by weight is preferable.

【0031】Znはこの範囲外では固液共存範囲が広く
なる、あるいは凝固開始温度が高くなりすぎ、かつ強度
や信頼性にも悪影響を与える。
Outside of this range, Zn has a wide solid-liquid coexistence range or an excessively high solidification start temperature, and adversely affects strength and reliability.

【0032】表1はZnの組成を変えてSn−Zn系は
んだの信頼性を試験したもので、−40℃と125℃の
温度サイクル試験を行った結果である。
Table 1 shows the reliability of the Sn--Zn type solder tested by changing the composition of Zn, and shows the results of the temperature cycle test of -40.degree. C. and 125.degree.

【0033】接合強度が初期の50%以下になるまでの
温度サイクル数を調べたものである。
The number of temperature cycles until the bonding strength was 50% or less of the initial value was examined.

【0034】表1からZnは7〜10重量%の範囲が良
いことがわかる。
From Table 1, it can be seen that Zn is preferably in the range of 7 to 10% by weight.

【0035】[0035]

【表1】 [Table 1]

【0036】濡れ性、強度、信頼性、等の特性改善のた
めFe、Ni、Co、Au、Ag、Cu、Mn、Ti、
Cr、Zn、Al、B、As、Se、Te、Ga、G
e、Pなどを微量添加することも可能である。
Fe, Ni, Co, Au, Ag, Cu, Mn, Ti, for improving the properties such as wettability, strength, reliability, etc.
Cr, Zn, Al, B, As, Se, Te, Ga, G
It is also possible to add a small amount of e, P or the like.

【0037】Sn−Zn−Bi系はんだは、Sn−Zn
系はんだの濡れ性向上、及び融点低下のために、Biを
添加したもので、Znは7〜10重量%、Biは1〜9
重量%の範囲が良い。
Sn-Zn-Bi solder is Sn-Zn.
Bi is added in order to improve the wettability of the system solder and to lower the melting point. Zn is 7 to 10% by weight and Bi is 1 to 9%.
The range of weight% is good.

【0038】Biがこれより少ないと効果がなく、多く
なると脆すぎ、信頼性が大きく低下する。
If Bi is less than this range, it is ineffective, and if it is more than this range, it is too brittle and the reliability is greatly reduced.

【0039】表2は92%Sn−8%ZnにBiを添加
していったときのSn−Zn−Bi系はんだの濡れ広が
りを試験したもので、濡れ広がり試験方法はJIS Z
3197による。
Table 2 shows the wet spread of Sn-Zn-Bi solder when Bi was added to 92% Sn-8% Zn. The wet spread test method was JIS Z.
According to 3197.

【0040】表2からBi添加が1重量%の以上で効果
があることがわかる。
From Table 2, it is understood that the effect is obtained when Bi is added in an amount of 1% by weight or more.

【0041】[0041]

【表2】 [Table 2]

【0042】表3は92%Sn−8%ZnにBiを添加
していったときのSn−Zn−Bi系はんだの信頼性を
上記と同様の試験で調べた結果である。
Table 3 shows the results of examining the reliability of the Sn-Zn-Bi type solder when Bi was added to 92% Sn-8% Zn in the same test as above.

【0043】表3よりBi添加は9重量%の以下がよい
ことがわかる。
From Table 3, it can be seen that Bi is preferably added in an amount of 9% by weight or less.

【0044】[0044]

【表3】 [Table 3]

【0045】以上表2と表3からわかるようにBiが1
重量%より少ないと効果がなく、9重量%より多くなる
と脆すぎ、信頼性が大きく低下する。
As can be seen from Tables 2 and 3, Bi is 1
If it is less than 10% by weight, no effect is obtained, and if it is more than 9% by weight, it is too brittle and the reliability is greatly reduced.

【0046】濡れ性、強度、信頼性、等の特性改善のた
め更に他の成分を微量添加することも可能である。
It is also possible to add a small amount of other components in order to improve properties such as wettability, strength, reliability and the like.

【0047】Sn−Bi系はんだはSn−58重量%B
i共晶(融点139℃)を基礎としたもので、Biは3
0〜72重量%の範囲が良い。
Sn-Bi solder is Sn-58 wt% B
Based on i eutectic (melting point 139 ° C), Bi is 3
A range of 0 to 72% by weight is preferable.

【0048】Biはこの範囲外では固液共存範囲が広く
なる、あるいは凝固開始温度が高くなりすぎ、また多い
と強度や信頼性にも悪影響を与える。
When Bi is outside this range, the solid-liquid coexistence range becomes wide, or the solidification start temperature becomes too high, and when it is too large, strength and reliability are adversely affected.

【0049】表4はBiの組成を変えてSn−Bi系は
んだの信頼性を試験したもので、−40℃と100℃の
温度サイクル試験を行い接合強度が初期の50%以下に
なるまでの温度サイクル数を調べたものである。
Table 4 shows the reliability of Sn-Bi type solders tested by changing the composition of Bi. A temperature cycle test of -40 ° C and 100 ° C was carried out until the bonding strength was 50% or less of the initial value. The number of temperature cycles was investigated.

【0050】これよりBiは30〜72重量%の範囲が
良いことがわかる。
From this, it is understood that Bi is preferably in the range of 30 to 72% by weight.

【0051】[0051]

【表4】 [Table 4]

【0052】強度や信頼性改善のため特に0.1〜3.
0重量%までのAgを添加することもある。
In order to improve strength and reliability, 0.1-3.
Up to 0% by weight Ag may be added.

【0053】強度や信頼性等の特性改善のため更に他の
成分を添加することも可能である。
Other components may be added to improve properties such as strength and reliability.

【0054】なお本発明のPbを含まないはんだとは不
可避不純物として0.1重量%以下しかPbを含まない
ものをいう。
The Pb-free solder of the present invention means a solder containing 0.1% by weight or less of Pb as an unavoidable impurity.

【0055】上述した本発明にかかる実施例は代表的な
製造方法及び構成を示したもので、接合に用いるはんだ
以外の、各部品・部材の形状、個数、実装位置、大き
さ、組み合わせは、製品仕様によって任意に設定でき
る。
The above-described embodiment according to the present invention shows a typical manufacturing method and configuration. The shape, the number, the mounting position, the size, and the combination of each component / member other than the solder used for joining are as follows. It can be set arbitrarily according to the product specifications.

【0056】基板は、ポリイミドベース以外にも、PE
T等をベースとしたものに、銅、アルミ、金、銀、ニッ
ケル、等の導体配線が形成されたものを使用する場合が
あり、さらに導体配線上には、プリフラックス、はんだ
めっき、金メッキ、錫メッキ、パラジウムメッキ、ニッ
ケルメッキ、銀メッキ、クロムメッキ等の処理が単独ま
たは組み合わせて用いられる場合がある。
The substrate is not only a polyimide base but also a PE.
There is a case where a conductor wiring of copper, aluminum, gold, silver, nickel, etc. is formed on the base material such as T, and further, on the conductor wiring, preflux, solder plating, gold plating, Treatments such as tin plating, palladium plating, nickel plating, silver plating, and chrome plating may be used alone or in combination.

【0057】バンプ付きICはベアチップ以外にも、ウ
エハレベルパッケージやチップサイズパッケージ等を用
いる場合があり、また複数チップが実装される場合もあ
る。
As the bumped IC, a wafer level package or a chip size package may be used in addition to the bare chip, and a plurality of chips may be mounted.

【0058】はんだ付けされる電子部品は、SOP、チ
ップ抵抗以外にも、QFP、BGA、トランジスタ、ダ
イオード、コンデンサ、サーミスタ、水晶、等々の各種
部品・各種仕様が用いられる場合がある。
As the electronic parts to be soldered, various parts and various specifications such as QFP, BGA, transistor, diode, capacitor, thermistor, crystal, etc. may be used in addition to SOP and chip resistor.

【0059】[0059]

【発明の効果】以上説明してきたように、本発明によれ
ば、バンプ付きICの実装後に鉛を含まないはんだで実
装を行う場合でも、IC接合時に使用される樹脂成分の
劣化を防ぎ、従来のSn−Pb系はんだ用のリフロー炉
が流用でき、はんだ材料のコストを抑えることが可能と
なる。
As described above, according to the present invention, even when the lead-free solder is mounted after mounting the bumped IC, it is possible to prevent the deterioration of the resin component used for IC bonding, The reflow furnace for Sn-Pb type solder can be used, and the cost of the solder material can be suppressed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明にかかる電子回路装置の製造方法の第1
の工程を示す上面図。
FIG. 1 is a first method of manufacturing an electronic circuit device according to the present invention.
FIG.

【図2】本発明にかかる電子回路装置の製造方法の第1
の工程を示す断面図。
FIG. 2 is a first method of manufacturing an electronic circuit device according to the present invention.
FIG.

【図3】本発明にかかる電子回路装置の製造方法の第2
の工程を示す上面図。
FIG. 3 is a second method of manufacturing an electronic circuit device according to the present invention.
FIG.

【図4】本発明にかかる電子回路装置の製造方法の第2
の工程を示す断面図。
FIG. 4 is a second method of manufacturing an electronic circuit device according to the present invention.
FIG.

【符号の説明】[Explanation of symbols]

1 ・・・基板 2 ・・・IC 3 ・・・封止樹脂 4 ・・・IC接合部 5 ・・・SOP 6 ・・・チップ抵抗 7 ・・・はんだ接合部 1 ... Substrate 2 ... IC 3 ... Sealing resin 4 ... IC junction 5 ... SOP 6 ... Chip resistance 7 ・ ・ ・ Solder joint

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 フレキシブル基板上に、バンプを形成し
たIC及び各種表面実装用部品が実装されている電子回
路装置において、前記フレキシブル基板と前記各種表面
実装用部品の接合が、Sn−Zn系、Sn−Zn−Bi
系、またはSn−Bi系合金のいずれかを主成分とする
はんだでなされていることを特徴とする電子回路装置。
1. In an electronic circuit device in which an IC having bumps formed thereon and various surface mounting components are mounted on a flexible substrate, the flexible substrate and the various surface mounting components are bonded by Sn—Zn system, Sn-Zn-Bi
An electronic circuit device, characterized in that it is made of a solder whose main component is either a Sn-based alloy or a Sn-Bi alloy.
【請求項2】 前記Sn−Zn系合金が7.0〜10.
0重量%Zn、残部Snを主成分とした合金であること
を特徴とする請求項1記載の電子回路装置。
2. The Sn—Zn alloy is 7.0 to 10.
The electronic circuit device according to claim 1, wherein the electronic circuit device is an alloy containing 0 wt% Zn and the balance Sn as main components.
【請求項3】 前記Sn−Zn−Bi系合金が7.0〜
10.0重量%Zn、1.0〜9.0重量%Bi、残部
Snを主成分とした合金であることを特徴とする請求項
1記載の電子回路装置。
3. The Sn—Zn—Bi alloy is 7.0 to 7.0.
The electronic circuit device according to claim 1, wherein the alloy is an alloy containing 10.0 wt% Zn, 1.0 to 9.0 wt% Bi, and the balance Sn as main components.
【請求項4】 前記Sn−Bi系合金が30.0〜7
2.0重量%Bi、残部Snを主成分とした合金である
ことを特徴とする請求項1記載の電子回路装置。
4. The Sn—Bi alloy is 30.0 to 7
2. The electronic circuit device according to claim 1, wherein the alloy is an alloy containing 2.0 wt% Bi and the balance Sn as a main component.
【請求項5】 フレキシブル基板上に、バンプを形成し
たICをフェイスダウンで接合する第1の工程と、前記
フレキシブル基板上に各種表面実装用部品を接合する第
2の工程を含み、 前記第2の工程において用いられる接合材料が、Sn−
Zn系、Sn−Zn−Bi系、またはSn−Bi系合金
のいずれかを主成分とするはんだであることを特徴とす
る電子回路装置の製造方法。
5. A first step of joining ICs having bumps formed face down on a flexible substrate, and a second step of joining various surface mounting parts on the flexible substrate, the second step The bonding material used in the step is Sn-
A method of manufacturing an electronic circuit device, which is a solder containing a Zn-based, Sn-Zn-Bi-based, or Sn-Bi-based alloy as a main component.
JP2002005001A 2002-01-11 2002-01-11 Electronic circuit device and its manufacturing method Pending JP2003209350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002005001A JP2003209350A (en) 2002-01-11 2002-01-11 Electronic circuit device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002005001A JP2003209350A (en) 2002-01-11 2002-01-11 Electronic circuit device and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2003209350A true JP2003209350A (en) 2003-07-25

Family

ID=27644167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002005001A Pending JP2003209350A (en) 2002-01-11 2002-01-11 Electronic circuit device and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2003209350A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005142209A (en) * 2003-11-04 2005-06-02 Nec Infrontia Corp Electronic circuit device
JP2016051798A (en) * 2014-08-29 2016-04-11 大日本印刷株式会社 Method of manufacturing mounting board and mounting board
CN110205517A (en) * 2019-06-26 2019-09-06 广东省焊接技术研究所(广东省中乌研究院) A method of refinement Sn-Bi system solder alloy eutectic structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005142209A (en) * 2003-11-04 2005-06-02 Nec Infrontia Corp Electronic circuit device
JP2016051798A (en) * 2014-08-29 2016-04-11 大日本印刷株式会社 Method of manufacturing mounting board and mounting board
CN110205517A (en) * 2019-06-26 2019-09-06 广东省焊接技术研究所(广东省中乌研究院) A method of refinement Sn-Bi system solder alloy eutectic structure

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