JP2003209343A - Printed circuit board - Google Patents
Printed circuit boardInfo
- Publication number
- JP2003209343A JP2003209343A JP2002007035A JP2002007035A JP2003209343A JP 2003209343 A JP2003209343 A JP 2003209343A JP 2002007035 A JP2002007035 A JP 2002007035A JP 2002007035 A JP2002007035 A JP 2002007035A JP 2003209343 A JP2003209343 A JP 2003209343A
- Authority
- JP
- Japan
- Prior art keywords
- base material
- circuit conductor
- conductor
- copper foil
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【発明が属する技術分野】本発明は、基材と銅箔や部品
搭載パッドとの密着度を向上させたプリント配線基板に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board having improved adhesion between a base material and a copper foil or a component mounting pad.
【0002】[0002]
【従来の技術】一般に、プリント配線基板は樹脂などの
基材に銅箔や部品搭載パッドなどが接着されて配置さ
れ、多数の単位回路が並列されて形成されており、プリ
ント配線基板を個々の単位回路を1個(単位)ずつ含む
大きさに切断して使用単位として用いられている。2. Description of the Related Art Generally, a printed wiring board is arranged by adhering a copper foil, a component mounting pad, etc. to a base material such as a resin, and a large number of unit circuits are arranged in parallel. The unit circuit is cut into a size including one (unit) and used as a unit for use.
【0003】近来各種電子機器の小型化を促進するた
め、プリント配線基板の小型化が図られ、プリント配線
基板の回路幅や部品搭載パッド寸法の微細化が行われて
いる。例えば、BGA,CAP.MCPといったパッケ
ージ向けのプリント配線基板においては、2005年に
は0.3mmピッチCSPの採用により、半田ボール搭
載パッドは直径0.15mm、配線ピッチは40μmの
製作寸法が必要とされると推測される。In recent years, in order to promote miniaturization of various electronic devices, miniaturization of printed wiring boards has been attempted, and circuit width of printed wiring boards and component mounting pad dimensions have been miniaturized. For example, BGA, CAP. In the printed wiring board for packages such as MCP, the solder ball mounting pad is required to have a manufacturing dimension of 0.15 mm in diameter and a wiring pitch of 40 μm by adopting 0.3 mm pitch CSP in 2005. .
【0004】[0004]
【発明が解決しようとする課題】しかしながら、上記プ
リント配線基板においては、基材と銅箔や部品搭載パッ
ド等の導体との接着(密着)強度は、回路幅や部品搭載
パッド寸法の微細化により低下するもので、微細化によ
る接着強度の低下状況の一例を図10の表1に示す。こ
のように微細化により接着強度が低下するため、外方か
らの衝撃、引っかけ等の外的ストレスを受けて基材と導
体とが剥離する恐れがあるという問題があった。However, in the above-mentioned printed wiring board, the adhesion (adhesion) strength between the base material and the conductor such as the copper foil or the component mounting pad depends on the miniaturization of the circuit width and the component mounting pad size. Table 1 in FIG. 10 shows an example of the situation in which the adhesive strength is reduced due to miniaturization. Since the adhesive strength is reduced due to the miniaturization as described above, there is a problem that the base material and the conductor may be separated from each other due to external stress such as external impact or hooking.
【0005】この問題を解決するために基材と導体との
接着強度を増大させる必要があり、図11に示すよう
に、導体Aの表面に、多数の凸部Bと凹部Cとを大きく
形成して、基材(樹脂)Dの表面に導体Aの表面の凹凸
を食い込ませることで接着(密着)強度を増大させるこ
とが知られているが、微細な配線の形成においては、凹
凸が小さい方が有利であるという問題があった。In order to solve this problem, it is necessary to increase the adhesive strength between the base material and the conductor, and as shown in FIG. 11, a large number of convex portions B and concave portions C are formed on the surface of the conductor A. Then, it is known that the unevenness of the surface of the conductor A is eroded into the surface of the base material (resin) D to increase the adhesion (adhesion) strength, but the unevenness is small in the formation of fine wiring. There was a problem that it was more advantageous.
【0006】本発明の目的は、これらの問題を解決し、
導体と基材の接触面の凹凸を大きくすることなく、基材
と配線及び部品搭載パッドとの接着(密着)強度を増大
させることのできるプリント配線基板を提供することで
ある。The object of the present invention is to solve these problems,
It is an object of the present invention to provide a printed wiring board capable of increasing the adhesion (adhesion) strength between a base material and wiring and component mounting pads without increasing the unevenness of the contact surface between the conductor and the base material.
【0007】[0007]
【課題を解決するための手段】上記目的を達成するため
に本発明のプリント配線基板は、請求項1のものは、基
材と回路を形成する回路導体とを備えるプリント配線基
板において、基材の表面に飛び出して回路導体を形成
し、飛び出して形成された回路導体を押圧・加熱して基
材内に埋没させたことにより、基材に埋没した回路導体
は、基材との接触面積が増大するために、導体と基材と
の接着(密着)強度が著しく増大する。特にパネルエッ
チング法で形成された回路導体は、断面形が台形状に末
広がりとなるため、回路導体を埋没させることで得られ
る接着(密着)強度向上の効果が大きいものである。さ
らに、回路導体が基材に埋没しているため、ぶつかる等
の外方からの衝撃や引っかける等の外的な物理ストレス
を受けにくくなり、導体と基材が剥離するといった不具
合の発生を抑制することができる。請求項2のものは、
基材の表面に飛び出して形成された回路導体の外表面に
微細な凹凸を設けることにより、埋没した回路導体と基
材との接触面積が増大し、接触(密着)強度を大きくす
ることができる。In order to achieve the above object, the printed wiring board according to the present invention has a base material and a circuit conductor forming a circuit. The circuit conductor embedded in the base material has a contact area with the base material that is formed by popping out the circuit conductor on the surface of the As a result, the strength of adhesion (adhesion) between the conductor and the substrate is significantly increased. In particular, the circuit conductor formed by the panel etching method has a trapezoidal cross section, and thus has a large effect of improving the bonding (adhesion) strength obtained by burying the circuit conductor. Furthermore, since the circuit conductor is buried in the base material, it is less likely to be subjected to external physical stress such as bumping or external impact or being caught, and the occurrence of problems such as separation of the conductor and the base material is suppressed. be able to. According to claim 2,
By providing fine irregularities on the outer surface of the circuit conductor formed by projecting on the surface of the base material, the contact area between the buried circuit conductor and the base material is increased, and the contact (adhesion) strength can be increased. .
【0008】[0008]
【発明の実施の形態】図1乃至図4に基づいて、パネル
鍍金法を用いた本発明の第1実施例を説明する。図2に
おいて、a.薬品等で樹脂(基材)1の表面を粗すこと
で表面に凹凸を形成する方法、b.凹凸を形成した銅箔
を樹脂(基材)1の表面に貼り付けることで表面に凹凸
を形成する方法などにより、樹脂(基材)1の表面即ち
接触面に凸部11と凹部12を形成して銅鍍金を施して
銅箔(導体)2を形成し、形成された銅箔(導体)2の
表面に、作成する回路に対応するエッチングレジスト3
を配設してエッチングを施す。図3において、エッチン
グにより余分な銅箔を除去した後、エッチングレジスト
3を洗い流して必要な回路部分の銅箔(回路導体)21
を残して回路を形成する(以上、パネル鍍金法)。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention using a panel plating method will be described with reference to FIGS. In FIG. 2, a. A method for forming irregularities on the surface by roughening the surface of the resin (base material) 1 with a chemical or the like, b. The convex portion 11 and the concave portion 12 are formed on the surface of the resin (base material) 1, that is, the contact surface, by a method of forming irregularities on the surface of the resin (base material) 1 by pasting a copper foil on which the roughness is formed on the surface of the resin (base material) 1. Then, copper plating is performed to form a copper foil (conductor) 2, and an etching resist 3 corresponding to the circuit to be created is formed on the surface of the formed copper foil (conductor) 2.
Is provided and etching is performed. In FIG. 3, after removing the excess copper foil by etching, the etching resist 3 is washed away to remove the copper foil (circuit conductor) 21 of the required circuit portion.
A circuit is formed by leaving (the above is the panel plating method).
【0009】図4において、飛び出した銅箔(回路導
体)21の上面に表面が平滑な鏡板等の板材4を載せて
熱と圧力をかける、或いはプリント配線基板を挟み込ん
で熱と圧力をかけ、銅箔(回路導体)21を樹脂(基
材)1内に埋没させるとともに、樹脂(基材)1及び銅
箔(回路導体)21の上面を平滑にする(図1参照)。In FIG. 4, a plate material 4 such as a mirror plate having a smooth surface is placed on the upper surface of the protruding copper foil (circuit conductor) 21 to apply heat and pressure, or a printed wiring board is sandwiched to apply heat and pressure. The copper foil (circuit conductor) 21 is embedded in the resin (base material) 1, and the upper surfaces of the resin (base material) 1 and the copper foil (circuit conductor) 21 are made smooth (see FIG. 1).
【0010】この構成によると、樹脂(基材)に埋没し
た銅箔(回路導体)と樹脂(基材)との接触面積が増大
するために、接着(密着)強度が著しく増大する。特に
パネルエッチング法で形成された回路導体は、断面形が
台形状に末広がりであるため、回路導体を埋没させるこ
とで得られる接着(密着)強度向上の効果が大きいもの
である。さらに、銅箔(回路導体)が樹脂(基材)に埋
没しているため、ぶつかる、引っかける等の外的な物理
ストレスを受けにくくなり、導体と基材が剥離するとい
った不具合の発生を抑制することができる。According to this structure, the contact area between the copper foil (circuit conductor) buried in the resin (base material) and the resin (base material) increases, so that the adhesive strength is significantly increased. In particular, the circuit conductor formed by the panel etching method has a trapezoidal cross section, and thus has a great effect of improving the bonding strength obtained by burying the circuit conductor. Furthermore, since the copper foil (circuit conductor) is buried in the resin (base material), it is less likely to be subject to external physical stress such as bumping or catching, and the occurrence of problems such as separation of the conductor and the base material is suppressed. be able to.
【0011】図5乃至図9に基づいて、パターン鍍金法
を用いた本発明の第2実施例を説明する。図5におい
て、樹脂(基材)5の表面に凸部51と凹部52を形成
し、その表面に鍍金レジスト6を配置して銅鍍金を施し
た後、鍍金レジスト6を洗い流して飛び出した銅箔(回
路導体)7を形成し(図6参照)、銅鍍金層による回路
が形成される。A second embodiment of the present invention using the pattern plating method will be described with reference to FIGS. In FIG. 5, a convex portion 51 and a concave portion 52 are formed on the surface of a resin (base material) 5, a plating resist 6 is arranged on the surface, copper plating is performed, and then the plating resist 6 is washed off and popped out. (Circuit conductor) 7 is formed (see FIG. 6), and a circuit is formed by the copper plating layer.
【0012】図7において、飛び出した銅箔(回路導
体)7の外表面71,72に、化学的処理又は物理的処
理により1〜2μmの深さの微小な凹凸を設ける。図8
において、その後、銅箔(回路導体)7の上面に表面が
平滑な鏡板等の板材4を載せて熱と圧力をかける、或い
はプリント配線基板を挟み込んで熱と圧力をかけ、銅箔
(回路導体)7を樹脂(基材)5内に埋没させる(図9
参照)。In FIG. 7, the outer surfaces 71, 72 of the protruding copper foil (circuit conductor) 7 are provided with minute irregularities having a depth of 1 to 2 μm by chemical treatment or physical treatment. Figure 8
Then, a plate material 4 such as a mirror plate having a smooth surface is placed on the upper surface of the copper foil (circuit conductor) 7 to apply heat and pressure, or a printed wiring board is sandwiched to apply heat and pressure to the copper foil (circuit conductor). ) 7 is embedded in the resin (base material) 5 (see FIG. 9).
reference).
【0013】なお、パターン鍍金法によるものに限られ
ることなく、上記第1実施例のようにパネル鍍金法或い
はパネルエッチング法で形成した突出する銅箔(回路導
体)の外表面に、化学的処理又は物理的処理により1〜
2μmの深さの微小な凹凸を設けても良いものである。It is to be noted that the outer surface of the protruding copper foil (circuit conductor) formed by the panel plating method or the panel etching method as in the first embodiment is not limited to the pattern plating method but is chemically treated. Or 1 to 1 by physical treatment
Fine irregularities having a depth of 2 μm may be provided.
【0014】この構成によると、飛び出した銅箔(回路
導体)の外表面に微細な凹凸を設けることで、埋没した
銅箔(回路導体)と樹脂(基材)との接触面積が増大
し、接触(密着)強度を大きくすることができる。According to this structure, by providing fine irregularities on the outer surface of the protruding copper foil (circuit conductor), the contact area between the buried copper foil (circuit conductor) and the resin (base material) increases, The contact (adhesion) strength can be increased.
【0015】なお、上記第1、第2実施例においては、
基材の表面に飛び出して形成された回路導体を押圧・加
熱して基材内に完全に埋没させているが、回路導体の厚
さの半分(50パーセント)以上が基材内に埋没されて
いれば良いものである。回路導体の厚さの半分以上が基
材内に埋没することにより、押圧作業が簡単になって製
造工程を簡略化することができる。In the first and second embodiments described above,
The circuit conductor formed by projecting on the surface of the base material is pressed and heated to be completely embedded in the base material, but more than half (50%) of the thickness of the circuit conductor is embedded in the base material. It would be nice. By embedding more than half of the thickness of the circuit conductor in the base material, the pressing operation can be simplified and the manufacturing process can be simplified.
【0016】[0016]
【発明の効果】本発明は、上述のとおり構成されている
から次に述べる効果を奏する。請求項1のものは、基材
の表面に飛び出して回路導体を形成し、該回路導体を押
圧・加熱して基材内に埋没させたことにより、基材に埋
没した回路導体は、基材との接触面積が増大するため、
導体と基材との接着(密着)強度が著しく増大する。特
に、パネルエッチング法で形成された回路導体は、断面
形が台形状に末広がりとなるため、飛び出して形成され
た回路導体を埋没させることで得られる接着(密着)強
度向上の効果が大きいものである。さらに、回路導体が
基材に埋没しているため、ぶつかる、引っかける等の外
的な物理ストレスを受けにくくなり、導体と基材が剥離
するといった不具合の発生を抑制することができる。請
求項2のものは、基材の表面に飛び出して形成された回
路導体の外表面に微細な凹凸を設けることにより、埋没
した回路導体と基材との接触面積が増大し、接触(密
着)強度を大きくすることができる。Since the present invention is constructed as described above, it has the following effects. According to the first aspect of the present invention, a circuit conductor is formed by popping out on the surface of the base material, and the circuit conductor is pressed and heated to be embedded in the base material. Because the contact area with
The adhesive strength between the conductor and the base material is significantly increased. In particular, since the circuit conductor formed by the panel etching method has a trapezoidal cross section, it has a large effect of improving the adhesion (adhesion) strength obtained by burying the protruding circuit conductor. is there. Further, since the circuit conductor is buried in the base material, it becomes difficult to receive external physical stress such as bumping or catching, and it is possible to suppress the occurrence of defects such as separation of the conductor and the base material. According to a second aspect of the present invention, by providing fine irregularities on the outer surface of the circuit conductor formed by projecting on the surface of the base material, the contact area between the buried circuit conductor and the base material increases, and contact (adhesion) occurs. The strength can be increased.
【図1】本発明の第1実施例のプリント配線基板の断面
図である。FIG. 1 is a sectional view of a printed wiring board according to a first embodiment of the present invention.
【図2】本発明の第1実施例の製造工程説明図である。FIG. 2 is a drawing explaining the manufacturing process of the first embodiment of the present invention.
【図3】同じく本発明の第1実施例の製造工程説明図で
ある。FIG. 3 is also a manufacturing process explanatory view of the first embodiment of the present invention.
【図4】同じく本発明の第1実施例の製造工程説明図で
ある。FIG. 4 is also a manufacturing process explanatory diagram of the first embodiment of the present invention.
【図5】本発明の第2実施例の製造工程説明図である。FIG. 5 is a drawing explaining the manufacturing process of the second embodiment of the present invention.
【図6】同じく本発明の第2実施例の製造工程説明図で
ある。FIG. 6 is also a manufacturing process explanatory diagram of the second embodiment of the present invention.
【図7】同じく本発明の第2実施例の製造工程説明図で
ある。FIG. 7 is also a manufacturing process explanatory diagram of the second embodiment of the present invention.
【図8】同じく本発明の第2実施例の製造工程説明図で
ある。FIG. 8 is also a manufacturing process explanatory diagram of the second embodiment of the present invention.
【図9】本発明の第2実施例のプリント配線基板の断面
図である。FIG. 9 is a sectional view of a printed wiring board according to a second embodiment of the present invention.
【図10】微細化による接着強度の低下状況の一例を示
す表1である。FIG. 10 is Table 1 showing an example of a situation in which the adhesive strength is reduced due to miniaturization.
【図11】プリント配線基板の説明図である。FIG. 11 is an explanatory diagram of a printed wiring board.
1 樹脂(基材)、11 凸部、12 凹部、2 銅箔
(導体)
21 銅箔(回路導体)、3 エッチングレジスト、4
鏡板
5 樹脂(基材)、51 凸部、52 凹部、6 鍍金
レジスト
7 銅箔(回路導体)、71,72 (回路導体の)外
表面DESCRIPTION OF SYMBOLS 1 resin (base material), 11 convex part, 12 concave part, 2 copper foil (conductor) 21 copper foil (circuit conductor), 3 etching resist, 4
End plate 5 Resin (base material), 51 Convex part, 52 Concave part, 6 Plating resist 7 Copper foil (circuit conductor), 71, 72 (of circuit conductor) outer surface
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成14年1月16日(2002.1.1
6)[Submission Date] January 16, 2002 (2002.1.1
6)
【手続補正1】[Procedure Amendment 1]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図5[Name of item to be corrected] Figure 5
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図5】 [Figure 5]
───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E343 AA02 AA12 AA36 AA39 BB24 BB67 BB71 CC61 DD43 DD76 DD80 EE17 EE52 ER11 ER50 GG04 ─────────────────────────────────────────────────── ─── Continued front page F term (reference) 5E343 AA02 AA12 AA36 AA39 BB24 BB67 BB71 CC61 DD43 DD76 DD80 EE17 EE52 ER11 ER50 GG04
Claims (2)
たプリント配線基板において、基材の表面に飛び出した
回路導体を形成し、飛び出して形成された回路導体を押
圧・加熱して基材内に埋没させたことを特徴とするプリ
ント配線基板。1. A printed wiring board comprising a base material and a circuit conductor forming a circuit, wherein a circuit conductor protruding from the surface of the base material is formed, and the circuit conductor formed by pressing out is pressed and heated to form a base. A printed wiring board characterized by being buried in a material.
導体の外表面に微細な凹凸を設けることを特徴とする請
求項1記載のプリント配線基板。2. The printed wiring board according to claim 1, wherein fine irregularities are provided on the outer surface of the circuit conductor formed by projecting on the surface of the base material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002007035A JP2003209343A (en) | 2002-01-16 | 2002-01-16 | Printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002007035A JP2003209343A (en) | 2002-01-16 | 2002-01-16 | Printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2003209343A true JP2003209343A (en) | 2003-07-25 |
Family
ID=27645643
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002007035A Pending JP2003209343A (en) | 2002-01-16 | 2002-01-16 | Printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2003209343A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011100778A (en) * | 2009-11-04 | 2011-05-19 | Panasonic Electric Works Co Ltd | Circuit board, and semiconductor device mounted with component |
US8929092B2 (en) | 2009-10-30 | 2015-01-06 | Panasonic Corporation | Circuit board, and semiconductor device having component mounted on circuit board |
US9332642B2 (en) | 2009-10-30 | 2016-05-03 | Panasonic Corporation | Circuit board |
WO2018211991A1 (en) * | 2017-05-19 | 2018-11-22 | フリージア・マクロス株式会社 | Board for mounting electronic component, and manufacturing method therefor |
-
2002
- 2002-01-16 JP JP2002007035A patent/JP2003209343A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8929092B2 (en) | 2009-10-30 | 2015-01-06 | Panasonic Corporation | Circuit board, and semiconductor device having component mounted on circuit board |
US9332642B2 (en) | 2009-10-30 | 2016-05-03 | Panasonic Corporation | Circuit board |
US9351402B2 (en) | 2009-10-30 | 2016-05-24 | Panasonic Corporation | Circuit board, and semiconductor device having component mounted on circuit board |
JP2011100778A (en) * | 2009-11-04 | 2011-05-19 | Panasonic Electric Works Co Ltd | Circuit board, and semiconductor device mounted with component |
WO2018211991A1 (en) * | 2017-05-19 | 2018-11-22 | フリージア・マクロス株式会社 | Board for mounting electronic component, and manufacturing method therefor |
KR20200010363A (en) * | 2017-05-19 | 2020-01-30 | 베지 사사키 | Board for mounting electronic components and manufacturing method thereof |
CN110915307A (en) * | 2017-05-19 | 2020-03-24 | 佐佐木贝慈 | Substrate for mounting electronic component and method for manufacturing the same |
CN110915307B (en) * | 2017-05-19 | 2023-02-03 | 佐佐木贝慈 | Substrate for mounting electronic component and method for manufacturing the same |
KR102631808B1 (en) | 2017-05-19 | 2024-01-31 | 베지 사사키 | Substrate for mounting electronic components and manufacturing method thereof |
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