JP2003209131A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the difficulty of a prior art that in a conventional semiconductor device, three metal layers are formed on a pad electrode using a sputter method to cause resulting in high manufacturing costs. <P>SOLUTION: In a surface electrode structure of a semiconductor device formed on a semiconductor element 21, there is formed a four-layer metal structure of a Ti layer 31, an Ni layer 32, a Cu layer 33, and an Au layer 34 on an Al layer 30 of a pad electrode. The Ni layer 32 and the Cu layer 33 prevent a solder after mounting from invading, and hold joining strength with the solder. The Ti layer 31 and the Ni layer 32 are deposited by an electron impact heating deposition method, so that a low manufacturing cost is ensured. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface electrode structure of a semiconductor device, a structure for preventing erosion of solder in the electrode part, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, semiconductor devices and circuit devices have been required for downsizing, thinning, and weight saving because they are used in mobile phones, portable computers, and the like. Also in the semiconductor device and the circuit device using these elements, similarly, miniaturization, thinning, and weight reduction are required. Therefore, reducing the thickness of the surface electrode itself of the semiconductor device is also an issue. For example, as a conventional technique, Japanese Patent Laid-Open No. 10-32
One embodiment will be described below with reference to Japanese Patent Publication No. 208.

As shown in FIG. 7, in the conventional structure of a surface electrode of a semiconductor device, a pad electrode 3 made of, for example, aluminum is provided on an insulating film 2 on a semiconductor substrate 1. An insulating protective film 4 is formed on the insulating film 2 and the pad electrode 3 so that the opening 5 is arranged on the pad electrode 3. Then, a Ti film 6 and a Ni film 7 are continuously deposited on the pad electrode 3 exposed through the opening 5 of the insulating protection film 4, and the thicknesses of both are, for example, about 100 nm and 300 nm, respectively. is there. And Ni
A Pd film 8 is formed on the film 7 in consideration of solder wettability, and solder bumps 9 are formed on the Pd film 8. Here, the surface of the Ti film 6 on which the solder bumps are not formed is oxidized to form an oxide film 10.

Next, a method of manufacturing the above-mentioned semiconductor device will be described with reference to FIG.

First, as shown in FIG. 8A, a pad electrode 3 made of, for example, aluminum is formed on an insulating film 2 on a semiconductor substrate 1, for example. After that, an insulating protective film 4 is formed on the entire surface.
And the insulating protection film 4 on the pad electrode 3 is selectively etched to form an opening 5 on the pad electrode 3. Subsequently, a Ti film 6 having a film thickness of 100 nm, a Ni film 7 having a film thickness of 300 nm, and a Pd film 8 having a film thickness of 50 nm, for example, are successively deposited on the entire surface by a sputtering method. .

Next, as shown in FIG. 8B, a resist 11 is applied on the Pd film 8 and the resist 11 other than on the pad electrode 3 is removed by using a photolinography technique.

Next, as shown in FIG.
Using 1 as a mask, the Pd layer 8 and the Ni layer 7 are etched using a reverse aqua regia-based etching solution. The surface of the Ti film 6 is oxidized by this etching solution to form an oxide film 10.

After that, the resist 11 is removed and the Ti film 6 is removed.
Electroplating is performed using the as a cathode. Since the surface of the Ti film 6 is covered with the oxide film 10, solder is not formed during the electroplating. Solder is selectively deposited only on the Pd layer 8, that is, on the pad electrode 3. Through this step, the electrode structure of the semiconductor device shown in FIG. 7 is completed.

[0009]

As described above, in the surface electrode structure of the conventional semiconductor device, as described above, for example, the Ti film 6 is formed on the pad electrode 3 by the sputtering method.
The Ni film 7 was continuously deposited, and the thicknesses of both were, for example, about 100 nm and 300 nm, respectively.
The solder wettability is taken into consideration on the Ni film 7 to form Pd.
The film 8 was formed, and the solder bumps 9 were formed on the Pd film 8.

However, the Ti film 6, which is a refractory metal, and Ni
There is a problem that the manufacturing cost is high when the film 7 is deposited by the sputtering method. Therefore, the Ti film 6, N
When the i film 7 is deposited by the electron impact heating evaporation method to the same film thickness as the sputtering method, for example, as a semiconductor element, MOSFE
When T is used, there is a problem that the characteristic changes. Further, when the Ni film 7 is deposited by the electron impact heating vapor deposition method to a thickness that does not cause the characteristic change of the MOSFET, the Ni film 7 is eroded by the solder when the conductive member is mounted, and the solder bonding strength is obtained. There was a problem that there was not.

[0011]

The semiconductor device of the present invention is made in view of the above-mentioned circumstances, and a semiconductor device according to the present invention includes a pad electrode portion formed of an Al layer deposited on a semiconductor substrate, and the pad electrode portion. A second conductive metal layer deposited on the first conductive metal layer for the purpose of connection and a solder deposited on the first conductive metal layer for the purpose of bonding and erosion prevention. A conductive metal layer and a third conductive metal layer,
A fourth conductive metal layer for the purpose of wettability with the solder deposited on the third conductive metal layer.

The semiconductor device of the present invention is preferably characterized in that the second and third conductive metal layers are a combination of a Ni layer and a Cu layer.

Further, the semiconductor device of the present invention is preferably
The Cu layer is deposited thicker than the Ni layer.

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention comprises depositing an Al layer on a semiconductor substrate, depositing a SiN layer in a desired region on the Al film, and depositing the SiN layer. A step of removing a part to form an opening, exposing the Al film through the opening to form a pad electrode, and connecting the pad electrode to the pad electrode by electron impact heating evaporation method are performed. A step of depositing a desired first conductive metal layer, and a second conductive metal for the purpose of bonding to solder and preventing corrosion by electron impact heating vapor deposition on the first conductive metal layer A step of depositing a layer, a step of depositing a third conductive metal layer on the second conductive metal layer by resistance heating vapor deposition for the purpose of bonding to solder and preventing erosion, For wettability with solder on the conductive metal layer of Characterized by comprising the step of depositing a fourth conductive metal layer.

In the method for manufacturing a semiconductor device of the present invention, preferably, after forming a resist layer on the SiN layer, the first to fourth conductive metal layers are deposited using the resist layer as a mask. It is characterized by

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a semiconductor device according to the present invention will be described below with reference to FIGS.

The semiconductor device of the present invention has the first conductivity for the purpose of connecting the pad electrode portion formed of the Al layer deposited on the semiconductor substrate and the pad electrode deposited on the pad electrode portion. A second layer for the purpose of joining the metal layer and the solder deposited on the first conductive metal layer and for preventing erosion.
A conductive metal layer and a third conductive metal layer, and
And a fourth conductive metal layer for the purpose of wettability with the solder deposited on the conductive metal layer.

FIG. 1 is a perspective view of the semiconductor device according to the present invention. In the present embodiment, for example, a case where a MOSFET is used as the semiconductor element 21 will be described. Specifically, as shown, for example, a conductive paste (not shown) is formed on the island 27 of the Cu frame.
The semiconductor element 21 is fixed via the above. For example, a gate electrode 22 and a source electrode 24 are formed on the surface of the semiconductor element 21 inside the SiN layer 23 that covers the peripheral edge portion. On the source electrode 24 side, the source electrode 24 and Cu are formed by a conductive member made of a copper plate, for example.
The frame is electrically connected to the post 28. On the other hand, on the gate electrode 22 side, for example, the metal wire 26 electrically connects the gate electrode 22 and the post 29 of the Cu frame. Then, as will be described in detail later, a characteristic of the semiconductor device of the present invention is that the source electrode 24, which is a surface electrode of the semiconductor element 21, is formed in a multilayer metal layer structure.

Here, the gate electrode 22 side does not adopt a multi-layer metal structure, and the gate electrode 22 and the post 29 are electrically connected by a thin metal wire 26. However, like the gate electrode 22 side, a multi-layer metal structure is used. You may form with. Although not shown, a drain electrode is formed on the back surface of the semiconductor element 21 and is connected to the island 27 via a conductive paste or the like. Although only a part of the Cu frame is shown in FIG. 1, the island 27 and the posts 28,
A plurality of mounting portions 29 and 29 are formed on the same Cu frame having a plurality of patterns.

Next, as shown in FIG. 2, the surface electrode structure of the semiconductor element, which is a feature of the present invention, for example, the source electrode 24 in this embodiment will be described.

First, FIG. 2A shows an enlarged sectional view of the source electrode 24 of the semiconductor device shown in FIG. In the present embodiment, the source electrode 24 is formed on the surface of the semiconductor element 21, but it has the structure described below. On the surface of the semiconductor element 21, for example, an Al layer 30 forming a pad electrode is deposited. A plurality of metal layers are formed on the Al layer 30 to form the source electrode 24.
The iN layer 23 is formed. That is, the SiN layer 23 is deposited to prevent oxidation of the Al layer and improve the moisture resistance, but the source electrode 24 is formed in the first opening 38 formed by the SiN layer 23. And first, the first
As the first metal layer, the Al layer 30 in the first opening 38
Considering the adhesiveness with the Al layer 30 and the like, for example, T
The i layer 31 is deposited on the order of 50 to 150 Å. next,
As the second metal layer, on the Ti layer 31, the erosion prevention of the solder, the bondability with the solder, etc. are taken into consideration.
Layer 32 is deposited on the order of 150-250 liters. next,
As a third metal layer, a second metal layer is formed on the Ni layer 32.
Like the metal layer of No. 3, the corrosion resistance of the solder, the bondability with the solder, and the like are taken into consideration.
Å Accumulated. Finally, as the fourth metal layer, the wettability of the solder, the oxidation prevention of the Cu layer, etc. are considered on the Cu layer 33. For example, the Au layer 34 is 500 to 150.
About 0Å is deposited. Further, the fourth metal layer may be a Pd layer or a Pt layer.

Next, FIG. 2B is an enlarged cross-sectional view of the source electrode 24 of the semiconductor device shown in FIG. 1, as in the case of FIG. 2A. And, the difference from the structure of FIG. 2A is that, as the second metal layer, for example, a Cu layer 33 is deposited on the order of 1000 to 2000Å,
As the third metal layer, for example, the Ni layer 32 is 150
It is a point where about 250Å is deposited. Other structures are the same as those in the case of FIG.
The description is omitted here with reference to the description of (A).

Differences between the surface electrode structure in the semiconductor device of the present invention and the surface electrode structure in the conventional semiconductor device will be described. As shown in FIG. 7, in a conventional semiconductor device, for example, a three-layer metal film of a Ti film 6, a Ni film 7, and a Pd film 8 is continuously deposited on the pad electrode 3 by a sputtering method. The respective film thicknesses are, for example, about 100 nm for the Ti film 6 and 3 for the Ni film 7.
The Pd film 8 has a thickness of about 50 nm. on the other hand,
In the semiconductor device of the present invention, as described above, for example, the Ti layer 31, the Ni layer 32, the Cu layer 33, the A layer 30 are formed on the Al layer 30.
This is a structure in which four metal layers of the u layer 34 are deposited.
Then, as will be described later in detail in the manufacturing method, the Ti layer 31 and the Ni layer 32, which are refractory metals among the metal layers, are deposited by the electron impact heating vapor deposition method and formed into a thin film. That is,
The conventional method and the method of depositing a metal layer of a surface electrode according to the present invention are different from the sputtering method and the electron impact heating vapor deposition method.

FIG. 3 is a characteristic diagram of the vapor deposition time by the electron impact heating vapor deposition method and the threshold voltage Vth of the MOSFET. As can be seen from the figure, the threshold voltage Vth of the MOSFET also increases as the vapor deposition time increases, causing characteristic variations. For example, in the electron impact heating vapor deposition method, the threshold voltage Vth of the MOSFET before vapor deposition is
Is a reference value, the threshold voltage Vth is reached after 4t.
Is known to increase by approximately 150%.
From this, the Ti layer 3 is formed by the electron impact heating vapor deposition method.
1. When depositing the Ni layer 32, it is desirable to shorten the vapor deposition time, and the Ti layer 31 and the Ni layer 32 are formed as thin films as described above. On the other hand, as indicated by the one-dot chain line, when the metal layer is deposited by the resistance heating deposition method, M
It can be seen that the threshold voltage Vth of the OSFET is hardly affected.

FIG. 4 is a characteristic diagram showing the erosion state of the solder. Specifically, FIG. 4A is a characteristic diagram showing the erosion state of solder when a Ni layer is formed on the surface. On the other hand, FIG. 4B is a characteristic diagram showing the erosion state of the solder when the Cu layer is formed on the surface.

First, as shown in FIG. 4A, the surface layer is N
It is shown that the erosion rate of the solder is low in the case of the i layer. Specifically, a Pb layer shown by a straight line is formed on the surface portion, and the Ni layer shown by the alternate long and short dash line is also eroded by the solder to some extent.
A Ni layer having a high concentration is formed. In addition, S shown by the dotted line
As can be seen from the n layer, the Ni / Sn layer, which is an intermetallic compound of Sn and Ni layers, which are the constituent elements of the solder, is also only formed on the surface portion. That is, the Ni layer is a metal layer that is excellent in preventing corrosion of solder, and if it has a certain thickness, even a single layer can prevent corrosion of solder.

On the other hand, as shown in FIG. 4B, the surface layer is C
On the contrary, in the case of the u layer, it is shown that the solder erosion rate is high. Specifically, the Pb layer indicated by a straight line is formed on the surface portion, but it can be seen that the Pb layer further erodes deeper than in the case of the Ni layer. Even in the Cu layer shown by the chain double-dashed line, Ni
It can be seen that, unlike the case of the layer, the metal concentration is lowered even in the deep portion. That is, as can be seen from the Sn layer shown by the dotted line, it is understood that the Cu / Sn layer, which is an intermetallic compound of Sn which is a constituent element of the solder and the Cu layer, is formed to a deep portion of the Cu layer. That is, it is understood that the Cu layer has a high solder erosion rate, and it is difficult to prevent the solder erosion unless the Cu layer is a single layer and has a certain thickness.

3 and FIG. 4 are summarized below, particularly when a semiconductor element 21, such as a MOSFET, is used, which is liable to cause characteristic variations of the element when the electron impact heating evaporation method is used, Can be said. When the electron impact heating vapor deposition method is used, it is considered that the electrons at the time of use are caused by the above characteristic variation. Therefore, when the metal layer is formed on the surface of the semiconductor element 21 by the electron impact heating evaporation method, it is desirable to perform it in a short time in order to prevent the characteristic variation of the threshold voltage Vth of the MOSFET. Performing the electron impact heating vapor deposition method in a short time means that the Ni layer 32 for the purpose of preventing solder erosion is formed as a thin film. That is, it is known that the Ni layer has a slow solder erosion rate.
The Cu layer 33 is formed thick on the second layer. As a result, it is possible to realize a surface electrode structure capable of completely preventing solder erosion and suppressing fluctuations in element characteristics.

Specifically, FIG. 5 is a sectional view showing the surface electrode structure after mounting the conductive member 25. Figure 5 (A)
Corresponds to FIG. 2 (A) and corresponds to Ni as the second metal layer.
It is sectional drawing at the time of depositing the layer 32 and depositing the Cu layer 33 as a 3rd metal layer. As shown, the conductive member 2
After mounting 5, C is soldered to the line 36 marked with ×
Most of the u layer 33 is eroded. However, FIG.
As shown in (A), since the Cu layer 33 is thickly deposited by the resistance heating vapor deposition method, the Cu layer 33 prevents solder corrosion. Even if the Cu layer 33 is entirely eroded by the solder, the Ni layer 32 can prevent the solder from eroding. On the other hand, FIG. 5B corresponds to FIG. 2B, and a Cu layer 33 is deposited as a second metal layer,
It is sectional drawing at the time of depositing Ni layer 32 as a 3rd metal layer. As shown in the figure, after mounting the conductive member 25, ×
Solder up to the marked line 36 by soldering Ni layer 32 and C
Most of the u layer 33 is eroded. In this case MOS
In relation to the characteristic variation of the threshold voltage Vth of the FET, Ni
The layer 32 is formed as a thin film, and the Ni layer 32 is entirely eroded. However, as shown in FIG. 2B, C
Since the u layer 33 is thickly deposited by the resistance heating vapor deposition method, the Cu layer 33 prevents the corrosion of the solder.

As described above, in the semiconductor device of the present invention, the four metal layers 3 are formed on the pad electrode composed of the Al layer 30.
1-34 are deposited. The layer is characterized by having a two-layer structure of a Ni layer 32 and a Cu layer 33 for the purpose of preventing solder corrosion. That is, in the semiconductor device of the present invention, solder erosion can be completely prevented by the Ni layer 32 and the Cu layer 33. With that,
The Ni layer 32 and the Cu layer 33 can prevent solder erosion, and can realize a structure in which the surface electrode does not peel off after mounting.

Further, in the semiconductor device of the present invention, when a MOSFET is used as the semiconductor element 21, since the Ni layer 32 which is the second metal layer is deposited by the electron impact heating vapor deposition method, for example, it is deposited at about 150 to 250 Å. Has been done. That is, the layers for the purpose of preventing solder erosion are two layers of the Ni layer 32 and the Cu layer 33. With that, MO
It is possible to realize a structure that prevents corrosion of the solder even if the Ni layer is a thin film, without causing the characteristics of the SFET 21, particularly the characteristics of the threshold voltage Vth, to fluctuate.

Further, in the semiconductor device of the present invention, the conductive member 25 is used as a connecting means for connecting the source electrode 24 and the post 28. Therefore, compared with the case where a large number of thin metal wires are connected, it is possible to deal with a semiconductor element having a high current density by having this electrode structure.

Although the structure in this embodiment has been described using a MOSFET as a semiconductor element, it is not particularly limited, and the same effect can be obtained for other semiconductor elements forming a surface electrode. . Further, not only the front surface electrode structure but also the back surface electrode structure can be applied.

Next, with reference to FIG. 6, a method of manufacturing the semiconductor device of the present invention will be described. Then, similarly to the description of the semiconductor device, a method of manufacturing the source electrode 24 structure will be described below. Note that the same drawings and reference numerals used in the above description of the semiconductor device are also used in the description of the present manufacturing method.

First, as shown in FIG. 6A, an Al layer 30, for example, which constitutes a pad electrode is deposited on the surface of the semiconductor element 21. Next, the SiN layer 23 is formed on the Al layer 30 in consideration of the oxidation resistance and the moisture resistance of the Al layer 30.
However, for example, a thickness of about 6000 Å to 8000 Å is deposited by a CVD method at 800 ° C. for about 2 hours. Then, in order to form the multilayer metal layer 41 for the source electrode 24, a resist 39 is deposited on the SiN layer 23 other than the region where the source electrode 24 is formed. Then, the SiN layer 23 on the source electrode 24 formation region is removed using the resist 39 as a mask by a known photolithography technique. At this time, the SiN layer 23 is removed more than the resist 39, and the end portion of the resist 39 is formed as if the eaves were provided to the SiN layer 23. Then, a second opening 42 is formed by the resist 39 inside the first opening 38 made of the SiN layer 23. As a result, FIG.
The structure shown in (A) is obtained.

Next, as shown in FIG. 6B, a multilayer metal layer 41 is formed in the source electrode 24 forming region through the second opening 42 made of the resist 39 by the lift-off method. First, as shown in FIG. 2 (A), as a first metal layer on the Al layer 30, considering the adhesiveness with the Al layer 30, etc., for example, a Ti layer 31 of about 50 to 150 Å It is deposited by the impact heating vapor deposition method. Next, as a second metal layer, for example, a Ni layer 32 of 150 to 2 is formed on the Ti layer 31 in consideration of solder erosion prevention, bondability with the solder, and the like.
About 50Å is deposited by the electron impact heating vapor deposition method. Next, as the third metal layer, on the Ni layer 32,
Similar to the second metal layer, the Cu layer 33 is, for example, 1000 to 200 in consideration of erosion prevention of solder, bondability with solder, and the like.
Deposit about 0Å by the resistance heating evaporation method. Finally, as the fourth metal layer, for example, the Au layer 34 is provided on the Cu layer 33 in consideration of the wettability of the solder, the oxidation prevention of the Cu layer, and the like.
About 500 to 1500 Å by resistance heating vapor deposition. Further, the fourth metal layer may be a Pd layer or a Pt layer.

Further, as shown in FIG. 2B, as the second metal layer, for example, a Cu layer 33 of 1000 to 200 is used.
Deposit about 0Å by the resistance heating evaporation method. After that, as the third metal layer, for example, the Ni layer 32 is 150 to
About 250 Å may be deposited by the electron impact heating vapor deposition method. The effect of forming such a structure is as described above in the description of the semiconductor device. The SiN layer 23
Is formed, for example, with a thickness of about 7,000 Å. As a result, the structure shown in FIG. 6B is obtained.

Next, as shown in FIG. 6C, the resist 3
The multilayer metal layer 41 and the resist 39 deposited on 9 are removed. As a result, the structure shown in FIG. 6C is obtained. After that, the semiconductor element 21 is mounted on the island 27 of the Cu frame. Then, the solder is supplied onto the source electrode 24 and fixed to the conductive member 25, and the structure shown in FIG. 1 is obtained.

As described above, in the method for manufacturing a semiconductor device of the present invention, the Ti layer and the Ni layer are deposited by the electron impact heating vapor deposition method instead of the conventional sputtering method.
The manufacturing cost can be reduced. Further, since the Cu layer is deposited by the resistance heating vapor deposition method, the layer thickness can be deposited to a desired thickness, thus preventing corrosion of the solder. As a result, it is possible to provide a semiconductor device having excellent solder joint strength and excellent product quality.

Further, according to the method of manufacturing a semiconductor device of the present invention, since the wireless structure can be realized on the source electrode 24, it can be applied to a semiconductor element having a high current density. Furthermore, since the source electrode 24 and the conductive member 25 are connected by soldering, it is possible to mount without impact as compared with the case of wire bonding.

In this embodiment, the case where the multi-layer metal layer is formed only on the source electrode side has been described, but there is no particular limitation, and a similar structure can be formed on the gate electrode side. . Further, in the above-described manufacturing method, the manufacturing method by the lift-off method has been described, but the same effect can be obtained by the ion milling method. In addition, various modifications can be made without departing from the scope of the present invention.

[0042]

As described above, in the semiconductor device of the present invention, for example, a Ti layer, a
That is, four metal layers including a Ni layer, a Cu layer, and an Au layer are deposited. In particular, it is characterized by having a two-layer structure of a Ni layer and a Cu layer as a layer for the purpose of preventing corrosion of solder. In other words, the Ni layer and the Cu layer can completely prevent the solder from eroding, and can realize a structure in which the surface electrode does not peel off after mounting.

Further, in the semiconductor device of the present invention, when a MOSFET is used as a semiconductor element, a Ti layer and Ni are used.
The electron impact heating vapor deposition method for depositing layers causes characteristic variations in the threshold voltage Vth of the MOSFET. Therefore, since the Ni layer is formed into a thin film, it may be eroded by the solder. However, according to the present invention, by implementing the solder erosion preventive structure with the two layers of the Ni layer and the Cu layer, it is possible to realize the structure in which the characteristic variation of the threshold voltage Vth of the MOSFET is not caused.

According to the method for manufacturing a semiconductor device of the present invention, the Ti layer and the Ni layer are deposited by the electron impact heating vapor deposition method instead of the conventional sputtering method, so that the manufacturing cost can be reduced. Further, since the Cu layer is deposited by the resistance heating vapor deposition method, the layer thickness can be deposited to a desired thickness. As a result, it is possible to provide a semiconductor device that prevents solder erosion, secures the bonding strength with the solder, and has excellent product quality.

[Brief description of drawings]

FIG. 1 is a perspective view for explaining a semiconductor device of the present invention.

FIG. 2 is a sectional view for explaining a surface electrode structure of a semiconductor device of the present invention.

FIG. 3 is a characteristic diagram showing characteristics of a semiconductor element used in the semiconductor device of the present invention.

FIG. 4 is a characteristic diagram showing an erosion state of a metal layer and a solder used in the semiconductor device of the present invention.

FIG. 5 is a cross-sectional view illustrating a semiconductor device of the present invention.

FIG. 6 is a cross-sectional view for explaining the method for manufacturing a semiconductor device of the present invention.

FIG. 7 is a cross-sectional view illustrating a conventional semiconductor device.

FIG. 8 is a cross-sectional view for explaining the conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

21 Semiconductor element 22 Gate electrode 23 Silicon oxide film 24 Source electrode 25 Conductive member 26 thin metal wires 27 islands 28, 29 post

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hisashi Tominaga             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. (72) Inventor Hirotoshi Kubo             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. F-term (reference) 5F033 HH07 HH08 HH11 HH13 HH18                       MM08 MM13 PP19 QQ09 QQ14                       QQ33 QQ41 RR06 SS11 VV07                       XX12 XX28 XX34                 5F044 RR00

Claims (13)

[Claims] 1. A pad electrode section made of an Al layer deposited on a semiconductor substrate, a first conductive metal layer for the purpose of connecting the pad electrode section deposited on the pad electrode section, and A second conductive metal layer and a third conductive metal layer for the purpose of bonding with a solder deposited on the first conductive metal layer and preventing erosion; and on the third conductive metal layer A semiconductor device comprising a fourth conductive metal layer for the purpose of wettability with the deposited solder. 2. The second and third conductive metal layers are N
The semiconductor device according to claim 1, wherein the semiconductor device is a combination of an i layer and a Cu layer. 3. The semiconductor device according to claim 2, wherein the Cu layer is deposited thicker than the Ni layer. 4. The semiconductor device according to claim 1, wherein the first conductive metal layer is a Ti layer. 5. The fourth conductive metal layer is an Au layer, Pd
The semiconductor device according to claim 1, wherein the semiconductor device comprises either a layer or a Pt layer. 6. An Al layer is deposited on a semiconductor substrate to form the Al layer.
Depositing a SiN layer on a desired region of the film, removing a part of the SiN layer to form an opening, and exposing the Al film through the opening to form a pad electrode; Depositing a first conductive metal layer on the electrode by electron impact heating vapor deposition for the purpose of connecting to the pad electrode, and soldering on the first conductive metal layer by electron impact heating vapor deposition And a step of depositing a second conductive metal layer for the purpose of bonding property with erosion and erosion prevention, and the purpose of bonding property with solder and erosion prevention by resistance heating vapor deposition on the second conductive metal layer. And a step of depositing a fourth conductive metal layer for the purpose of wettability with solder on the third conductive metal layer. A method for manufacturing a characteristic semiconductor device. 7. The semiconductor device according to claim 6, wherein after forming a resist layer on the SiN layer, the first to fourth conductive metal layers are deposited using the resist layer as a mask. Manufacturing method. 8. The method of manufacturing a semiconductor device according to claim 6, wherein the second conductive metal layer is a Ni layer, and the third conductive metal layer is a Cu layer. Method. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the Cu layer is deposited thicker than the Ni layer. 10. An Al layer is deposited on a semiconductor substrate,
l deposit a SiN layer on the desired region on the
Removing a part of the layer to form an opening, exposing the Al film through the opening to form a pad electrode, and connecting the pad electrode to the pad electrode by electron impact heating vapor deposition A step of depositing a first conductive metal layer for the purpose of improving the conductivity, and a second conductivity for the purpose of preventing erosion and bonding with solder by resistance heating vapor deposition on the first conductive metal layer. Depositing a metal layer, depositing a third conductive metal layer on the second conductive metal layer by electron impact heating vapor deposition for the purpose of bonding with solder and preventing erosion, And a step of depositing a fourth conductive metal layer on the third conductive metal layer for the purpose of wettability with solder, the method for manufacturing a semiconductor device. 11. The semiconductor device according to claim 10, wherein after forming a resist layer on the SiN layer, the first to fourth conductive metal layers are deposited using the resist layer as a mask. Manufacturing method. 12. The manufacturing of a semiconductor device according to claim 10, wherein the second conductive metal layer is a Cu layer and the third conductive metal layer is a Ni layer. Method. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the Cu layer is deposited thicker than the Ni layer.