JP2003209050A - Substrate treatment method and substrate treatment apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate treatment method and apparatus which can control accurately the line width of a resist pattern formed on a substrate and can improve the uniformity of the line width of the entire part of a substrate or on a substrate surface. <P>SOLUTION: The temperature of heat treatment is considered as a parameter which may give a maximum influence on the variation of line width, but is has also been proved that the higher the temperature of heat treatment is, the smaller the line width is by paying particular attention to the temperature of heat treatment before development. Accordingly, the line width can be controlled precisely and the predetermined resist pattern can be obtained by measuring the line width of the resist pattern after the development and then controlling the temperature of heat treatment, based on the result of the measurement, for example, by raising the temperature of heat treatment when the line width is smaller than a predetermined width. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate processing method and a substrate processing apparatus for forming a desired resist pattern on a semiconductor substrate in manufacturing a semiconductor device, particularly in a photolithography process.

[0002]

2. Description of the Related Art In a photolithography process in the manufacture of semiconductor devices, a resist film is formed on the surface of a semiconductor wafer (hereinafter referred to as "wafer"), which is then exposed to a predetermined pattern and further developed. As a result, a desired resist pattern is formed.

Conventionally, such a photolithography process includes a resist coating processing unit for rotating a wafer to apply a resist solution by centrifugal force, a developing processing unit for supplying a developing solution to a wafer and performing a developing process. It is carried out by the coating / developing apparatus and the exposure apparatus which is continuously provided integrally with the apparatus. In addition, such a coating and developing treatment apparatus, for example, after forming a resist film,
Alternatively, it has a heating processing unit and a cooling processing unit that perform thermal processing such as heating processing and cooling processing on the wafer before and after the development processing, and further, a transfer robot that transfers the wafer between these processing units. And so on.

By the way, in recent years, the miniaturization of the resist pattern has been further advanced, and for example, the line width of the resist pattern is required to be controlled more precisely. In particular, the uniformity of the line width for each substrate or the uniformity of the line width within the wafer has become an important issue. In order to solve such a problem, in the coating and developing treatment apparatus, for example, the processing temperature in the heat treatment unit or the cooling treatment unit, which may affect variations in the line width and the resist film thickness, the development time in the development treatment Etc. are strictly managed for each unit.

[0005]

However, even under such strict control of each unit, it is becoming difficult to precisely control the line width which tends to be extremely miniaturized. Further, in particular, in the heat treatment, it is known that the heat treatment temperature and the line width have an inversely proportional correlation, so that the heat treatment temperature is precisely controlled to be constant. Although the line width is precisely controlled by the above, under the present circumstances, even under such precise temperature control, the line width varies for each substrate or within the substrate surface.

In view of the above circumstances, an object of the present invention is to precisely control the line width of a resist pattern formed on a substrate and to improve the uniformity of the line width for each substrate or within the plane of the substrate. It is an object of the present invention to provide a substrate processing method and a substrate processing apparatus capable of performing the same.

[0007]

In order to achieve the above-mentioned object, the substrate processing method according to the present invention comprises performing a heat treatment on a substrate after forming a resist film on the substrate and then performing a developing treatment. The substrate processing method for forming a resist pattern includes the steps of recognizing the shape of the resist pattern formed after the development processing, and controlling the temperature of the heat treatment based on the recognition result.

In the present invention, the shape of the resist pattern is concerned with, for example, the line width, and the temperature of the heat treatment is mentioned as one of the parameters that may most affect the fluctuation of the line width. Focus on temperature. The higher the heating temperature, the smaller the line width tends to be. Therefore, for example, the line width of the resist pattern after development is recognized, and based on the recognition result, for example, if the line width is smaller than a predetermined value, the heating temperature is raised above a predetermined value, and the line width is precisely controlled It is possible to obtain a desired resist pattern.

According to one aspect of the present invention, the heat treatment is performed by placing a substrate on a hot plate, and the control of the heat treatment temperature controls the temperature of the hot plate. As described above, as a method of controlling the heating temperature, the temperature can be easily controlled by mounting the substrate and controlling, for example, a hot plate having a heater or the like capable of adjusting the heating temperature.

According to one aspect of the present invention, the step of controlling the heat treatment temperature includes the step of controlling the temperature in the hot plate surface based on the distribution of the resist pattern shape in the substrate surface. In this way, by controlling the heating temperature distribution in the hot plate surface based on, for example, the distribution of the line width in the substrate surface,
It is possible to suppress variations in the line width and the like within the substrate surface and improve the uniformity. The heating temperature control in the hot plate surface can be performed by, for example, preparing a plurality of the above-mentioned heaters in the hot plate, and controlling these heaters so that the respective temperatures are different in the hot plate surface.

According to one aspect of the present invention, the recognition of the resist pattern shape is performed by an optical observation device. When the resist pattern is recognized using an electron microscope, the resist pattern may be contracted due to the influence of the electron beam. However, by using the optical observation apparatus as in the present invention, such a problem occurs. It is possible to measure the line width non-destructively without causing it. As a result, the line width of the actual resist pattern can be measured accurately, which contributes to the accurate formation of the resist pattern.

According to one aspect of the present invention, the recognition of the resist pattern shape by the optical observation device is performed at multiple points in the plane of the substrate. By thus recognizing the resist pattern at multiple points on the substrate surface, it becomes possible to more accurately control the line width and the like. Also, 10
It is preferable to perform multi-point recognition at 0 to 20000 points. As described above, even with multi-point recognition of more than 10,000 points, by using the optical observation device, processing can be performed much faster than when an electron microscope is used, and high throughput can be achieved.

According to an aspect of the present invention, a step of providing a plurality of the heat plates, performing heat treatment on a plurality of substrates on each of the plurality of heat plates, and controlling the heat treatment temperature of each of the plurality of heat plates. including. As a result, high throughput can be achieved, and even when a plurality of hot plates are provided for processing as described above, it is possible to suppress variations in line width and the like that occur between the hot plates.

A substrate processing apparatus according to the present invention comprises a heat treatment means for performing heat treatment on a substrate having a resist film formed thereon before the development treatment, and means for recognizing the shape of a resist pattern formed after the development treatment. Means for controlling the temperature of the heat treatment based on the recognition result.

The substrate processing apparatus according to the present invention includes a plurality of heat treatment units for performing heat treatment on a plurality of substrates on which a resist film is formed before development processing, and a conveyance for carrying the substrates to the plurality of heat treatment units. A mechanism, means for recognizing the shape of the resist pattern formed after the development processing for each of the plurality of substrates, and means for controlling the temperature of each heat treatment for each of the plurality of heat treatment units based on the recognition result.

Further features and advantages of the present invention will become more apparent with reference to the accompanying drawings and the description of the embodiments of the invention.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1 to 3 are views showing the overall structure of a coating and developing treatment apparatus according to the first embodiment of the present invention.
Is a plan view thereof, and FIGS. 2 and 3 are a front view and a rear view of the coating and developing treatment apparatus.

In the coating and developing treatment apparatus 1, a plurality of semiconductor wafers W as substrates to be treated are transferred into or out of the apparatus 1 from the outside in units of a plurality of wafer cassettes CR, for example, 25 wafers. Cassette station 10 for loading and unloading wafers W
Further, a processing station 12 in which various single-wafer processing units that perform a predetermined process on the wafer W one by one in the coating and developing process are arranged in multiple stages at predetermined positions, and is provided adjacent to the processing station 12. The interface unit 14 for transferring the wafer W to and from the exposure apparatus 100 is integrally connected.

In the cassette station 10, as shown in FIG. 1, a plurality of wafer cassettes CR, for example, five wafer cassettes CR are located at the positions of the projections 20a on the cassette mounting table 20, with their respective wafer entrances / outlets facing the processing station 12 side in the X direction. The wafer carriers 22 placed in a row and movable in the cassette arrangement direction (X direction) and in the wafer arrangement direction (Z direction) of the wafers stored in the wafer cassette CR selectively access each wafer cassette CR. It is like this.
Further, the wafer carrier 22 is configured to be rotatable in the θ direction so that it can also access a heat treatment system unit belonging to the third processing unit section G3 having a multi-stage configuration described later as shown in FIG. It has become.

As shown in FIG. 1, the processing station 12
The third processing unit section G3, the fourth processing unit section G4, and the fifth processing unit section G5 are arranged from the cassette station 10 side on the rear side of the apparatus (upper side in the drawing). Unit part G3 and 4th
The first main wafer transfer device A1 is provided between the first main wafer transfer device A1 and the processing unit part G4. As will be described later, in the first main wafer transfer device A1, the first main wafer transfer body 16 includes a first processing unit section G1, a third processing unit section G3, a fourth processing unit section G4, and the like. Are installed to allow selective access to. Further, a second main wafer transfer apparatus A2 is provided between the fourth processing unit section G4 and the fifth processing unit section G5, and the second main wafer transfer apparatus A2 is the same as the first main wafer transfer apparatus A2. The second main wafer carrier 17 is installed so as to selectively access the second processing unit section G2, the fourth processing unit section G4, the fifth processing unit section G5, and the like.

Further, a heat treatment system unit is installed on the back side of the first main wafer transfer device A1. For example, an adhesion unit (AD) 110 for hydrophobizing the wafer W and the wafer W are heated. Heating unit (H
As shown in FIG. 3, P) 113 are stacked in two steps in order from the bottom. In addition, the adhesion unit (AD)
May further include a mechanism for controlling the temperature of the wafer W. On the back side of the second main wafer transfer device A2, there is a peripheral exposure device (W that selectively exposes only the edge portion of the wafer W).
EE) 120, a film thickness inspection device 119 for inspecting the resist film thickness applied to the wafer W, and an optical observation device (OCD) 40 according to the present invention are provided in multiple stages.

The optical observation device 40 is for recognizing a resist pattern by, for example, diffraction and interference of light, pattern-matches with a calculation pattern (library), and makes the coincident calculation pattern an actual pattern. It is a thing. The observation data obtained by the optical observation device 40 is sent to the control unit 60 for each of a plurality of substrates, and the control unit 60 uses the post exposure baking unit (PEB) based on these data as described later. ) Is controlled. The second
The rear side of the main wafer transfer apparatus A2 is similar to the back side of the first main wafer transfer apparatus A1 in the heat treatment unit (HP) 1
13 may be arranged.

As shown in FIG. 3, in the third processing unit section G3, an oven type processing unit for carrying out a predetermined processing by placing the wafer W on a mounting table, for example, a high temperature for carrying out a predetermined heating processing on the wafer W A heating processing unit (BAKE), a cooling processing unit (CPL) for performing cooling processing on the wafer W with accurate temperature control, and a transition unit (transfer unit for transferring the wafer W from the wafer carrier 22 to the main wafer carrier 16). TRS), and a transfer / cooling processing unit (TCP), which is separately arranged in the upper and lower two stages of the transfer part and the cooling part, is stacked in order from the top, for example, in ten stages. In the third processing unit section G3,
In this embodiment, the third stage from the bottom is provided as a spare space. Also in the fourth processing unit section G4, for example, a post-baking unit (POST), a transition unit (TRS) that serves as a wafer transfer section, a pre-baking unit (PAB) that heat-treats the wafer W after the resist film formation, and a cooling processing unit. (CPL) are stacked, for example, in 10 steps from the top. Further, in the fifth processing unit section G5, for example, as a heat treatment unit according to the present invention, a post exposure baking unit (PEB) for performing a heat treatment on the exposed wafer W,
For example, a cooling processing unit (CPL) and a transition unit (TRS) that serves as a transfer unit for the wafer W are stacked in 10 stages in order from the top. In this embodiment, five post-exposure baking units (PEB) are provided, and PEB to PEB are arranged in order from the top.

In FIG. 1, a first processing unit section G1 and a second processing unit section G2 are provided side by side in the Y direction on the front side (lower side in the figure) of the processing station 12. Between the first processing unit section G1 and the cassette station 10 and between the second processing unit section G2 and the interface section 14, as shown in FIG. 2, the respective processing unit sections G1 and G2 supply. Liquid temperature control pumps 24 and 25 used for temperature control of the processing liquid are provided respectively, and further, clean air from an air conditioner (not shown) provided outside the coating and developing processing apparatus 1 is supplied to each processing unit section. G
1 to G5 are provided with ducts 31 and 32 for supplying the inside.

As shown in FIG. 2, in the first processing unit section G1, five spinner type processing units for carrying out predetermined processing by placing the wafer W on the spin chuck in the cup CP,
For example, a resist coating processing unit (COT) that forms a resist film on a wafer has three stages, and a bottom coating unit (BARC) that forms an antireflection film to prevent reflection of light at the time of exposure has two stages from below. They are stacked in five steps in order. Similarly, in the second processing unit section G2, five spinner type processing units, for example, development processing units (DEV) are stacked in five stages. In the resist coating processing unit (COT), draining of the resist solution is troublesome both mechanically and in terms of maintenance. Therefore, it is preferable to arrange the resist solution in the lower stage. However, it is also possible to arrange them in the upper stage if necessary.

Further, the first and second processing unit sections G1
At the bottom of G2 and G2, there are processing unit sections G1 and G2.
The chemical chamber (CH
M) 26 and 27 are provided respectively.

A portable pickup cassette CR and a stationary buffer cassette BR are arranged in two stages on the front surface of the interface section 14, and the wafer carrier 2 is arranged in the central portion.
7 is provided. This wafer carrier 27 is composed of X, Z
By moving in the direction, both cassettes CR and BR can be accessed. Further, the wafer carrier 27 is configured to be rotatable in the θ direction so that it can also access the fifth processing unit section G5. Further, as shown in FIG. 3, a plurality of high-precision cooling processing units (CPL) are provided on the back surface of the interface section 14, for example, two upper and lower stages. The wafer transfer body 27 can also access this cooling processing unit (CPL).

FIG. 4 is a perspective view showing the first main wafer transfer device A1. Since the second main wafer transfer device A2 is the same as the first main wafer transfer device A1, its description is omitted.

As shown in FIG. 1, the main wafer transfer device A1
Is surrounded by the housing 41 to prevent particles from entering. In FIG. 4, the illustration of the housing 41 is partially omitted for clarity of explanation.

As shown in FIG. 4, poles 33 are vertically provided at both ends of the main wafer transfer device A1, and the main wafer transfer body 16 (17) extends vertically (Z direction) along the poles 33. It is arranged to be movable. The wafer W is held on the carrier base 55 of the main wafer carrier 16 3
Two tweezers 7a to 7c are provided, and these tweezers 7a to 7c are configured to be movable in the horizontal direction by a drive mechanism (not shown) built in the transport base 55. Below the transport base 55, a support member 45 that supports the transport base 55 is provided with a rotating member 46 that is rotatable in the θ direction.
Connected through. As a result, the wafer carrier 1
6 is rotatable in the θ direction. A flange portion 45a is formed on the support body 45, and the flange portion 45a is slidably engaged with a groove 33a provided in the pole 33, and is slidable by a belt drive mechanism incorporated in the pole 33. It is provided. As a result, the main wafer carrier 16 can move vertically along the pole 33.

At the bottom of the main wafer transfer device A1,
For example, four fans 36 for controlling the atmospheric pressure and temperature / humidity inside the transport device A1 are provided.

FIG. 5 is a conceptual block diagram of the optical observation device 40. The optical observation device 40 includes an optical system 61 indicated by a broken line. The optical system 61 is arranged so as to reflect, for example, a xenon lamp 62 that emits white light and the light from the xenon lamp 62 in a downward right direction. The half mirror 56, the lens 54 that guides the light reflected by the half mirror 56 to the resist pattern formed on the surface of the wafer W, and the detector 57 that detects the reflected diffracted light from the wafer W. Further, the optical observation device 40 is provided with a stage 53 on which the wafer W is placed, and is also connected with a processing unit 11 for processing the detection result of the detector 57. The optical system 61 is configured to be movable in a direction parallel to the surface direction of the wafer W (X-Y direction) by a drive mechanism (not shown), and irradiates light on each chip formed on the wafer W for observation. You can do it.

The processing section 11 derives, by calculation (simulation), a diffraction pattern corresponding to the detection result 35 by the detector 57 and the state of the resist pattern (for example, line width, pitch between patterns, height, etc.). The calculation unit 59, the storage unit 58 that stores the plurality of diffraction patterns derived by the calculation unit 59, the detection result 35, and the plurality of diffraction patterns stored in the storage unit 58 are compared, and the comparison is performed. Of the plurality of diffraction patterns, one diffraction pattern corresponding to the detection result 35 is stored in the storage unit 5 as the measurement result.
8 and the analysis part 52 which extracts from 8. As a result, the optical observation device 40 detects the detection result 35 and the storage unit 5.
It is possible to perform pattern matching with the calculated pattern (library) stored in 8, and regard the matched calculated pattern as an actual pattern. As a more specific example, in the present embodiment, for example, scatterometry (Sc
The pattern matching is performed by the technique of “atterometry”.

6 and 7 are a plan view and a sectional view of a post exposure baking unit (PEB) according to the present invention. PEB to PEB have the same configuration. In addition, the pre-baking unit (PAB) and the post-baking unit (POST), which are other heat-treating system units, have substantially the same configuration as the post-exposure baking unit (PEB).

As shown in FIG. 6, these units are surrounded by a casing 75, and the wafer W is under control of the temperature controller 34 on the back side in the processing chamber 30.
Is provided and a heating plate 86 for performing heat treatment at, for example, 70 ° C. to 150 ° C. is provided, and on the front side, a temperature control plate 71 for mounting the wafer W and controlling the temperature is provided.

The heating plate 86 is supported by a supporting body 88, and elevating pins 85 for supporting the wafer W from the lower portion of the supporting body 88 are provided so as to be able to move up and down by an elevating cylinder 82. Further, a cover member (not shown) that covers the heating plate 86 at the time of heat treatment is arranged above the heating plate 86.

As the temperature adjusting mechanism of the temperature adjusting plate 71, for example, cooling water, a Peltier element, or the like is used and the wafer W
Is controlled to a predetermined temperature, for example, around 40 ° C. to perform temperature control. This temperature control plate 7
6, the notch 71a is formed as shown in FIG. 6, and the elevating pin 84 buried under the temperature control plate 71 can be projected and retracted from the surface of the temperature control plate by the elevating cylinder 81. . Also, this temperature control plate 7
1 can be moved along the rail 77 by, for example, a motor 79a, so that the wafer is transferred to the heating plate 86 while the temperature of the wafer is adjusted.

The post-exposure baking unit (PEB) is also provided with an air flow passage 75c for controlling the atmospheric pressure.
The air from is introduced into the processing chamber 30 via the fan 87a. Further, the air inside the processing chamber 30 is exhausted from the exhaust port 75d by the fans 87b provided on both wall surfaces.

Further, on one side surface portion of the temperature control plate side 71 of the casing 75, for example, a fourth processing unit section G4
With regard to the above, an opening 75a is provided in order to transfer the wafer W to and from the first main wafer transfer device A1, and the other side surface part is provided with the second main wafer transfer device A2 side. An opening 75b is provided so as to face the opening. A shutter 76 that can be opened and closed by a drive unit (not shown) is provided in each of the openings 75a and 75b.
a and 76b are provided.

Although not shown, the cooling processing unit (CPL) has a cooling plate on which, for example, a wafer W is placed and which is subjected to cooling processing at about 23 ° C. for each heat-treated wafer. As the cooling mechanism, for example, cooling water or a Peltier element is used.

FIG. 8 shows a control system for PEB to PEB. The control unit 60 stores the line width data of the plurality of substrates obtained by the line width measurement of the optical observation device 40. Figure 8
In, the respective heating plates in PEB to PEB are represented by reference numerals 86 to 86. As shown in the drawing, the heating plate 86 has nine heaters 91 to 99 made of, for example, nichrome wire or the like built therein.
The heating temperature of each 99 is controlled independently and independently by the temperature controller 34a. The heating plates 86 to 86 in the other PEBs to PEBs are similarly controlled by the temperature controllers 34b to 34e.

Next, a series of processing steps of the coating and developing processing apparatus 1 described above will be described with reference to the flow shown in FIG.

First, in the cassette station 10, the wafer carrier 22 accesses the cassette CR which contains the unprocessed wafer W on the cassette mounting table 20, and takes out one wafer W from the cassette CR.
Then, the wafer W is then transferred to the first main wafer transfer device A1 via the transfer / cooling processing unit (TCP) and transferred to the bottom coating unit (BARC). Then, here, an antireflection film is formed to prevent reflection of exposure light from the wafer during exposure (step 1).

Next, the wafer W is transferred to the baking processing unit in the third processing unit section G3 and subjected to a predetermined heat treatment at 120 ° C. (step 2),
After a predetermined cooling process is performed in the cooling process unit (CPL) (step 3), a desired resist film is formed on the wafer W in the resist coating process unit (COT) (step 4).

When the resist film is formed, the wafer W is transferred to the pre-baking unit (PAB) by the first main wafer transfer device A1 and subjected to predetermined heat treatment and temperature control treatment at, for example, about 100 ° C. ( Step 5).

Next, the wafer W is cooled by the cooling processing unit (CP
L) is cooled at a predetermined temperature (step 6). After that, the wafer W may be taken out by the second main transfer device A2 and transferred to the film thickness inspection device 119 to measure the resist film thickness. The wafer W is then transferred to the transition unit (T
The exposure apparatus 1 via the RS) and the interface unit 14.
00, and exposure processing is performed there (step 7).

Next, the wafer W has an interface section 14
And, after being transferred to the second main transfer device A2 via the transition unit (TRS) in the fifth processing unit section G5, it is transferred to one of the post-exposure baking units (PEB) to a predetermined position. The heating process and the temperature control process are performed (step 8). Thereafter, a predetermined cooling process is performed in the cooling process unit (CPL) (step 9). After the exposure process is completed, the wafer W may be temporarily stored in the buffer cassette BR in the interface section 14. And the wafer W
Is conveyed to the development processing unit (DEV) and development processing is performed (step 10).

Next, the wafer W is carried into the optical observation device 40 via the second main wafer transfer device A2, where the resist pattern is recognized and the line width of the resist pattern is measured. The line width may be measured for a plurality of chips on the wafer. When the measurement is performed on a plurality of chips in this way, the average value of those line widths may be obtained.

FIG. 10 shows the measurement results of the line widths on the wafers W to W which have been heat-treated by the heating plates 86 to 86 in PEB to PEB, respectively. For example, it is assumed that when the target line width is 150 nm, the line width of the wafer W is the target line width, and the other wafers W, ... Are deviated from the target as illustrated. Here, as shown in FIG. 11, the higher the heating temperature of the wafer by the heating plate, the smaller the line width. Therefore, this relationship is utilized to heat the heating plates 86, ... As shown in FIG. Offset the temperature. That is, since the line width of the wafer W is the target line width and the desired line width is obtained, the heating temperature of the heating plate 86 is not changed, and the heating temperatures of the heating plates 86, ... Are corrected as illustrated.

In this embodiment, before the heating temperature is corrected, all the heating plates 86 to 86 have the same heating temperature (for example, 90%).
As a result of the processing at (.degree. C.), the line widths of the respective wafers, .about. Have been displaced, so that the heating plates ,. For example, in FIG. 11, the heating plate is corrected to 89 ° C., the heating plate to 92 ° C., the heating plate to 88 ° C., and the heating plate to 91 ° C. In this case, each heater 9
It is preferable to control 1 to 99 so that all of them have the same temperature within the surface of the heating plate.

Conventionally, even if a plurality of post-exposure baking units (PEB) are set to the same environment, that is, the same heating temperature and the line width is strictly controlled, the line widths of a plurality of wafers are not controlled. Although there was variation, the line width can be precisely controlled and the desired resist pattern can be formed by correcting the wafer heating temperature based on the line width measurement result as in the present embodiment. Therefore, variation among multiple wafers can be suppressed,
The uniformity of the line width can be improved.

When the resist pattern is recognized by using an electron microscope, the resist pattern may be contracted due to the influence of the electron beam. However, the optical observation device 40 as in this embodiment is used. Thus, the line width can be measured nondestructively without causing such a problem. As a result, the line width of the actual resist pattern can be measured accurately, which contributes to the accurate formation of the resist pattern.

In this embodiment, the heating temperature may be corrected first by using several test wafers, and then the actual product wafer may be used for manufacturing, or It is also possible to control the heating temperature dynamically in the product manufacturing stage.

Next, the control of the heating temperature within the plane of one wafer will be described. FIG. 13A shows the line width measured by the optical observation device 40 within the wafer surface (wafer radial direction). Thus, for example, when the line width in the wafer surface is not uniform, the wafer W placed on the heating plate 86 is shown in FIG. 13B according to the correlation shown in FIG. 11 as shown in FIG. The temperature is controlled so that In this case, the heating temperatures of the heaters 91 to 99 in one heating plate 86 are independently controlled so that the heating temperatures are different in the heating plate 86 (radial direction of the heating plate 86). As a result, the line width within the wafer surface can be made uniform.

Similarly, if the measured line width is as shown in A of FIG. 15A, the temperature of the heating plate 86 is controlled as shown in C of FIG. When the line width is as shown in B of (a), the temperature of the heating plate 86 is controlled as shown in D of (b) to make the line width uniform in the wafer surface. it can.

Next, a method of measuring the line width by the optical observation device 40 will be described. When the resist pattern formed on the wafer W is recognized and the line width is measured by the above-mentioned pattern matching, for example, as shown in FIG. Take a measurement. In this case, the measurement is not limited to 400 points, but may be 100 points to 20000 points, preferably 10,000 points.

By recognizing the resist pattern at multiple points on the wafer surface as described above, the line width distribution on the wafer surface can be grasped with higher accuracy and precise control can be performed. As described above, even with multi-point recognition exceeding 10,000 points, by using the optical observation apparatus by pattern matching, processing can be performed much faster than when using an electron microscope. When an optical observation device is actually used, it is 1/10 to 1/30 compared with SEM.
Can be processed in time of. Thereby, the throughput can be improved.

The present invention is not limited to the embodiment described above, and various modifications can be made.

For example, in the above-described embodiment, the optical observation device 40 is in-line with the coating and developing treatment device 1, but it may be a stand-alone device instead.

Further, although the multi-point recognition by the optical observation device 40 is set to 100 to 20000 points, it may be set to be more than this for more precise line width measurement in the wafer plane.

Further, in the above embodiment, the case where the semiconductor wafer is used has been described, but the present invention is not limited to this and the present invention can be applied to a glass substrate used for a liquid crystal display or the like.

[0063]

As described above, according to the present invention,
The line width of the resist pattern formed on the wafer can be precisely controlled, and the uniformity of the line width can be improved for each wafer or within the wafer surface.

[Brief description of drawings]

FIG. 1 is a plan view of a coating and developing treatment apparatus according to an embodiment of the present invention.

FIG. 2 is a front view of the coating and developing treatment apparatus shown in FIG.

FIG. 3 is a rear view of the coating and developing treatment apparatus shown in FIG.

FIG. 4 is a perspective view showing a main wafer transfer device.

FIG. 5 is a conceptual configuration diagram of an optical observation device.

FIG. 6 is a plan view of a post exposure baking unit (PEB).

7 is a sectional view of the post-exposure baking unit (PEB) shown in FIG.

FIG. 8 shows a control system of PEB to PEB.

9 is a flowchart showing a series of processing steps of the coating and developing processing apparatus 1. FIG.

FIG. 10 shows measurement results of line widths on wafers W to W that have been heat-treated by heating plates 86 to 86, respectively.

FIG. 11 is a diagram showing a relationship between a heating temperature and a line width in the heat treatment.

FIG. 12 is a diagram showing respective heating temperatures by the heating plates 86 to 86.

FIG. 13A is a diagram showing an example of a line width distribution in the wafer surface, and FIG. 13B is a temperature distribution in the heating plate surface.

FIG. 14 is a side view showing a state where a wafer is placed on a heating plate.

15A is a diagram showing another example of the line width distribution in the wafer surface, and FIG. 15B is a temperature distribution in the heating plate surface.

FIG. 16 is a plan view for explaining multipoint recognition by the optical observation device.

[Explanation of symbols]

W ... Semiconductor wafer COT ... Resist coating processing unit DEV ... Development processing unit PEB (PEB to PEB) ... Post-exposure baking unit 1 ... Coating development processing apparatus 34 ... Temperature controller 40 ... Optical observation apparatus 60 ... Control unit 86 (86) ~ 86) ... Heating plates 91-99 ... Heater

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Ryoichi Uemura             TBS release, 5-3-6 Akasaka, Minato-ku, Tokyo             Sending Center Tokyo Electron Limited (72) Inventor Shuji Iwanaga             TBS release, 5-3-6 Akasaka, Minato-ku, Tokyo             Sending Center Tokyo Electron Limited F-term (reference) 2H096 AA25 FA01 GB03 GB07

Claims (16)

[Claims] 1. A substrate processing method for forming a desired resist pattern by forming a resist film on a substrate and then performing heat treatment on the substrate before the development process, comprising: forming a resist pattern formed after the development process; A substrate processing method comprising: a step of recognizing a shape; and a step of controlling a temperature of the heat treatment based on the recognition result. 2. The substrate processing method according to claim 1, wherein the heat treatment is performed by placing a substrate on a hot plate, and the heat treatment temperature is controlled by controlling a temperature of the hot plate. A substrate processing method, comprising: 3. The substrate processing method according to claim 2, wherein the step of controlling the heat treatment temperature includes a step of controlling the temperature in the hot plate surface based on the distribution of the resist pattern shape in the substrate surface. A substrate processing method comprising: 4. Any one of claims 1 to 3
Item 5. The substrate processing method as described in the item 1, wherein the recognition of the resist pattern shape is performed by an optical observation device. 5. The substrate processing method according to claim 4, wherein recognition of the resist pattern shape by the optical observation device is performed at multiple points within the substrate surface. 6. The substrate processing method according to claim 5, wherein the multipoint recognition is performed at 100 points to 20000 points. 7. The substrate processing method according to claim 1, wherein a plurality of the heat plates are provided, heat treatment is performed on a plurality of substrates on each of the plurality of heat plates, and a heat treatment temperature is set for each of the plurality of heat plates. A substrate processing method comprising a controlling step. 8. Any one of claims 1 to 3
Item 5. The substrate processing method according to Item 4, wherein the shape of the resist pattern relates to a line width. 9. A heat treatment means for heat-treating a substrate on which a resist film is formed before the development treatment, a means for recognizing the shape of a resist pattern formed after the development treatment, and the heat treatment based on the recognition result. And a means for controlling the temperature of the substrate processing apparatus. 10. The substrate processing apparatus according to claim 9, wherein the heat treatment unit includes a heat plate on which a substrate is placed and heat treatment is performed, and the heat treatment temperature control unit controls the temperature of the heat plate. A substrate processing apparatus comprising: 11. The substrate processing apparatus according to claim 10, wherein the heat treatment temperature control unit controls the temperature in the hot plate surface based on the distribution of the resist pattern shape in the substrate surface. Substrate processing equipment. 12. The substrate processing apparatus according to claim 9, wherein the resist pattern shape is recognized by an optical observation device. 13. The substrate processing apparatus according to claim 12, wherein the recognition of the resist pattern shape by the optical observation device is performed at multiple points within the substrate surface. 14. The substrate processing apparatus according to claim 13, wherein the multipoint recognition is performed at 100 points to 20000 points. 15. The substrate processing apparatus according to claim 9, wherein the resist pattern has a shape related to a line width. 16. A plurality of heat treatment units that heat-treat a plurality of substrates on which a resist film is formed before the development treatment, a conveyance mechanism that conveys the substrates to the plurality of heat treatment units, and a post-development treatment. A substrate processing apparatus comprising: a unit for recognizing the shape of the formed resist pattern for each of the plurality of substrates; and a unit for controlling the temperature of heat treatment for each of the plurality of heat treatment units based on the recognition result. .