JP2003207756A - Liquid crystal display - Google Patents

Abstract

(57) [Problem] To easily and surely detect a defective product even in the case of a slight transistor characteristic deviation. For each TFT 205, two gate control signal voltages (for example, 13V and 10V) for testing TFT characteristics are provided.
In the case of TFT characteristic failure, defective products due to slight shifts in TFT element characteristics can be easily and reliably determined by changing the brightness of the display image every predetermined switching time (n-field period). This eliminates the need for turning on both the inspection target device and the comparison target device and comparing the luminance with a large-scale device over time as in the related art.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device such as an active matrix type liquid crystal display device having a transistor characteristic detecting circuit for detecting a transistor characteristic.

[0002]

2. Description of the Related Art A configuration example of a conventional active matrix type liquid crystal display device will be described with reference to FIG.

In FIG. 11, an active matrix type liquid crystal display device 100 includes a liquid crystal display panel 200 having a display screen and a source driver 300 as a control signal line driving means for supplying a video signal to the liquid crystal display panel 200.
And a gate driver 400 as video signal line driving means for controlling the timing of supplying a video signal to the liquid crystal display panel 200, and a control IC 500 for supplying a synchronization control signal to the source driver 300 and the gate driver 400. And have.

The liquid crystal display panel 200 includes a transparent insulating substrate (hereinafter referred to as an active matrix substrate) such as a glass plate having a plurality of pixel electrodes 201 arranged in a matrix, and facing the active matrix substrate. The liquid crystal layer LC is sandwiched between the liquid crystal layer LC and a transparent insulating substrate (hereinafter, referred to as a counter substrate) such as a glass plate on which the one-film common electrode 202 is provided.

The active matrix substrate has a plurality of gate control signal lines 203 (gate signal lines) and a plurality of video signal lines 204 intersecting these gate control signal lines 203.
(Source signal line), a pixel electrode driving element 205 that drives pixels by being arranged at each intersection of each gate control signal line 204 and each video signal line 203, and each pixel element driving element 205. The pixel electrode 201 is connected to the matrix wiring through the pixel electrode 201.

This pixel electrode driving element 205 is a thin film transistor (TFT:
Thin Film Transister) and MIM (Metal Insulator)
Metal) element and the like.

The source driver 300 includes an H shift register 301 for sequentially outputting sampling signals obtained by sequentially delaying an input sampling signal SP in synchronization with a clock signal CLK, and an RGB shift signal input terminal Sin for each color component of a video signal. An RGB signal line 302 to which a certain RGB signal is input, and a plurality of sampling switches 303 (sampling SW 303) that repeatedly turn on / off each color signal from the RGB signal line 302 in response to a sampling signal from the H shift register 301 to output each color signal, A plurality of sampling capacitors 304 each temporarily holding each color signal from the sampling SW 303, and a plurality of transfer switches 305 (transferring all the color signals respectively held in each sampling capacitor 304 by the transfer signal TRS). And SW305), each transfer SW305
A plurality of transfer capacitors 306 that temporarily hold the respective color signals transferred via the plurality of operational amplifiers 307, and a plurality of operational amplifiers 307 that amplify the respective color signals respectively held in the respective transfer capacitors 306 and output the amplified color signals to the plurality of video signal lines 203. And have.

The gate driver 400 outputs a gate control signal line selection signal and a V shift register 401 that sequentially outputs a gate control signal line selection signal in which the input start pulse signal SPG is synchronized with the gate clock signal CLG and sequentially delayed. Externally supplied gate-on voltage VGH
Output buffers 40 for outputting the
2 and. The output buffer 402 is provided for each gate control line 204.

The control IC 500 has a serial / parallel conversion circuit 501 and a CLG generation circuit 502 for generating a gate clock signal CLG in response to a control signal from the serial / parallel conversion circuit 501, and has an input sampling signal SP and a clock signal CLK. And transfer signal TR
S is output to the source driver 300, and the start pulse signal SPG and the gate clock signal CLG are output to the gate driver 400.

With the above configuration, first, the RGB signals, which are the respective color components of the video signal, are input to the RGB signal line 302 via the RGB signal input terminal Sin, and the input sampling signal SP is sequentially synchronized with the clock signal CLK. By the output H shift register 301, each color signal of the video signal in one horizontal period on the RGB signal line 302 is sequentially sampled by each sampling SW 303 as a video signal to be displayed on the liquid crystal display panel 200, and the sampled video signal The respective color components of are sequentially held in the respective sampling capacitors 304.

Next, until the sampling operation, each transfer SW 305 is turned on by the transfer signal TRF output from the control IC 500, and the video signal in one horizontal period is transferred from each sampling capacitor 304 to each transfer SW3.
05 is transferred to each transfer capacitor 306. Further, the video signal voltages charged in the transfer capacitors 304 are respectively amplified by the operational amplifiers 307 and then transferred to the video signal lines 203.

On the other hand, the video signal for one horizontal period output to each video signal line 203 is supplied to the gate driver 400.
In accordance with the gate control signals sequentially output from the output buffer 402 of FIG. 1 to the respective gate control signal lines 204, a plurality of TFTs 205 in a horizontal line for one line connected to the gate control signal lines 204 are simultaneously turned on, and a plurality of images are displayed. Each video signal voltage on the signal line 203 is applied to each TFT 205.
Is written in each picture element electrode 201 through.

The output timing of the gate control signal from the gate driver 400 in this case will be described.

FIG. 12 shows the gate driver 400 of FIG.
3 is a timing chart showing the output timing of each gate control signal from FIG. As shown in FIG. 12, the control IC 50 is added to the V shift register 401 of the gate driver 400.
The start pulse signal SPG output from 0 is synchronized with the gate clock signal CLG having a predetermined frequency, and is placed at the top of the gate control signal line 204 of the first line (first line) of the screen of the liquid crystal display panel 100. The gate control signal is output through the output buffer 402 of the screen, which causes the screen 1
The line is displayed. Further, in synchronization with the gate clock signal CLG of a predetermined frequency, the second line of the screen (second line)
A gate control signal is output to the gate control signal line 204 of the second output buffer 402 from the top, and this is repeated in the cycle of the gate clock signal CLG to display one screen within one vertical period. Output buffer 4
The gate-on voltage VGH of the gate control signal output to the gate control signal line 204 through 02 is 13 V, and the gate-off voltage is 0 V (GND).

[0015]

Conventional liquid crystal display device 1
In 00, even if the gate-on voltage VGH is constant, TF
If the T characteristic is defective, the signal level of the video signal may not be accurately written in the pixel electrode 201. In the conventional TFT characteristic inspection method, in order to determine whether or not the liquid crystal display device 100 is insufficiently charged with TFT, the image signal voltage applied to the liquid crystal layer LC is set to a fixed value, and the liquid crystal display device 100 having good TFT characteristics. Is determined and the luminance of the liquid crystal display device 100 to be inspected is measured to determine whether it is a non-defective product or a defective product as compared with that of a non-defective product. In this case, it is necessary to turn on the non-defective liquid crystal display device 100 so that it can be compared with the liquid crystal display device 100 to be measured. Thereby, the liquid crystal display device 10 to be inspected
In addition to the 0 brightness measurement, a non-defective liquid crystal display device 10 to be compared
It takes time to measure the brightness of 0, which is a major cause of a decrease in processing speed. Further, even when compared with the non-defective liquid crystal display device 100, the inspection device becomes large, and a drive circuit for driving the liquid crystal display device 100 for comparison is required, which leads to an increase in cost.

Further, in the conventional method of inspecting the TFT characteristics of the liquid crystal display device 100, after the liquid crystal display device 100 is inspected and shipped, the liquid crystal display device 100 is used in various processes such as manufacturing and transportation. In some cases, the TFT characteristics may be slightly shifted due to static electricity, etc., and if the TFT characteristics are extremely shifted, the defective product can be determined, but if the TFT characteristics are slightly shifted, the defective product determination is difficult and cannot be detected. was there.

In the conventional quality inspection of TFT characteristics, TF
The present inventors examined the T characteristic as follows.

FIG. 13 shows the source driver 300 of FIG.
3 is a signal waveform diagram of the video signal output of, the gate clock signal CLG of the TFT and its drain voltage.

Referring to FIG. 13, the respective signal waveforms will be sequentially described. First, in the output signal waveform of the video signal from the source driver 300, the video signal output period (a)
Is the timing of writing the high-level voltage video signal, and the next period (b) is the timing of writing the low-level voltage video signal to the picture element electrode 201. Further, the gate control signal output from the gate driver 400 becomes a high level voltage by the high level voltage of the gate clock signal CLG to turn on the gate of the TFT, and the low level voltage of the gate clock signal CLG causes the gate driver 400 to turn on. The output gate control signal turns off the gate of the TFT at a low level voltage.

The output signal waveform (a) to the drain D of the TFT is a normal TFT (non-defective product) at the high level timing (gate high level voltage timing) of the gate clock signal CLG during the video signal output period (a). ), A signal waveform when the source driver 300 writes a maximum voltage of 5 V capable of outputting a video signal to the pixel electrode 201 is shown.

The output signal waveform (b) to the drain D of the TFT has a normal TFT (non-defective product) at the high level timing (gate high level voltage timing) of the gate clock signal CLG during the video signal output period (b). ), The minimum voltage that the source driver 300 can output is 1 V
7 shows a signal waveform when the video signal of (1) is written in the pixel electrode 201.

The output signal waveform (c) to the drain D of the TFT has a normal characteristic which is deviated at the high level timing (gate high level voltage timing) of the gate clock signal CLG during the video signal output period (a). Not T
A signal waveform when the source driver 300 writes a maximum voltage of 5 V that can output a video signal to the pixel electrode 201 via an FT (defective product) is shown.

The output signal waveform (d) to the drain D of the TFT has a normal characteristic which is deviated at the high level timing (gate high level voltage timing) of the gate clock signal CLG during the video signal output period (b). Not T
The signal waveform when writing the video signal of the minimum voltage 1V which the source driver 300 can output via FT (defective item) in the picture element electrode 201 is shown.

FIG. 14 shows the gate / source voltage VG of the TFT.
TFT showing relationship between S and source / drain current IDS
It is a characteristic diagram.

In FIG. 14, the solid line shows the normal TFT characteristics of a good product (TFTa), and the dotted line shows the defective TFT (TFTb).
The T characteristic is shown.

In FIG. 14, a non-defective product (TFT
The gate-on potential of (a) (gate-on voltage VGH of the gate control signal) is 13 V, and the maximum drain potential of the video signal is 5 V
Then, the gate-source voltage VGS is 13V-5V.
= 8V, the IDS current is IDSa8 (ID corresponding to A8 on the characteristic curve when the gate-source voltage VGS is 8V).
S current), which exceeds the minimum IDS current value IDSM (shown by a dashed line) that allows the TFTa to sufficiently charge the pixel electrode 201 within the ON period of the TFTa, and the drain D of the TFT of FIG. The waveform of the output signal to (a) is shown by the solid line waveform, and the same potential as the output video signal voltage 5V from the source driver 300 is written to the pixel electrode 201 during the ON period of the TFTa.

Assuming that the gate-on voltage V of the gate control signal
Even if GH is 10 V, the gate-source voltage VGS is
10V-5V = 5V, TF with normal TFT characteristics
In the case of the liquid crystal display device 100 having Ta, the IDS current becomes IDSa5 (the gate-source voltage VGS is 5V, which represents the IDS current corresponding to A5 on the characteristic curve), and the TFTa is turned on during the ON period of the TFTa. Picture element electrode 201
13 is higher than the minimum IDS current value IDSM (indicated by a dashed line) that can be sufficiently charged, and as shown by the dotted waveform of the output signal waveform (a) in FIG. Even if the rise of
The output video signal voltage 5V from the source driver 300 can be written in the pixel electrode 201 within the ON period of.

If the TFT has normal TFT characteristics, the VGS-IDS characteristic of the TFTa shown in FIG. 14 is indicated by a solid line. If the gate-on potential of the TFTa is 13V and the minimum drain potential of the video signal is 1V, the source Gate voltage V
GS becomes 13V-1V = 12V, and IDS current is I
DSa12 (the gate-source voltage VGS is 12V, indicating the IDS current corresponding to A12 on the characteristic curve), which exceeds the current value IDSa8 when writing the video signal of the output video voltage 5V. This is higher than the minimum IDS current IDSM with which the TFTa can sufficiently charge the pixel electrode 201 during the ON period of the TFTa, as shown by the solid line signal waveform of the output signal waveform (b) in FIG. The same potential as the output voltage 1V from 300 is applied to the pixel electrode 2
01 will be written.

Also in this case, even if the gate-on voltage VGH of the gate control signal is 10V and the gate-source voltage VGS is 10V-1V = 9V, the normal T
In the case of the liquid crystal display device 100 having the TFTa having the FT characteristic, the IDS current is IDSa9 (gate / source voltage VG
When S is 9 V, the IDS current corresponding to A9 on the characteristic curve is shown), and the minimum IDS current value IDSM (shown by a dashed line) where the TFTa can sufficiently charge the pixel electrode 201 within the ON period of the TFTa. 13) and Fig. 13
As shown by the dotted line waveform of the output video signal waveform (b) of
Even if the fall of the waveform of the video signal written in the pixel electrode 201 is slow, the source driver 30 is turned on during the ON period of the TFTa.
The output image signal voltage 5V from 0 exceeds the minimum IDS current IDSM with which the pixel electrode 201 can be written. Even when the output video signal voltage from the source driver 300 is 1V, which is the minimum, the output signal voltage 1
The same potential as V is written in the pixel electrode 201.

Therefore, in the image displayed on the active matrix type liquid crystal display device 100, a positive polarity video signal and a negative polarity video signal are alternately written to the pixel electrodes 201 for each line, or one screen is displayed. All picture element electrodes 2
After writing 01, the polarities of the video signals of the line in which the video signal of the positive polarity is written and the line in which the video signal of the negative polarity is written are reversed on the next screen, and the pixel electrode 201
Written in. Therefore, as the voltage applied to the liquid crystal layer LC, a voltage of 5V-1V = 4Vp-p is applied regardless of whether the gate-on voltage VGH of the gate control signal is 13V or 10V, and the input video signal voltage. Can be faithfully reproduced.

However, as shown by the dotted line of the VGS-IDS characteristic waveform in FIG. 14, in the case of the defective product (TFTb) in which the TFT characteristics are shifted, the gate-on potential of the TFTb is 13V and the maximum drain potential of the video signal is If it is 5V, the gate-source voltage VGS is 13V-5V = 8V
And the IDS current becomes IDSb8 (the gate-source voltage VGS is 8V, which indicates the IDS current corresponding to B8 on the characteristic curve), and TF is turned on during the ON period of the TFTb.
The minimum ID that can sufficiently charge the pixel electrode 201 with the output video signal voltage from the source driver 300 having Tb of 5V.
It falls below the S current value IDSM. In this case,
As shown in the waveform (c) of the output signal to the drain D of the TFTb 3 of FIG. 3, the ON period of the TFTb (gate clock signal C
During the LG high-level voltage period), a voltage lower than the output video signal voltage 5V from the source driver 300 (for example, FIG. 1).
In No. 3, only 4.8 V can be written in the pixel electrode 201.

When the gate-on voltage is 10 V and the maximum drain potential of the video signal is 5 V, the gate-source voltage VGS
Becomes 10V-5V = 5V, and the IDS current is the current value I
DSb5 (the gate-source voltage VGS is 5V, indicating the IDS current corresponding to B5 on the characteristic curve),
The current value IDSb5 is lower than the current value IDSa8 when the gate-on voltage is 13V and the output video signal voltage 5V is written. This is because the rising edge of the video signal waveform written in the pixel electrode 201 is further delayed, as shown by the dotted line waveform of the output video signal waveform (C), and the ON period of the TFTb (the high level voltage period of the gate clock signal CLG is increased). ), The output video signal voltage of 5 V of the source driver 300 is applied to the pixel electrode 201.
The voltage value that can be written to is lower than the voltage value when the VGS voltage is 8V (eg, 4.3 in FIG. 13).
V).

Further, in the case of a defective product (TFTb) in which the TFT characteristics are shifted, VGS-ID of the TFTb of FIG.
If the gate-on potential of the TFTb is 13V and the minimum drain potential of the video signal is 1V, which is shown by the S characteristic (dotted line), the source-gate voltage VGS is 13V-1V = 12V, and the TFTb is the pixel electrode during the ON period. 201 exceeds the minimum IDS current IDSM that can sufficiently charge the output video signal voltage 5V from the source driver 300 (B12 on the characteristic curve). Therefore, the source driver 3
If the output signal voltage of 00 is 1V, the output signal voltage from the source driver 300 is 1V during the ON period of the TFTb.
The same potential as is written in the pixel electrode 201.

When the gate voltage VGH is 10V and the minimum drain potential is 1V, the gate-source voltage VGS is 10V.
V-1V = 9V and T of defective product with TFT characteristics shifted
If the liquid crystal display device 100 has an FT, the TF of FIG.
As shown by the dotted line of the output signal waveform (d) to the drain D of T, the output signal waveform written to the pixel electrode 201 has a slow fall, but the output signal voltage from the source driver 300 during the ON period of the TFT. It exceeds the minimum IDS current IDSM capable of writing 5 V to the pixel electrode 201 (B9 on the characteristic curve). Therefore, when the output signal voltage of the source driver 300 is 1V, T
The same signal voltage as the output signal voltage 1V from the source driver 300 is written in the pixel electrode 201 during the ON period of the FT.

From the above, the T from the source driver 300
The output signal waveform of negative polarity is normally transmitted through the FT to the pixel electrode 2
01 can be applied to the source driver 300
Therefore, a positive output signal waveform cannot be written in the pixel electrode 201. Therefore, the image of the liquid crystal display device 100 cannot be faithfully reproduced with respect to the input video signal. As the video signal voltage applied to the liquid crystal layer LC in the above case, a video signal of positive polarity and a video signal of negative polarity are alternately written for each line as an image, and after the entire screen is written. On the next screen, the polarities of the video signals written to the positive polarity written line and the positive polarity written line are reversed and written.
Therefore, the voltage applied to the liquid crystal layer LC is the gate-on voltage V
When GH is 13V, write voltage is 4.8V-1V
= 3.8Vp-p and the gate-on voltage VGH is 10V, a video signal voltage of 4.3V-1V = 3.3Vp-p is applied. Therefore, the abnormal TFT
TFT with normal TFT characteristics when it has characteristics TFTb
The voltage becomes lower than that of the case with a (5V-1V = 4Vp-p), and the image becomes light on the entire screen (in the case of normally white).

Thus, the TF with the TFT characteristics shifted
When the liquid crystal display device 100 having Tb is inspected, the gate-on voltage VGH is lowered within a range in which the image does not change in the on-characteristics of the non-defective TFTa.
By making the thinning of the screen noticeable in the on-characteristic of Tb, and judging the brightness of the dark and light images on the display screen,
A determination of good or bad can be made.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a liquid crystal display device capable of easily and reliably detecting a defective product even in the case of a slight transistor characteristic deviation. .

[0038]

In the liquid crystal display device of the present invention, a plurality of picture element electrodes are provided near the intersections of a plurality of video signal lines and a plurality of control signal lines, respectively. In a liquid crystal display device that supplies an image signal to each pixel electrode at each drive timing of the pixel electrode driving element to display an image, between two control signal voltages for element characteristic inspection for each pixel electrode driving element. The above-mentioned object is achieved by having an image display control means capable of displaying an image by switching.

Further, preferably, the image display control means in the liquid crystal display device of the present invention comprises a video signal line driving means for sequentially selecting a video signal line from a plurality of video signal lines and supplying a video signal, and a plurality of control devices. Control signal line driving means for sequentially selecting control signal lines from the signal lines and supplying a control signal, and driving voltage switching for switching between two driving voltages for element characteristic inspection supplied to the control signal line driving means And means.

Further, preferably, the drive voltage switching means in the liquid crystal display device of the present invention comprises a switching timing control signal generating means for generating a switching timing control signal and two for inspecting element characteristics based on the switching timing control signal. And a drive voltage generating means for alternately switching the drive voltage.

Further, preferably, the drive voltage generating means in the liquid crystal display device of the present invention has a series circuit of the dividing resistance means and the switching means, and controls the switching means according to the switching timing control signal to divide the resistance. The drive voltage is obtained from the divider of the means.

Further, preferably, the switching timing control signal generating means in the liquid crystal display device of the present invention switches the signal level of the switching timing control signal at least every one field period or one frame period of the screen display. Further, the drive voltage generating means switches between the signal levels of the two drive voltages at least every one field period or one frame period of the screen display.

Further, preferably, the switching timing control signal generating means in the liquid crystal display device of the present invention switches the signal level within one field of the screen display and at the same display line position for each field. Further, the drive voltage switching means in the liquid crystal display device of the present invention switches between the signal levels of the two drive voltages within one field of the screen display and at the same display line position for each field.

Further, preferably, in the switching timing control signal generating means or the drive voltage switching means of the liquid crystal display device of the present invention, the switching line position in one field of the screen display is one or plural, and the screen display The switching within one field is performed once or a plurality of times.

Further, preferably, in the switching timing control signal generating means or the drive voltage switching means of the liquid crystal display device of the present invention, the switching direction between two signal levels at the same display line position is m (m is a natural number) field. The opposite direction is used for each. That is, the order of switching within the screen display period is reversed.

Further, preferably, at least one of the set values of the two drive voltages in the liquid crystal display device of the present invention is variable. For example, when the dividing resistance means is composed of a series circuit of the first resistance means and the second resistance means, at least the second resistance means is composed of the variable resistance means. Further, a plurality of series circuits of the first resistance means and the second resistance means may be provided to be selectable.

With the above-mentioned structure, since the image display is performed by switching between the two control signal voltages for inspecting the element characteristics for each picture element electrode driving element, when the element characteristics are defective, the switching time or the switching position is changed. It is possible to easily and surely check for defective products due to slight shifts in element characteristics by changing the brightness of the displayed image. There is no need to compare the brightness by multiplying.

The detection of the liquid crystal display device in which the element characteristics are deviated is determined by switching the control signal voltage (element driving voltage) in the middle of the display period and changing the brightness of the display screen. It is not necessary to compare the brightness with a non-defective liquid crystal display device and to measure the brightness of the display screen of the liquid crystal display device. Therefore, the quality inspection work of the element characteristics is simplified and the work efficiency is improved.

The two control signal voltages (two drive voltages) output to the control signal line are, for example, 1 for each frame.
Since it is possible to switch between 3V and 10V, the display screen looks like flicker in the liquid crystal display device in which the element characteristics are deviated, and it is possible to easily and reliably determine the quality of the element characteristics by checking the flicker. Become.

Further, since the two control signal voltages (two driving voltages) output to the control signal lines are switched between 13 V and 10 V, for example, in the middle of one screen, in the liquid crystal display device in which the element characteristics are deviated, the upper part of the screen is displayed. It is possible to easily and surely judge the quality of the element characteristics by the difference in brightness between the bottom and the bottom.
As compared with the method of switching the drive voltage (control signal voltage) within the display period, it becomes possible to detect the defective element characteristics more reliably in a shorter time.

Furthermore, in addition to switching the two control signal voltages (two driving voltages) output to the control signal line between 1.3 V and 10 V in the middle of one screen, the voltage is changed to 13 V within the display period. By switching the switching direction between 10V in the opposite direction, it is possible to easily and surely determine the quality of the element characteristics even when there is a slight element characteristic deviation in a part of the display screen (for example, the upper part or the lower part). Is possible.

Further, two control signal voltages (two driving voltages) are provided for each predetermined line (for example, three lines) on the display screen.
, For example, is switched between 13 V and 10 V, so in a liquid crystal display device with deviated element characteristics, the display brightness changes every predetermined line within one screen, which appears as a horizontal striped pattern. It becomes possible to easily and surely determine the quality of the element characteristics only by performing the confirmation inspection. Further, in this case, even when the element characteristics are deviated only in a part of the display screen, a portion where the element characteristics are deviated appears as a striped pattern, so that the display screen of the liquid crystal display device in which the element characteristics are deviated It becomes possible to easily and surely perform a part of quality judgment.

Further, every predetermined line (for example, 3 lines)
Two control signal voltages (two drive voltages) are, for example, 13
In addition to switching between V and 10V, the switching direction (switching order) for switching between, for example, 13V and 10V is reversed in the display period, so that only a small part (several lines) of the display screen is displayed. It is possible to easily and surely detect a characteristic deviation defect.

Further, by varying the values of the two control signal voltages (two driving voltages) to be switched, it is possible to satisfactorily change the detection level of the defective element characteristics so that the display brightness difference becomes clearer. Become.

Further, in addition to the usual driving method, for example, a switching timing control signal generating means and a driving voltage switching means capable of controlling the switching timing of the driving voltage are built in the control IC having the control circuit of the liquid crystal display device built therein. By doing so, it becomes possible to easily and reliably detect whether the element characteristics are good or bad due to static electricity or the like after being incorporated in a product as a liquid crystal display device.

[0056]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a case where Embodiments 1 to 6 of a liquid crystal display device of the present invention are applied to an active matrix type liquid crystal display device will be described with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing a main configuration of a liquid crystal display device according to Embodiment 1 of the present invention. In addition,
Members having the same effects as those of FIG. 11 are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 1, the liquid crystal display device 10 includes a liquid crystal panel 200 as an image display means and a video signal line 203 which sequentially selects one video signal line 203 from a plurality of video signal lines 203 to supply respective color signals of the video signal. A source driver 300 as a signal line driving means, and a plurality of gate control signal lines 2
Gate driver 400 as control signal line driving means for sequentially selecting one control signal line 204 from 04 to supply a gate control signal, control circuit control IC 11 including switching timing control signal generating means, and drive voltage generating means. Drive voltage generating circuit 12 as

These control IC 11 and drive voltage generation circuit 12 constitute drive voltage switching means, and the drive voltage switching means supplies TF to the source driver 300 based on the switching timing control signal from the control IC 11.
Two driving voltages for T characteristic inspection (= gate-on voltage VG
H) can be switched at predetermined time intervals. Further, the drive voltage switching means, the source driver 300 and the gate driver 400 constitute an image display control means, and the image display control means conducts a TFT characteristic inspection for the TFT 205 as each pixel electrode drive element. The two control signal voltages (= gate-on voltage VGH) are switched at predetermined time intervals to display an image on the liquid crystal panel 200. As will be described later in detail, the predetermined time interval is a time interval that can be visually confirmed. For example, the predetermined time interval is an n field period (or n frame period; n is a natural number) of screen display.

The serial / parallel conversion circuit 501 of the control IC 11 includes a switching timing control signal generating means, and the switching timing control signal generating means is an inversion pulse signal RP1 (hereinafter RP1) as a switching timing control signal.
Signal).

The drive voltage switching circuit 12 includes a power supply voltage input terminal VGH1 for the gate driver (eg, power supply voltage 15).
V) and the ground (GND), the division resistors R1 and R2 as division resistance means and the control switch 121 as switching means are connected in series (composed of a series circuit), and the division portion of the division resistances R1 and R2. The (connection point) is connected to the input VGH terminal of the gate driver 400, and the output inversion pulse signal line from the control IC 11 is connected to the control terminal 122 of the control switch 121.

More specifically, in the drive voltage generating circuit 12, the high level voltage of the inversion pulse signal RP1 (RP1 signal) which is inverted every n field periods is input to the control terminal 122 and the control switch 121 is turned on. At this time, a voltage of, for example, 10 V is applied to the input VGH terminal for the gate driver 400 from the dividing portion (connection point) of the dividing resistors R1 and R2 having a predetermined dividing ratio. In the drive voltage generation circuit 12, the low level voltage of the inversion pulse signal RP1 (RP1 signal) which is inverted every n field periods is input to the control terminal 122 and the control switch 12 is operated.
When 1 is turned off, a voltage of 13 V, for example, is applied to the input VGH terminal for the gate driver from the dividing portion (connection point) of the dividing resistors R1 and R2. As described above, the control switch 121 is controlled by the inverted pulse signal RP1.
Can be switched between two drive voltages (here, 13V and 10V) for TFT inspection applied to the gate (control terminal) of the TFT 205 by continuously turning on / off at predetermined time intervals. I have to.

With the above configuration, the operation will be described below.

FIG. 2 is a diagram showing the drive timing of the gate driver 400 of FIG. 1 and the application distribution of the gate-on voltage VGH for each display screen.

As shown in FIGS. 1 and 2, when the gate start pulse SPG is input to the V shift register 401 of the gate driver 400, the V shift register 401
Performs a selection pulse output operation so as to sequentially delay the gate start pulse SPG in synchronization with the input gate clock signal, and first outputs the selection pulse from the buffer circuit 402 for the gate control signal line 204 of the first line. Buffer circuit 4 for the gate control signal line 204 of the line
02 are sequentially operated, and the gate-on voltage VGH is sequentially applied to the plurality of gate control signal lines 204 to display one screen.

At this time, for example, in FIG. 2, the inverted pulse signal RP1 is displayed until the (n-1) th screen after the (n-1) th field period.
(RP1 signal) is a low level voltage, and the gate-on voltage VGH is 13V. That is, the RP1 signal is controlled by the serial signal SI input to the control IC 11, and the input SI signal is initially output from the control IC 11 as a low level voltage by the serial / parallel conversion circuit 501 in the control IC 11 to control the signal. Switch 121
To turn off. Therefore, the resistance R1 causes 15
The gate-on voltage VGH, which is a voltage drop from V to 13V, is applied. Therefore, up to the n-1 screen, the gate (control terminal) of the TFT 205 via the gate control signal line 204.
Then, a voltage of 13 V is applied as the gate-on voltage VGH.

Next, when the serial signal SI is switched,
The inverted pulse signal RP1 from the control IC 11 switches from the low level voltage to the high level voltage between the n-1th screen and the nth screen after the n-1 field period of the display screen. As a result, the control switch 121 is turned on. As a result, a voltage of 10V is applied to the input VGH terminal for the gate driver 400 from the dividing portion (connection point) of the dividing resistors R1 and R2. Therefore, from the n screen, the gate (control terminal) of the TFT 205 is switched from 13V to 10V via the gate control signal line 204 as the gate-on voltage VGH.

Based on the above, a method of determining whether the liquid crystal display device 10 to be inspected is a non-defective product or a defective product in TFT characteristics will be described with reference to FIGS. 13 and 14.

A feature of the driving method of the liquid crystal display device 10 of the present invention is that the inversion pulse signal RP is obtained from the nth screen of the display screen.
By switching 1 to the high level voltage, the input VGH terminal of the gate driver 400 is switched from 13V to 10V, and as a result, the gate output voltage from the gate output buffer 402 is switched from 13V to 10V in the gate output line. Is output.

By using the liquid crystal display device 10 using this driving method, the liquid crystal display device 10 which is a good product having a normal TFT characteristic can be explained by referring to the TFT characteristic diagram of FIG. , The VGS voltage of the TFTa at the time of the gate signal line for writing the positive polarity of the video signal shown in the period (a) of FIG. 13 to the pixel electrode 201 is 8V (= 13V-5).
I) driven by V) and flowing to the pixel electrode 201 at this time
The DS current becomes IDSa8, which is a voltage value that exceeds the minimum IDS current value IDSM that allows the TFTa to sufficiently charge the pixel electrode 201 during the ON period of the TFTa. As a result, the source driver 30 is turned on within the ON period of the TFTa.
The same signal voltage as the video signal voltage output from 0 is written in the pixel electrode 201.

Even when the negative video signal shown in the period (b) of FIG. 13 is written in the pixel electrode 201, the VGS voltage becomes 13V-1V = 12V, and the ISD
Since a larger amount of current flows than when a video signal of positive polarity 5V is written, a voltage of 1V output from the source driver 300 can be written sufficiently during the ON time of the TFTa.

Next, from the n screen of the screen display, the gate-on voltage VGH is 10 V, so the period (a) in FIG.
The VGS voltage of the TFTa is driven at 5V (= 10V-5V) at the time of writing the positive polarity of the video signal indicated by the symbol to the pixel electrode 201, the IDS current flowing through the pixel electrode 201 at this time becomes IDSa5, and the TFTa is turned on. TFT within the period
The minimum IDS that a can sufficiently charge the pixel electrode 201
The value exceeds the current value IDSM. N on screen display
Similar to the first screen, the same signal voltage as the video signal voltage output from the source driver 300 is applied to the pixel electrode 201 within the ON period of the TFTa.

Further, the negative video signal is the picture element electrode 201.
Also in the period (b) of FIG.
Since the VGS voltage is 10V-1V = 9V, and the ISD current flows more than when writing a video signal of positive polarity 5V, the source driver 300 is turned on during the on-time of the TFTa.
It is also possible to sufficiently write the voltage of 1 V output from the. Therefore, the entire screen of the liquid crystal display device 10 has a uniform display screen.

On the other hand, the T of a defective product in which the TFT characteristics are shifted
A case of the liquid crystal display device 10 in which the liquid crystal panel 200 having FTb is mounted will be described.

Up to the (n-1) th screen display, the VGS voltage of the TFTb is 8V (= 13V) when the positive polarity of the video signal shown in the period (a) of FIG. 13 is written in the pixel electrode 201.
The IDS current flowing through the pixel electrode 201 at this time is IDSb8, which is less than the minimum IDS current value IDSM at which the TFTb can sufficiently charge the pixel electrode 201 during the ON period of the TFTb. Become. As a result, the voltage written in the pixel electrode 201 becomes 4.8 V, as indicated by the solid line in the waveform (c) of FIG. However, when the negative video signal shown in the period (b) of FIG. 13 is written to the pixel electrode 201, the VGS voltage is 12 V, and the TFTb can sufficiently charge the pixel electrode 201 within the ON period of the TFTb. The value exceeds the minimum IDS current value IDSM, and the current value for writing the signal voltage 1V output from the source driver 300 to the pixel electrode 201 during the ON time of the TFTb is sufficient. As a result, the voltage value written in the liquid crystal layer LC is 4.8V.
-1V = 3.8Vp-p, which is lower than the originally written voltage of 5V-1V = 4Vp-p, and a little more image than when the potential of 4Vp-p is written up to the n-1 screen of the liquid crystal display. Becomes thin.

Next, after the nth screen, the VGS voltage of the TFTb is 5V (= 10V− = 10V−) when the positive polarity of the video signal shown in the period (a) of FIG. 13 is written in the pixel electrode 201.
5D), the IDS current flowing through the picture element electrode 201 at this time becomes IDSb5, which is considerably lower than the minimum IDS current value IDSM at which the TFTb can sufficiently charge the picture element electrode 201 within the ON period of the TFTb. Become. As a result, as shown by the dotted line in the waveform (C) of FIG. 13, the voltage written in the pixel electrode 201 is 4.3 V as an example.
Becomes Further, in the case where the negative video signal shown in the period (b) of FIG. 13 is written in the pixel electrode 201,
The VGS voltage becomes 9V (= 10V-1V), and TFTb
Becomes almost the same value as the current value that can be sufficiently charged during the on-time, and the value written in the liquid crystal layer LC is 4.3V-1V =
It becomes 3.3 Vp-p, which is considerably lower than the voltage value of 3.8 Vp-p written from the first line to the (n-1) th line.

As a result, in the liquid crystal display device 10 of the defective TFTb in which the TFT characteristics are deviated, n of the screen display is displayed.
A difference in brightness occurs between the screens up to the -1st screen and the screens subsequent to the nth screen, and in the liquid crystal display device 10 having a normal TFT characteristic, the screens up to the n-1th screen and the screens subsequent to the nth screen are displayed. Since there is no difference in brightness on the screen, it is a non-defective TFTa.
With the defective TFTb whose TFT characteristics are deviated, the quality of the liquid crystal display device 10 can be easily and reliably determined by the difference in screen brightness. (Embodiment 2) FIG. 3 is a block diagram showing the main configuration of Embodiment 2 of the liquid crystal display device of the present invention. In addition,
Members having the same effects as those of FIGS. 11 and 1 are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 3, the liquid crystal display device 20 includes a liquid crystal panel 200 as an image display means, and a video signal line 203 for sequentially selecting one video signal line 203 from a plurality of video signal lines 203 and supplying each color signal of the video signal. A source driver 300 as a signal line driving means, and a plurality of gate control signal lines 2
Gate driver 400 as control signal line drive means for sequentially selecting one control signal line 204 from 04 to supply a gate control signal, control IC 21 of the control circuit including switching timing control signal generation means, and drive voltage generation means. Drive voltage generating circuit 22 as

These control IC 21 and drive voltage generating circuit 22 constitute drive voltage switching means, and the drive voltage switching means supplies TF to the source driver 300 based on the switching timing control signal from the control IC 21.
Two driving voltages for T characteristic inspection (= gate-on voltage VG
It is possible to switch between H) every frame period. Further, the drive voltage switching means, the source driver 300 and the gate driver 400 constitute an image display control means, and the image display control means conducts a TFT characteristic inspection for the TFT 205 as each pixel electrode drive element. An image is displayed on the liquid crystal panel 200 by switching between two control signal voltages (= gate-on voltage VGH) every frame period. As will be described later in detail, the predetermined time interval is a time interval that can be visually confirmed. For example, the predetermined time interval is one frame period of screen display.

The control IC 21 has an RP generation circuit 211, and the serial / parallel conversion circuit 501 and the RP generation circuit 211 constitute a switching timing control signal generation means. The switching timing control signal generating means is an inversion pulse signal R as a switching timing control signal.
P2 (hereinafter referred to as RP2 signal) is generated.

The RP generating circuit 211 outputs the vertical synchronizing signal VD.
And a control signal from the serial-parallel conversion circuit 501 is input, and an inverted pulse signal RF that is inverted every frame period is output. The inversion pulse signal RF is controlled by the serial signal SI input to the control IC 21, and when performing normal display by the serial / parallel conversion circuit 501 in the control IC 21, the inversion pulse signal RF is a low level signal as the control IC 21. Is output from.

The drive voltage switching circuit 22 includes a power supply voltage input terminal VGH1 for the gate driver (for example, the power supply voltage 15).
V) and the ground (GND), the division resistors R1 and R2 as division resistance means and the control switch 221 as switching means are connected in series (composed of a series circuit), and the division portion of the division resistors R1 and R2 is connected. The (connection point) is connected to the input VGH terminal of the gate driver 400, and the output inversion pulse signal line from the control IC 21 is connected to the control terminal 222 of the control switch 221.

More specifically, in the drive voltage generation circuit 12, the high level voltage of the inverted pulse signal RP2 (RP2 signal) which is inverted every n field periods is input to the control terminal 222 and the control switch 221 is turned on. At this time, a voltage of, for example, 10 V is applied to the input VGH terminal for the gate driver 400 from the dividing portion (connection point) of the dividing resistors R1 and R2 having a predetermined dividing ratio. In the drive voltage generation circuit 22, the low level voltage of the inversion pulse signal RP2 (RP2 signal) which is inverted every frame period is input to the control terminal 222 to control the control switch 221.
When is turned off, a voltage of, for example, 13 V is applied from the dividing portion (connection point) of the dividing resistors R1 and R2 to the input VGH terminal for the gate driver 400. As described above, the control switch 2 is controlled by the inverted pulse signal RP2.
Two driving voltages (13V and 10V in this case) for TFT inspection applied to the gate (control terminal) of the TFT 205 by continuously turning on / off 21 at one frame period.
V) can be switched at intervals of one frame period.

With the above structure, the TF of the liquid crystal panel 200 is
When determining whether the T characteristic is good or bad, the SI signal for performing good / bad determination is the serial / parallel conversion circuit 50.
1, the serial-parallel conversion circuit 501 outputs a control signal for outputting a TFT characteristic inspection signal to the RP generation circuit 211. RP generation circuit 211
A vertical synchronizing signal VD is also input to the control driving voltage switching circuit 2 and an inverted pulse signal RP2 whose polarity is inverted every frame period synchronized with the VD signal is supplied from the control IC 21.
It is output to the second input terminal 222. As a result, the control switch 221 is turned on / off every frame period, so that two drive voltages (13 V and 10 V in this embodiment) are alternately applied to the input VGH terminal. The two driving voltages are output to the output buffer 402 as a gate control signal voltage.
Is output to the gate of the TFT 205. The VGH voltage applied to the input VGH terminal is a signal having the opposite polarity synchronized with the RP2 signal as shown in FIG.

As a result, the defective TFT 20 in which the TFT characteristics are deviated when the VGH voltage is 13V and 10V, respectively.
In the liquid crystal display device 20 having No. 5, a difference in brightness occurs on the screen display, but the two driving voltages (13 V and 10 V in the present embodiment) are switched every frame period, so that flicker occurs in the eyes of the inspector. Can be confirmed easily and surely. (Embodiment 3) FIG. 5 is a block diagram showing the main configuration of Embodiment 3 of the liquid crystal display device of the present invention. In addition,
Members having the same effects as those of FIGS. 11 and 1 and 3 are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 5, the liquid crystal display device 30 includes a liquid crystal panel 200 as an image display means, and a video signal line 203 for sequentially selecting one video signal line 203 from a plurality of video signal lines 203 and supplying each color signal of the video signal. A source driver 300 as a signal line driving means, and a plurality of gate control signal lines 2
Gate driver 400 as control signal line driving means for sequentially selecting one control signal line 204 from 04 to supply a gate control signal, control IC 31 of control circuit including switching timing control signal generating means, and drive voltage generating means. Drive voltage generating circuit 32.

These control IC 31 and drive voltage generation circuit 32 constitute drive voltage switching means, and the drive voltage switching means supplies TF to the source driver 300 based on the switching timing control signal from the control IC 31.
Two driving voltages for T characteristic inspection (= gate-on voltage VG
It is possible to switch between H) for each predetermined screen position. Further, the drive voltage switching means, the source driver 300 and the gate driver 400 constitute an image display control means, and the image display control means conducts a TFT characteristic inspection for the TFT 205 as each pixel electrode drive element. An image is displayed on the liquid crystal panel 200 by switching between two control signal voltages (= gate-on voltage VGH) for each predetermined screen position. As will be described later in detail, the predetermined screen position is a screen position that can be visually confirmed, for example, the same line in the middle of one screen (one field) (for example, the intermediate line position as shown in FIG. 6).

The control IC 31 has an RP generation circuit 311, and the serial / parallel conversion circuit 501 and the RP generation circuit 311 constitute a switching timing control signal generation means. The switching timing control signal generating means is an inversion pulse signal R as a switching timing control signal.
P3 (hereinafter referred to as RP3 signal) is generated.

The RP generation circuit 311 uses the vertical synchronization signal VD.
And a control signal from the serial-parallel conversion circuit 501 is input, and an inverted pulse signal RF1 that is inverted at the same line position in the middle of one screen (one field) is output. The inversion pulse signal RF1 is controlled by the serial signal SI input to the control IC 31, and when performing normal display by the serial-parallel conversion circuit 501 in the control IC 31, the inversion pulse signal RF1 is a low level signal as the control IC 31. Is output from.

The drive voltage switching circuit 32 includes dividing resistors R1 and R2 as dividing resistor means and a control switch 221 as switching means between the input VGH terminal (for example, power supply voltage 15V) for the gate driver 400 and the ground (GND). Are connected in series (composed of a series circuit), the dividing portion (connection point) of the dividing resistors R1 and R2 is connected to the input VGH terminal of the gate driver 400, and the control switch 32
An output inversion pulse signal line from the control IC 31 is connected to the first control terminal 322.

More specifically, the drive voltage generating circuit 32 has an inversion pulse signal RP3 (RP3 signal) which is inverted every same line position in the middle of one screen (one field).
Is input to the control terminal 322 and the control switch 321 is turned on, from the dividing portion (connection point) of the dividing resistors R1 and R2 having a predetermined dividing ratio to the input VGH terminal for the gate driver 400, for example, 10V. Is applied. In addition, the drive voltage generation circuit 32
The low-level voltage of the inversion pulse signal RP3 (RP3 signal) that inverts at the same line position in the middle of one screen (one field) is input to the control terminal 322, and the control switch 3
When 21 is turned off, a voltage of, for example, 13 V is applied to the input VGH terminal for the gate driver 400 from the divided portion (connection point) of the divided resistors R1 and R2. In this way, the control switch 321 is continuously turned on / off at the same line position interval in the middle of one screen (one field) by the inversion pulse signal RP3, so that the TFT
One between two drive voltages (here, 13V and 10V) for inspecting TFT characteristics applied to the gate (control terminal) of 205
It is possible to switch for each same line position on the screen (one field). The two drive voltages for this TFT characteristic inspection are the gate-on voltage VGH applied to the gate (control terminal) of the TFT 205.

In this way, the inversion pulse signal RF1 is inverted at the same position in the middle of one screen, and the gate driver 4
The gate-on voltage VGH output from 00 switches between 13V and 10V at the same position in the middle of one screen.

With the above structure, the TF of the liquid crystal panel 200 is
When determining whether the T characteristic is good or bad, the SI signal for performing good / bad determination is the serial / parallel conversion circuit 50.
1, the serial-parallel conversion circuit 501 outputs a control signal for outputting a TFT characteristic inspection signal to the RP generation circuit 311. RP generation circuit 311
A vertical synchronizing signal VD (VD signal) is also input to
An inverted pulse signal RP3 whose polarity is switched in the middle of one screen is repeatedly output for each field. As a result, the gate high-level voltage (gate-on voltage VGH) is synchronized with the RP3 signal, and a signal having the opposite polarity is output.
In the liquid crystal display device 30 in which the TFT characteristics are deviated when the H voltage is 13 V and 10 V, a brightness difference occurs in the screen display, but the gate-on voltage V is generated at the same line position in the middle of one screen.
By switching the GH to either 13V or 10V, the gate-on voltage VG is generated at the intermediate line position in the middle of one screen.
If H is switched, it can be easily and surely confirmed visually by the brightness difference between the upper part of the display screen and the lower part of the display screen within one screen. (Embodiment 4) FIG. 7 is a block diagram showing the main configuration of Embodiment 4 of the liquid crystal display device of the present invention. In addition,
Members having the same effects as those of FIGS. 11 and 1 and FIGS. 3 and 5 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 7, the liquid crystal display device 40 includes a liquid crystal panel 200 as an image display means and a video signal line 203 for sequentially selecting one video signal line 203 from a plurality of video signal lines 203 and supplying each color signal of the video signal. A source driver 300 as a signal line driving means, and a plurality of gate control signal lines 2
Gate driver 400 as control signal line driving means for sequentially selecting one control signal line 204 from 04 to supply a gate control signal, control circuit control IC 4 including switching timing control signal generating means, and drive voltage generating means. Has a drive voltage generating circuit 42.

These control IC 41 and drive voltage generating circuit 42 constitute drive voltage switching means, and the drive voltage switching means supplies TF to the source driver 300 based on the switching timing control signal from the control IC 41.
Two driving voltages for T characteristic inspection (= gate-on voltage VG
It is possible to switch between H) for each predetermined line in one screen (one field). Further, the drive voltage switching means, the source driver 300 and the gate driver 400.
The image display control means is constituted by the image display control means, and the image display control means makes one screen (2) between two control signal voltages (= gate-on voltage VGH) for TFT characteristic inspection with respect to the TFT 205 as each pixel electrode driving element. Liquid crystal panel 2 by switching every predetermined line every predetermined screen position in one field)
The image is displayed at 00. As will be described later in detail, 1
The predetermined line on the screen (1 field) is on the number of lines that can be visually confirmed, and for example, on the screen (1 field) is on every 3 lines as shown in FIG. 8, for example.

The control IC 41 has a 1/6 frequency dividing circuit 411, and the serial / parallel converting circuits 501 and 1 /
The divide-by-six circuit 411 constitutes a switching timing control signal generating means. The switching timing control signal generating means generates an inverted pulse signal RP4 (hereinafter referred to as RP4 signal) as a switching timing control signal.

The 1/6 frequency dividing circuit 411 receives the clock signal CLG from the CLG generating circuit 502 and the control signal from the serial / parallel converting circuit 501, and receives 1 screen (1
Inverted pulse signal RF that inverts every 3 lines in the field is output. This inverted pulse signal RF is controlled by the control I
The serial-parallel conversion circuit 50 in the control IC 41 is controlled by the serial signal SI input to C41.
In the case of performing a normal display with 1, the inverted pulse signal R
F is output from the control IC 41 as a low level signal.

The drive voltage switching circuit 42 includes dividing resistors R1 and R2 as dividing resistor means and a control switch 421 as switching means between the input VGH terminal (for example, power supply voltage 15V) for the gate driver 400 and the ground (GND). Are connected in series (composed of a series circuit), the dividing portion (connection point) of the dividing resistors R1 and R2 is connected to the input VGH terminal of the gate driver 400, and the control switch 42 is connected.
An output inversion pulse signal line from the control IC 41 is connected to the first control terminal 422.

More specifically, in the drive voltage generation circuit 42, the high level voltage of the inversion pulse signal RP4 (RP4 signal) which is inverted every three lines in one screen (one field) is input to the control terminal 422. When the control switch 421 is turned on, the gate driver 40 is moved from the dividing portion (connection point) of the dividing resistors R1 and R2 having a predetermined dividing ratio.
For example, a voltage of 10 V is applied to the 0 input VGH terminal. In addition, the drive voltage generation circuit 42
When the low level voltage of the inversion pulse signal RP4 (RP4 signal) which is inverted every three lines in one screen (one field) is input to the control terminal 422 and the control switch 421 is turned off, the division unit of the division resistors R1 and R2. (Connection point)
Therefore, a voltage of 13 V, for example, is applied to the input VGH terminal for the gate driver 400. In this way, the control switch 421 is controlled by the inverted pulse signal RP4.
Is continuously turned on / off at intervals of three lines in one screen (one field), so that two drive voltages (here, 13V and 10V) for inspecting TFT characteristics applied to the gate (control terminal) of the TFT 205 are set to 1 The screen (1 field) can be switched every 3 lines. The two drive voltages for the TFT characteristic inspection are the gate-on voltage VGH applied to the gate (control terminal) of the TFT 205.
Is.

In this way, the inverted signal RF2 is inverted every three lines in one screen (one field), and the gate-on voltage VGH output from the gate driver 400 is output.
Is 13V for every 3 lines in 1 screen (1 field)
And switches between 10V.

The RP signal is controlled by the serial signal SI input to the control IC 41, and the SI signal is low when the normal display is performed by the serial parallel converter 501 in the control IC 41. It is output from the control IC 41 as a level signal, and the control switch 42
1 is turned off, and the VGH voltage is set to apply 13V.

With the above structure, the TF of the liquid crystal panel 200 is
When determining whether the T characteristic is good or bad, the signal for performing the good / bad determination is the serial / parallel conversion circuit 50.
1, the serial-parallel conversion circuit 501 outputs a control signal for causing the 1/6 frequency divider circuit 411 to output a TFT characteristic inspection signal. 1/6 frequency divider circuit 411
Is a gate clock signal CL for the gate driver 400
G is also input, and the RP4 signal obtained by dividing the CLG signal by 1/6 is input from the control IC 41 to the input terminal 422 of the control switch 421. As a result, the polarity is switched every three lines in one screen (one field), and this is repeated every field and output from the drive voltage switching circuit 42 to the input VHG terminal. The gate high level voltage (VHG voltage) is a signal which is synchronized with the RP4 signal and has a reverse polarity.

As a result, the VGH voltage applied to the input VHG terminal is switched between 13V and 10V, and T
In the liquid crystal display device 40 in which the FT characteristics are deviated, a luminance difference occurs for each predetermined line group of screen display, but the gate-on voltage VGH is 13 V for every three line groups on the display screen, for example.
By switching between 10 V and 10 V, the brightness changes every three lines in one screen, and the quality judgment of the liquid crystal display device 40 in which the TFT characteristics are deviated is easy depending on whether or not a horizontal striped pattern appears. In addition, the inspection can be performed reliably. (Embodiment 5) FIG. 9 is a diagram showing the drive timing of the gate driver and the application distribution of the gate-on voltage VGH for each display screen in Embodiment 5 of the present invention.

The gate driver 40 shown in the third embodiment.
In comparison with the output timing of 0 and the application distribution chart (FIG. 6) of the gate high level voltage (gate-on voltage 13V and 10V) on the display 1 screen, as shown in FIG.
After the m (m is a natural number; m = 6 in FIG. 9) screen, the gate-on voltage VGH within one screen is 13 V and 10 V
Set the position of the voltage application part upside down on the display screen,
The output waveform of the inverted pulse signal RP5 is set, and the RP5 signal and the VGH voltage waveform after the m-th screen are set to have opposite polarities after the m-th screen. By this,
Even when the TFT characteristic deviation occurs only in the upper part of the screen, the TFT characteristic deviation can be easily and accurately detected by reversing the application distributions of the gate high level voltages of 13V and 10V. (Embodiment 6) FIG. 10 is a block diagram showing the main configuration of Embodiment 6 of the liquid crystal display device of the present invention.

As shown in FIG. 9, the resistance R2 that divides the VGH1 voltage (for example, 15 V) in FIGS. 1, 3, 5, and 7 is changed to the variable resistance VR2 as the variable resistance means, so that the driving voltage One gate-on voltage 1
For example, 0V can be raised to 10.5V or lowered to 9.5V, and the TFT characteristic detection level can be changed.

The resistance R1 may be a variable resistance VR1 as a variable resistance means. In this case, the gate-on voltage 13V, which is the other of the drive voltages, can be changed, and the TFT characteristic detection level can be changed.

As described above, according to the first to sixth embodiments,
Since an image is displayed by switching between two gate control signal voltages (for example, 13 V and 10 V) for inspecting the TFT characteristics for each TFT 205, in the case of defective TFT characteristics, a predetermined switching time (n field period or the like) or a predetermined switching time is set. It is possible to easily and surely confirm defective products due to slight shifts in the TFT element characteristics by the lightness and darkness of the display image at each display screen position (same line position, etc.). It is not necessary to turn on and both together and take a long time to compare the brightness with a large-scale device.

In the first to sixth embodiments, the switching timing control signal generating means and the driving voltage switching means capable of controlling the switching timing between the two driving voltages are provided in the liquid crystal display device 10, 20, 30, 40, 50. Although the case where the switching timing control signal generating means and the driving voltage switching means are incorporated is provided outside the liquid crystal display device, a device characteristic pass / fail judgment device (arrows shown in FIGS. 1, 3, 5, 7, and 10) is described. It may be configured by a control IC on the A side and a drive voltage switching circuit).

Further, it may be configured to switch between two drive voltages for element inspection by manually switching from the outside.

[0109]

As described above, according to the present invention, an image is displayed by switching between two control signal voltages for inspecting the element characteristics for each picture element electrode driving element. Depending on the switching time or switching position, it is possible to easily and surely check for defective products due to slight deviations in the element characteristics, depending on the brightness of the displayed image. It is not necessary to turn on the lights together and to compare the brightness over time with a large-scale device.

The detection of the liquid crystal display device in which the element characteristics are deviated is determined by changing the control signal voltage (element driving voltage) in the middle of the display period (every n field periods) and changing the brightness of the display screen. Unlike the related art, it is not necessary to compare the brightness with a non-defective liquid crystal display device, and it is not necessary to measure the brightness of the display screen of the liquid crystal display device. For this reason, the work of judging the quality of the element characteristics is simplified and the work efficiency is improved.

The two control signal voltages (two driving voltages) output to the control signal line are, for example, 1 for each frame.
Since it is possible to switch between 3V and 10V, the display screen looks like a flicker in a liquid crystal display device in which the element characteristics are deviated, and the quality of the element characteristics can be easily and reliably determined by checking the flicker. .

Further, since the two control signal voltages (two drive voltages) output to the control signal lines are switched between 13 V and 10 V, for example, in the middle of one screen, in the liquid crystal display device in which the element characteristics are deviated, the upper part of the screen is displayed. It is possible to easily and surely judge the quality of element characteristics by the brightness difference between the
As compared with the method of switching the drive voltage (control signal voltage) within the display period, the defective element characteristics can be detected more reliably in a shorter time.

Further, in addition to switching between the two control signal voltages (two driving voltages) output to the control signal line between 1.3 V and 10 V in the middle of one screen, the control voltage is changed to 13 V within the display period. By switching the switching direction between 10V in the opposite direction, it is possible to easily and surely determine the quality of the element characteristics even when there is a slight element characteristic deviation in a part of the display screen (for example, the upper part or the lower part). You can

Furthermore, two control signal voltages (two driving voltages) are provided for each predetermined line (for example, three lines) on the display screen.
For example, in the case of a liquid crystal display device in which the element characteristics are deviated, the display brightness changes every predetermined line within one screen, which appears as a horizontal striped pattern. It is possible to easily and surely determine the quality of the element characteristics only by performing the confirmation inspection. Further, in this case, even when the element characteristics are deviated only in a part of the display screen, a portion where the element characteristics are deviated appears as a striped pattern, so that the display screen of the liquid crystal display device in which the element characteristics are deviated A part of the quality judgment can be easily and surely performed.

Furthermore, every predetermined line (for example, 3 lines)
Two control signal voltages (two drive voltages) are, for example, 13
In addition to switching between V and 10V, the switching direction (switching order) for switching between, for example, 13V and 10V is reversed in the display period, so that only a small part (several lines) of the display screen is displayed. A characteristic deviation defect can also be detected easily and surely.

Furthermore, by varying the values of the two control signal voltages (two driving voltages) to be switched, the detection level of the defective element characteristics can be favorably changed so that the display luminance difference becomes clearer.

Furthermore, in addition to the usual driving method, for example, inside the control IC having the control circuit of the liquid crystal display device built therein, a switching timing control signal generating means and a driving voltage switching means capable of controlling the switching timing between the above two driving voltages. By incorporating the device, it is possible to easily and reliably detect whether the element characteristics are good or bad due to static electricity or the like after being incorporated in a product as a liquid crystal display device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a drive timing of the gate driver of FIG. 1 and an application distribution of a gate-on voltage VGH for each display screen.

FIG. 3 is a block diagram showing a main configuration of a second embodiment of a liquid crystal display device of the present invention.

4 is a diagram showing a drive timing of the gate driver of FIG. 3 and an application distribution of a gate-on voltage VGH for each display screen.

FIG. 5 is a block diagram showing a main configuration of a liquid crystal display device according to a third embodiment of the present invention.

6 is a diagram showing a drive timing of the gate driver in FIG. 5 and an application distribution of a gate-on voltage VGH for each display screen.

FIG. 7 is a block diagram showing a main configuration of a liquid crystal display device according to a fourth embodiment of the present invention.

8 is a diagram showing a drive timing of the gate driver of FIG. 7 and an application distribution of a gate-on voltage VGH for each display screen.

FIG. 9 is a timing chart of driving the gate driver and a gate-on voltage VGH for each display screen according to the fifth embodiment of the present invention.
It is a figure which shows the application distribution of.

FIG. 10 is a block diagram showing a main configuration of a liquid crystal display device according to a sixth embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration example of a conventional active matrix type liquid crystal display device.

12 is a timing chart of each gate control signal from the gate driver of FIG.

13 is a video signal output of the source driver of FIG. 11, T
It is each signal waveform diagram of the gate clock signal CLG of FT and its drain voltage.

FIG. 14 is a TFT characteristic diagram showing the relationship between the gate / source voltage VGS and the source / drain current IDS of the TFT.

[Explanation of symbols]

10, 20, 30, 40, 50 Liquid crystal display device 200 Liquid crystal panel 201 Picture element electrode 203 Video signal line 204 Gate control signal line 205 TFT 300 Source driver 400 Gate driver 11, 21, 31, 41 Control IC 211, 311 RP generation Circuits 12, 22, 32, 42, 52 Drive voltage generation circuits 121, 221, 321, 421, 521 Control switch 501 Serial parallel conversion circuit 502 CLG generation circuit 411 1/6 frequency dividing circuit (1 / n frequency dividing circuit; n Is a natural number of 2 or more) R1, R2 Dividing resistors PR1-5 Inverted pulse signals

Claims (9)

[Claims] 1. A plurality of picture element electrodes are provided in the vicinity of respective intersections of a plurality of video signal lines and a plurality of control signal lines, respectively.
In a liquid crystal display device in which a video signal is supplied to each picture element electrode at each drive timing of each picture element electrode drive element by a control signal to display an image, a two-element test for element characteristic inspection is performed for each picture element electrode drive element. A liquid crystal display device having image display control means capable of displaying an image by switching between two control signal voltages. 2. The image display control means sequentially selects a video signal line from a plurality of video signal lines to supply a video signal, and a control signal line from a plurality of control signal lines. 2. A control signal line driving means for supplying a control signal to the control signal line driving means, and a drive voltage switching means for switching between two drive voltages for device characteristic inspection supplied to the control signal line driving means. Liquid crystal display device. 3. The drive voltage switching means includes a switching timing control signal generating means for generating a switching timing control signal, and a drive for alternately switching between the two driving voltages for the element characteristic inspection based on the switching timing control signal. The liquid crystal display device according to claim 2, further comprising a voltage generating means. 4. The drive voltage generating means has a series circuit of a dividing resistance means and a switching means, and controls the switching means in accordance with the switching timing control signal to drive the driving voltage from the dividing portion of the dividing resistance means. The liquid crystal display device according to claim 3, wherein 5. The liquid crystal display device according to claim 3, wherein the switching timing control signal generating means switches the signal level at least every n (n is a natural number) field period or n frame period of screen display. 6. The switching timing control signal generating means switches between two signal levels of the switching timing control signal within one field of screen display and switches at the same display line position for each field. Liquid crystal display device. 7. The liquid crystal display device according to claim 6, wherein there are one or a plurality of switching line positions in one field of the screen display. 8. The liquid crystal display device according to claim 6, wherein a switching direction between the two signal levels at the same display line position is set to be a reverse direction for every m (m is a natural number) field. 9. The liquid crystal display device according to claim 1, wherein at least one of the set values of the two drive voltages is variable.