JP2003202866A - Electronic sound generating device and portable equipment using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve processing efficiency by providing an external auxiliary device which assists operations of a DSP and enabling the auxiliary device to operate without being restricted by a processing function of the DSP. <P>SOLUTION: The DSP 20 is externally provided with a data storage device 70 which receives data with a bit width less than a first specified bit width (p) in order and stores them in different storage areas and an external processor 100 which reads data stored in two or more storage areas of the data storage device as data with a 2nd specified bit width (q) (q≥2p) at the same time and processes them. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic sound generator for playing music using waveform data stored in a storage device, and a portable device (eg, mobile phone, synthesizer, PDA) using the electronic sound generator. Etc.)

[0002]

2. Description of the Related Art Conventionally, as a method of generating an electronic sound using waveform data stored in a storage device, a method of designing entirely by hardware and a digital signal processing device such as DSP (digital signal processor) are used. Then, a method of performing arithmetic processing with software has been used.
In recent years, the number of simultaneous pronunciations has increased, and in order to deal with various acoustic effects, the contents of calculation and the order of calculations have become complicated. Therefore, it is becoming difficult to configure all the signal processing by hardware in view of changes in design period and processing contents.

Therefore, a method of processing by software using a digital signal processing device such as a DSP has been widely used because a complicated operation sequence can be developed as a program.

In the conventional general DSP, not only the processing of the waveform data, but also the address generation (address calculation) of the internal working memory and the waveform data are used as the calculation resources of the product-sum calculation circuit, which is the central circuit. Must be used for address generation (address operation) processing of the external memory storing The product-sum operation circuit of such a DSP is a circuit designed to execute signal processing (convolution operation such as FIR filter processing and IIR filter processing) at high speed, and is special in signal processing other than its specialty. When it is used for such an arithmetic operation (for example, a modulo arithmetic operation, a memory address generation processing such as an address jump processing, etc.), the arithmetic efficiency becomes very poor.

Therefore, in recent DSPs for audio signal processing, a circuit configuration has been proposed in which address generation processing can be performed without imposing a load on the product-sum calculation circuit. (For example, Japanese Patent Laid-Open No. 2001-242878. Hereinafter, referred to as a prior art example.)

[0006]

In this prior art example, since the address generation processing is performed inside the DSP, it is necessary to use a DSP having a built-in address generation processing circuit for an external memory. In addition, since the address generation processing is performed inside the processing, the processing function (for example, the data bit width) of the DSP is limited, and the processing efficiency is reduced. Although it is possible to improve the processing efficiency by increasing the processing frequency, the power consumption increases as the processing frequency is increased, so it should be applied to mobile devices that require small size and low power consumption. Becomes difficult.

Therefore, according to the present invention, an auxiliary circuit device for processing operations that the DSP is not good at, such as address generation processing of a memory storing waveform data, and operations that cannot effectively use the DSP is provided outside the DSP. , Improving the processing efficiency by preventing this auxiliary circuit device from being limited by the processing function (for example, data bit width) of the DSP,
It is an object of the present invention to provide an electronic sound generation device that enables the use of a general-purpose DSP and has improved processing efficiency, and a mobile device using the same.

[0008]

An electronic sound generating apparatus according to claim 1, wherein a digital signal processing means 20 including a product-sum operation circuit, and a bit width of a first predetermined bit width p or less from the digital signal processing means. Data are sequentially received and stored in a plurality of different storage areas, and data are stored in two or more storage areas of the data storage means 70 and the data storage means 70 that can simultaneously read the data from the plurality of storage areas. The data has a second predetermined bit width q (where q ≧
2p), the external processing means 100 for simultaneously reading the data, performing the required data processing based on the data, and outputting the data processing result so as to give it to the digital signal processing means 20.

According to a second aspect of the present invention, there is provided an electronic sound generating device according to the first aspect, wherein the external processing means 1 is used.
00 includes a waveform memory address calculation means 30 and a waveform storage means 40, and each data stored in the storage area of the data storage means is a parameter for calculating the address of the waveform storage means, and the waveform memory The address calculation means calculates an address of the waveform storage means based on the plurality of parameters read from the data storage means, and the waveform storage means is stored in accordance with the address from the waveform memory address calculation means. The waveform data is read out.

A portable device according to claim 3 is the portable device according to claim 1 or 2.
It is characterized by comprising the electronic sound generating device described in any one of 1.

According to the electronic sound generator of the present invention, the digital signal processing means (hereinafter referred to as DSP) including the product-sum calculation circuit.
A data storage unit 70 that sequentially receives data having a bit width equal to or smaller than a first predetermined bit width p outside 20 and stores the data in different storage regions, and two or more storage regions of the data storage unit. The data has a second predetermined bit width q
(However, q ≧ 2p) data is read out at the same time,
An external processing means 100 for processing is provided. Therefore, the external processing means uses the data bit width p used in the DSP.
The data having a larger bit width can be read in batch at the same time without being limited to, so that the arithmetic processing can be performed quickly without increasing the processing frequency.

The parameters for calculating the address of the waveform storage means are, in addition to the start address and end address,
Since the amount of data is large, including an arbitrary increment by address unit, the effect of batch reading of parameters is great.

In particular, since the data processing efficiency can be improved without increasing the processing frequency, it can be suitably used for a mobile device such as a mobile phone which requires low power consumption.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of an electronic sound generating apparatus according to the present invention will be described below with reference to FIGS.

FIG. 1 is a diagram showing the configuration of an electronic sound generator according to the present invention. The electronic sound generating apparatus of the present invention includes a system control unit 10 including a host CPU as a main constituent unit, a music signal processing DSP 20, a waveform memory address arithmetic circuit 30, a waveform memory 40 D / A converter 60.
And a storage device 70. The storage device 70 is for exchanging data between the external auxiliary device 100 including the waveform memory address calculation circuit 30 and the waveform memory 40 and the DSP 20.

First, the host CPU 10 controls each component so that the electronic sound generator performs a desired operation as a whole and appropriately generates and outputs an analog audio signal. Specifically, for example, various control commands are sent to the DSP 20 so that the DSP 20 appropriately performs desired processing.

The PCM sound source signal to be processed (hereinafter, this may be referred to as waveform data) is input to the waveform memory 40 via an input / output means (not shown), and the read-only memory (ROM). ) Is used. As this waveform data, various data for each musical instrument is stored in association with its memory address (n bits).

As shown in the internal structure of FIG. 2, the DSP 20 performs desired processing such as demodulation processing on the PCM sound source signal read from the waveform memory 40 under the control of the system controller 10. Then, a baseband digital audio signal is generated and output to the D / A converter 60.

The DSP 20 has a control unit 21, a program memory 22, a work memory address control means 23, a work memory 24, a waveform memory address control means 25, a product sum calculation circuit 26 and an external output I / F 27.

The program memory 22 is a memory for storing the processing procedure performed by the DSP 20, and the stored control programs are sequentially read by the control unit 21 in accordance with control commands. The control unit 21 controls each component of the DSP 20 so that the DSP 20 performs desired processing as a whole. Specifically, based on the control command from the system control unit 10, the processing program that executes the instruction is sequentially read from the program memory 22. Then, the address calculation parameter PA for controlling the address for accessing the data used for processing is written and held in the waveform memory address control means 25 as needed. This parameter PA has different values depending on the types of various musical instruments and scales. Then, the product-sum operation command is output to the product-sum operation circuit 26,
The desired processing is actually performed.

The address calculation parameter PA output from the waveform memory address control means 25 and held in the storage device 70 is a start address O indicating the start point of the sound source data.
FST and end address STOP indicating the end point thereof,
When repeatedly outputting, a repeat start address REST for repeating and an address unit increment PHIN indicating an address increment for determining the next sampling point.
It consists of C. Here, the increment of the address unit PH
INC may be an arbitrary integer, or may include an address below the decimal point in relation to other start addresses. Of course, it may be 1 as usual. These parameters PA are determined within the DSP 20 based on the relationship between the waveform data stored in the waveform memory 40 and the waveform data required by the DSP 20 for calculation.

The bit width of the data processed by the DSP 20 is a predetermined bit width p determined by the DSP.
(Eg, 16 bits) and therefore DSP 20
The data bit width output from the outside is also p. Start address O that constitutes the address calculation parameter PA
The FST, the end address STOP, the repeat start address REST, the increment by address unit PHINC, etc. are also sequentially output from the DSP 20 with the data bit width p or less.

The waveform memory address calculation circuit 30 receives the address calculation parameter PA and calculates the address given to the waveform memory 40. Since various parameters are used to perform this address calculation, data having a bit width q larger than the data bit width p in the DSP 20 is required.

If various parameters required for the address calculation in the waveform memory address calculation circuit 30 are set to the DSP 2
If the data bit width p is received from 0, the access is performed a plurality of times r to obtain the necessary parameter (data bit width q). In this case, the address calculation time, the reading time from the waveform memory 40, and the like are added to the access time of a plurality of r times, so that the output from the external auxiliary device 100 to the DSP 20 is delayed. As a result, the DSP 20 waits for the processing result (that is, the waveform data) from the external processing device 100, and it becomes difficult to increase the calculation amount of the entire electronic sound generating device.

In the present invention, the storage device 70 is replaced by the DSP 20.
And the waveform memory address calculation circuit 30. Moreover, the storage device 70 stores a plurality of memory areas (first memory to fifth memory) 71 to 75 capable of storing data of bit width p sequentially input from the DSP 20 and simultaneously reading the data. And a sixth memory area 76. Note that the number of these memory areas is an example number, and can be an arbitrary number as necessary. Also,
It is also possible to use different storage devices.

The relationship of the bit width in the storage device 70 is as follows.
It is organized as follows. p <q, p ≧ p1 to p5, q ≦ p1 + p2 + p3 +
p4 + p5

In the storage device 70, various address calculation parameters PA from the DSP 20 are input to and stored in the first memory 71 to the fifth memory 75 as data each having a bit width p or less at a suitable time. On the other hand, the waveform memory arithmetic circuit 30 simultaneously accesses the first memory 71 to the fifth memory 75. Then, from the stored data, all the data or the data required at that time are collectively read with the data bit width q (q ≧ 2p). Based on the read data, the required address calculation for the waveform memory 40 is performed.

The waveform data read from the waveform memory 40 in accordance with the calculated address is taken into the DSP 20 via the sixth memory 76 functioning as a buffer. The data bit width q ′ of the sixth memory 76 may be larger than p (for example, 2p), but the DSP 20
Will read this data in pieces.

The result of the waveform memory address calculation may be written in the storage device 70, and the storage device 70 may also be used.
The DSP 20 may refer to the data stored in. Therefore, the data direction can be bidirectional between the DSP 20 and the storage device 70 and between the storage device 70 and the waveform memory address operation circuit 30.

As described above, the external processing device 100 is
Since the data q having a larger bit width can be read in batch at the same time without being limited to the data bit width p used in the SP 20, the arithmetic processing can be performed quickly without increasing the processing frequency.

The operation of the waveform memory arithmetic circuit 30 is performed as follows, assuming an example having a loop portion in which a sound starts to be emitted and thereafter.

First, the start address OFST is given as the current address PHASE. Next, the increment by address unit PHINC is added to the current address PHASE to obtain the next current address PHASE. The process of adding the increment PHINC to the current address PHASE is continued.

Current address PHASE> End address S
When it becomes TOP, the end address STOP is subtracted from the current address PHASE, and the start address RE is repeated.
Add ST to obtain the new current address PHASE. Such address calculation processing is repeatedly performed.

FIG. 3 is a diagram showing another embodiment of the external auxiliary device 100. In FIG. 3, the external auxiliary device 10
A waveform data interpolation processing circuit 50 is further provided at 0.

In the embodiment of FIG. 3, the increment by increment of address unit PHINC has lower bits corresponding to the fractional part of the start address OFST and the repeating address REST. The number of bits of the address of the waveform memory 40 is n bits, and the calculated current address PHASE is a predetermined number of m bits consisting of upper n bits and lower k bits.

The upper n bits of the present address PHASE are given to the waveform storage device 40 as an address, and the lower k bits are given to the waveform data interpolation processing device 50 for interpolation processing.

In the waveform data interpolation processing circuit 50, in accordance with the value of the lower-order bit k, that is, the value below the decimal point of the address, for example, the waveform data indicated by the address of the higher-order bit n and the waveform data indicated by the next address are linearly divided. By interpolation, waveform data suitable for the current address PHASE represented by m bits (= n + k) is obtained. The interpolation method is not limited to linear interpolation, and various known interpolation methods such as a filtering method by weighting a plurality of waveform data can be adopted.

In any of the embodiments, the D / A converter 60 converts the baseband digital audio signal input from the DSP 20 into an analog signal and outputs it as an analog audio signal that can be output as audio from a speaker or the like.

In addition to the host CPU 10 and the DSP 20, the waveform memory address operation circuit 30, the waveform memory 4
0, waveform data interpolation processing circuit 50, D / A converter 60,
Each of the storage devices 70 can individually form an LSI, or an arbitrary combination thereof can be used as an LSI.
It is also possible to build in.

[0040]

According to the present invention, the external processing means is a DS
Since data having a larger bit width can be read in batch at the same time without being limited to the data bit width p used in P, the arithmetic processing can be performed quickly without increasing the processing frequency.

The parameters for calculating the address of the waveform storage means are, in addition to the start address and end address,
Since the amount of data is large, including an arbitrary increment by address unit, the effect of batch reading of parameters is great.

In particular, since the data processing efficiency can be improved without increasing the processing frequency, it can be suitably used for a mobile device such as a mobile phone which requires low power consumption.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an electronic sound generation device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an internal configuration of a DSP.

FIG. 3 is a diagram showing a configuration of an external processing device according to another embodiment.

[Explanation of symbols]

10 System control unit 20 DSP (Digital Signal Processor) 21 Control unit 22 Program memory 23 Working Memory Address Control Means 24 working memory 25 Waveform memory address control means 26 Product-sum operation circuit 27 External output I / F 30 Waveform memory address operation circuit 40 waveform memory 50 Waveform data interpolation processing circuit 60 D / A converter 70 storage device 100 external storage device

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hidetomo Tanaka             21 Ryozo Mizozaki-cho, Saiin, Ukyo-ku, Kyoto             Inside the company F term (reference) 5D378 AD12 AD13 AD22 AD33 AD42                       AD44 BB06

Claims (3)

[Claims] 1. A digital signal processing means including a product-sum calculation circuit, and a first predetermined bit width p from the digital signal processing means.
A data storage unit that sequentially receives data of the following bit widths and stores the data in a plurality of different storage regions, and that can simultaneously read data from the plurality of storage regions; and two or more storage regions of the data storage unit. The stored data is read simultaneously as data having a second predetermined bit width q (where q ≧ 2p), required data processing is performed based on the data, and the data processing result is given to the digital signal processing means. And an external processing means for outputting to the electronic sound generating device. 2. The external processing means includes a waveform memory address calculation means and a waveform storage means, and each data stored in the storage area of the data storage means is a parameter for calculating an address of the waveform storage means. The waveform memory address calculation means calculates an address of the waveform storage means based on a plurality of parameters read from the data storage means, and the waveform storage means outputs the waveform memory address calculation means from the waveform memory address calculation means. The electronic sound generating apparatus according to claim 1, wherein the stored waveform data is read according to an address. 3. A portable device comprising the electronic sound generating device according to claim 1. Description: