JP2003202353A - Waveform checking device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a waveform checking device that can check simply and quickly whether a signal waveform is abnormal or not. <P>SOLUTION: The waveform checking device is provided with a phase lock circuit 2 which generates a clock signal phase-locked with a signal obtained by bringing a probe 14 into contact with a terminal to be measured; an A/D converter 3 which samples the clock signal so as to be converted into a digital signal according to the clock signal; a memory 4 in which signal waveform data as the digital signal converted by the A/D converter 3 is stored; a processor 5 which processes the signal waveform data stored in the memory 4 and which detects an abnormality such as an overshoot, an undershoot, a waveform crack or the like in the signal waveform; an abnormality display means, with light emitting diodes 10, 11 or a buzzer, which displays the abnormality of the signal waveform detected by the processor 5; a liquid crystal panel 9 which can display the signal waveform; and a termination circuit 12 which is connected selectively by a switching circuit 13. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform check device capable of easily checking whether or not a signal waveform in various digital circuits is normal, and displaying an abnormal signal waveform by a light emitting diode or a buzzer. Regarding

[0002]

2. Description of the Related Art In various digital circuits using a large scale integrated circuit (LSI) or the like, it is required to suppress noise, and in particular, the problem of electromagnetic wave radiation is associated with an increase in operating frequency. Has occurred. Therefore, it is desired that the signal waveform in the digital circuit is normal. For example, when the signal waveform includes overshoot or undershoot, the harmonic components increase, which causes interference noise to adjacent circuits, and when the level is high, a problem of electromagnetic wave radiation occurs. Therefore, whether or not the signal waveform of each part of the digital circuit is normal is observed using a synchroscope.

In this case, the probe of the synchroscope is brought into contact with the terminal of each part of the digital circuit or the terminal of the integrated circuit to display the signal waveform, and it is determined whether the signal waveform is normal or not. If the signal waveform is not normal, design changes such as addition of circuit elements or change of wiring pattern will be made.

[0004]

To check the signal waveform in the conventional digital circuit, the probe of the synchroscope is brought into contact with the terminal of the printed circuit board or the terminal of the integrated circuit to display the signal waveform. As the circuit scale of a printed circuit board or an integrated circuit increases, the number of measurement target points increases, and there is a problem that the time required to check the signal waveform becomes extremely long. Further, a certain degree of skill is required for observing the signal waveform, and there is a problem that the quality judgment of the signal waveform varies. An object of the present invention is to easily judge the quality of a signal waveform in a digital circuit.

[0005]

The waveform checking apparatus of the present invention will be described with reference to FIG. 1. A phase synchronizing circuit 2 for generating a clock signal phase-locked with a signal taken in from a terminal to be measured, and a phase synchronizing circuit 2 An AD converter 3 for sampling the signal in accordance with the clock signal from the synchronizing circuit 2 to convert the signal into a digital signal, a memory 4 for storing signal waveform data of the digital signal converted by the AD converter 3, and a memory 4 A processor 5 for processing the stored signal waveform data to detect an abnormality of the signal waveform, and a light emitting diode 10 or 11 for detecting and displaying an abnormality of the signal waveform by the processor 5 or a buzzer abnormality display means are provided. There is.

The processor 5 also outputs a signal when the peak hold value of the high level peak hold circuit of the signal waveform data, the low level peak hold circuit, and the high level peak hold circuit exceeds the first reference voltage. A first comparator for detecting the occurrence of waveform overshoot;
A function of a second comparator for detecting occurrence of undershoot of a signal waveform when the peak hold value of the low level peak hold circuit is lower than a second reference voltage, and detection of the first and second comparators There is provided an anomaly display means composed of light emitting diodes 10 and 11 or a buzzer for displaying anomalous signal waveform by a signal.

Further, the processor 5 compares the limiter circuit for limiting the peak of the signal waveform data with the signal waveform data passed through this limiter circuit and the previous sample hold value, and in the rising process of the signal waveform, A third comparator that determines a waveform break when the signal waveform data is lower than the previous sample hold value, and a waveform break when the signal waveform data in the falling process of the signal waveform is higher than the previous sample hold value. The abnormality display means includes a light emitting diode 10 or 11 or a buzzer, which includes a function of the fourth comparator for determining that the signal waveform abnormality is detected by the detection signals of the third and fourth comparators.

Further, a transmission section such as a wireless transmission / reception section 7 for transferring the signal waveform data stored in the memory 4 to the outside under the control of the processor 5 can be provided. In addition, a probe for contacting the measurement target terminal to capture a signal is provided at the tip of the housing, and an abnormality display means consisting of a light emitting diode or a buzzer for indicating an abnormal signal waveform is provided on the surface of the housing to store the signal stored in the memory. A liquid crystal panel that displays a signal waveform based on the waveform data may be provided on the surface of the housing. Further, a probe for contacting the measurement target terminal and capturing a signal can be provided at the tip of the housing, and a termination circuit that can be selectively connected to the probe via a switch circuit can be provided.

[0009]

1 is a functional block diagram of an embodiment of the present invention, in which 1 is a buffer amplifier, 2 is a phase locked loop (PLL), 3 is an AD converter (A / D), and 4 is Memory (MEM), 5 is a processor (CPU), 6 is a control circuit (CON), 7 is a wireless transmission / reception unit, 8 is an antenna, 9 is a liquid crystal panel, 10 and 11 are light emitting diodes as abnormality display means, and 12 is a terminal. Circuit, 13 is a switch circuit, 14
Is a probe, LSI is a large-scale integrated circuit mounted on a printed circuit board, and V _CC is a power supply voltage.

At the start of the waveform check, the switch circuit 13
With the switch off, turn on the power switch of the device,
The probe 14 is brought into contact with the measurement target terminal of the digital circuit such as the terminal of the LSI, and the check start key is operated. As a result, the signal acquired from the probe 14
The signal is input to the AD converter 3 via the buffer amplifier 1 and a clock signal phase-locked with the signal is generated in the phase-locking circuit 2, and the AD converter 3 samples the signal waveform according to the clock signal. Converted into a digital signal and stored in the memory 4 as signal waveform data.
This memory 4 is, for example, a dual port memory,
Writing of the signal waveform data and reading by the processor 5 can be performed simultaneously. Probe 1 in this case
4 does not affect the operation of the measurement target terminal side,
The input impedance is usually a high interface configuration.

Further, the phase locked loop 2 can be configured to output a clock signal synchronized with the cycle of the input signal and a high speed clock signal. Thereby, not only a single signal waveform but also a repeatedly generated signal waveform is sampled in accordance with a high-speed clock signal, and it is possible to obtain signal waveform data averaged over a plurality of cycles under the control of the processor 5.

The processor 5 controls each section and processes the signal waveform data read from the memory 4 as described later to determine whether the signal waveform is normal or not, and the determination result is the control circuit 6. Transfer to. The control circuit 6 is the processor 5
When the notification from, for example, the waveform of the signal waveform is broken, the light emitting diode 11 is driven to emit light, and when the signal waveform is overshoot or undershoot, the light emitting diode 10 is driven to emit light to generate the signal waveform. Is not normal. Further, the signal waveform can be displayed on the liquid crystal panel 9 under the control of the processor 5 based on the signal waveform data stored in the memory 4. Therefore, it is possible to visually confirm the waveform when the signal waveform is abnormal. When the signal waveform is abnormal, the switch circuit 13 is turned on and the termination circuit 12 is connected. This termination circuit 12
Can have a structure in which impedance matching is performed with respect to the terminal to be measured, a filter structure, or a limiter structure. By connecting this termination circuit 12, it is checked whether the signal waveform is improved, and the wiring pattern is checked. Can be used as a material for changing or adding circuit parts.

The wireless transmission / reception unit 7 is, for example, a Bluetooth.
ooth, IEEE802.11a, IEEE802.
A standardized wireless data communication configuration such as 11b can be applied, and according to the control of the processor 5,
The signal waveform data stored in the memory 4 can be wirelessly transferred to another computer or the like via the antenna 8. Further, the wireless transmission / reception unit 7 can be a transmission unit that transfers the signal waveform data stored in the memory 4 to another computer or the like by a wire such as a local area network (LAN) under the control of the processor 5. In this case, the signal waveform data of each part of the digital circuit collected by another computer can be processed and used as the data for the circuit design. Further, the function of this waveform checking device can be accommodated in a small housing to make it portable. Further, since it can be incorporated in an in-circuit tester or a function tester, various test data can be input to the digital circuit to quickly determine the presence / absence of a signal waveform abnormality.

FIG. 2 is an explanatory diagram of the overshoot and undershoot waveform detecting section according to the embodiment of the present invention.
2 is a phase synchronization circuit (PLL), 21 is a high level peak sample hold circuit (HPSH), 22 is a low level peak sample hold circuit (LPSH), 23,
24 is a first and second comparator (COM), 25 is a NOR circuit, 10 is a light emitting diode, 14 is a probe, and 26-2.
8 is a termination circuit, 29 is a switch circuit, V _CC is a power supply voltage,
Vr1 and Vr2 represent the first and second comparison reference voltages.

The functions of the overshoot and undershoot waveform detecting sections can be realized by the processing function of the processor 5 in FIG. The phase synchronization circuit 2 corresponds to the phase synchronization circuit 2 in FIG. 1, but in FIG. 2, a clock signal is generated from the signal waveform data input to the peak sample hold circuits 21 and 22. It is shown as a configuration for reproducing. Also switch circuit 2
9 is an off state at the start of measurement.

The high level peak sample hold circuit 21 sequentially compares the high level signal waveform data,
The high-level peak value is held, and the low-level peak sample and hold circuit 22 sequentially compares the low-level signal waveform data and holds the low-level peak value.

The first comparison reference voltage Vr1 is a voltage corresponding to a high level of a normal signal waveform, and the second comparison reference voltage Vr2 is a voltage corresponding to a low level of a normal signal waveform. Then, the first comparator 23 compares the peak value held in the high-level peak sample hold circuit 21 with the first comparison reference voltage Vr1,
When the peak value is higher than the comparison reference voltage Vr1, the detection signal of "1" (high level) is sent to the NOR circuit 25 as overshoot waveform detection.

The second comparator 24 compares the peak value held in the low level peak sample hold circuit 22 with the second comparison reference voltage Vr2, and the peak value is low due to this comparison reference voltage Vr2. In this case, as the undershoot waveform detection, a “1” (high level) detection signal is sent to the NOR circuit 25.

The NOR circuit 25 includes the first and second comparators 2
When one or both of the detection signals 3 and 24 become "1" (high level), the output signal becomes "0" (low level), and the power supply voltage V _CC applied to the light emitting diode 10 causes the light emitting diode. A current flows through 10 to emit light. That is, when the light emitting diode 10 emits light, it can be displayed that overshoot or undershoot has occurred in the signal waveform at the measurement target terminal. When an overshoot or an undershoot occurs as a signal waveform abnormality, the terminating circuit 2 is switched by the switch circuit 29.
6 to 28 is connected. For example, when it is connected to the termination circuit 26 having an impedance matching function composed of a resistance network, when it is connected to the termination circuit 27 having a filter configuration including a capacitor, and when it is connected to the termination circuit 28 having a limiter function by a diode. By determining whether or not the improvement of the signal waveform can be obtained in any or all of them, it is possible to use the improvement data such as the wiring pattern on the side of the terminal to be measured.

FIG. 3 is an explanatory diagram of the waveform breakage detecting unit according to the embodiment of the present invention. The same reference numerals as those in FIGS. 1 and 2 indicate the same parts, 31 is a limiter circuit (LIM), and 32 is a sample hold circuit. (SH), 33 and 34 are third and fourth comparators (COM), and 35 and 36 are flip-flops (F
F), 37 are NOR circuits, 11 is a light emitting diode as an abnormality display means, and V _CC is a power supply voltage.

The function of the waveform breakage detecting unit can be realized by the processing function of the processor 5 in FIG. The phase-locked loop 2 corresponds to the phase-locked loop 2 in FIG. 1, but FIG. 2 shows a configuration for reproducing a clock signal from the signal waveform data input to the limiter circuit 31. There is. Also in the case of this waveform breakage detection, the switch circuit 29 is turned off at the start of the measurement.

The limiter circuit 31 removes the overshoot component and the undershoot component of the signal waveform data and inputs them to the sample hold circuit 32 and the comparators 33 and 34. The sample-hold circuit 32 has a function of sampling and holding a signal waveform of one cycle at a plurality of timings in accordance with the clock signal from the phase synchronization circuit 2 including the rising and falling periods of the signal waveform. is there.

Further, the third and fourth comparators 33 and 34 compare the input signal waveform data of this time with the previous sample hold value according to the sample hold timing.
In this embodiment, the third comparator 33 detects an abnormality in the rising edge of the signal waveform and the fourth comparator 34 detects an abnormality in the falling edge of the signal waveform. Will be described. That is, in the rising process of the signal waveform, it is normal when the signal waveform data of this time is larger than the previous sample hold value, and in the opposite case,
It can be determined that the rising process of the signal waveform is abnormal.
Similarly, in the falling process of the signal waveform, it is normal when the signal waveform data of this time is smaller than the previous sample hold value, and in the opposite case, it is judged that the falling process of the signal waveform is abnormal. I'm dying.

The third and fourth comparators 33 and 34 output "1" (high level) when it is determined to be abnormal, whereby the flip-flops 35 and 36 are set and the output terminal Q is "." 1 "(high level), the output of the NOR circuit 37 becomes" 0 "(low level), and the light emitting diode 11 emits light. Also in this case, when it is determined that the signal waveform is abnormal, it is possible to switch and connect the termination circuits 26 to 28 to the probe 14 by the switch circuit 29 and determine whether or not the signal waveform is improved.

4A and 4B are explanatory diagrams of the operation of the embodiment of the present invention. FIG. 4A shows the operation of the waveform breakage detecting section, and FIG. 4B shows the operation of the overshoot and undershoot detecting section. In FIG. 4A, assuming that the previous sample hold value is Vu1 and the current input signal waveform data is Vu2 in the rising process of the signal waveform, Vu1> Vu.
The relationship of 2 can be detected in the third comparator 33. In the falling process, the previous sample and hold value is V
If the input signal waveform data of this time is Vd2, the relationship of Vd1 <Vd2 can be detected in the fourth comparator 34. Therefore, it is possible to determine whether the waveform is a normal rising waveform or a normal falling waveform by comparing the sample hold values for each sampling period.

If one period of the signal waveform is T, and if a signal waveform shown by a dotted line occurs during that period, it means that the period is longer than the sampling period.
The waveform abnormality can be detected by one or both of the comparators 33 and 34. Such timing control can be performed based on the clock signal indicating one cycle of the signal waveform from the phase synchronization circuit 2 and the clock signal for sampling at a higher speed than that.

Further, in FIG. 4B, the first comparison reference voltage Vr1 and the peak hold value Vp1 of the high-level peak hold circuit 21 are compared by the first comparator 23, and Vp1> Vr1. In the case of the above relationship, it is determined that overshoot has occurred. Also, the peak hold value Vp2 of the low level peak hold circuit 22 and the second comparison reference voltage Vr2 are compared by the second comparator 24,
When the absolute value has a relationship of Vp2> Vr2, it is determined that undershoot has occurred.

Therefore, the light emitting diode 10 in FIG.
When the LED emits light, the signal waveform shows overshoot or undershoot, and when the light emitting diode 11 emits light, the signal waveform shows waveform breakage.
It is also possible to use a single light emitting diode as the light emitting diodes 10 and 11 to display a signal waveform abnormality. A buzzer may be provided together with the light emitting diodes 10 and 11 as an abnormality display means. Further, it is possible to provide only the buzzer so that the buzzer sounds when a signal waveform abnormality is detected. It is also possible to display the signal waveform on the liquid crystal panel 9 for examination when an abnormality in the signal waveform is detected. Further, if it is necessary to examine it in more detail, a synchroscope can be connected to the measurement target terminal as in the conventional example to perform detailed waveform observation and analysis.

FIG. 5 is a schematic perspective view of an embodiment of the present invention, in which 50 is a waveform check device, 51 is a power supply display light emitting diode, 52 is a signal waveform abnormal display light emitting diode as abnormality display means, and 53 is a signal waveform. A buzzer as an abnormality display means, 54 a liquid crystal panel, and 55 a probe.
This waveform checking device 50 shows a case where the function shown in FIG. 1 is housed in a small housing. A power switch, a measurement start button, and a switch circuit for selectively connecting the termination circuit are not shown, and one light emitting diode 52 also serves as a light emitting diode for detecting and displaying an abnormal signal waveform. The case is shown.

Further, the probe 55 is a waveform check device 50.
Can be provided at the tip of the casing to hold the terminal of the signal waveform observation target such as the pin of the large-scale integrated circuit as shown in the figure. Since various configurations are already known for such a configuration, a desired configuration can be applied. It also includes a configuration for connecting to a ground terminal (not shown).

When a power switch (not shown) is turned on, electric power is supplied to each part from an internal battery, and the light emitting diode 51 also emits light to indicate that it is in operation. Buzzer 53 again
Can be made to ring when an abnormality in the signal waveform is detected or when the signal waveform observation processing is completed. Further, the liquid crystal panel 54 can display a signal waveform based on the signal waveform data stored in the memory 4 under the control of the processor 5 (see FIG. 1). Further, as shown in FIG. 1, the wireless transmitter / receiver 7 and the antenna 8
By incorporating and, the signal waveform data and the determination result can be transferred to another computer by an operation key or the like (not shown). It is also possible to provide a terminal connected to a local area network (LAN) and transfer the signal waveform data to another computer under the control of the processor.

Every time the probe 55 is brought into contact with the signal waveform observation target terminal to observe the signal waveform, the control function of the processor 5 counts up and the count content and the signal waveform data are stored in the memory 4 in association with each other. It is also possible to store the count and associate the count content with the pin number of the integrated circuit or the like. It is also possible to display the rise time and fall time of the signal waveform displayed on the liquid crystal panel 54 based on the reference point on the time axis.

The present invention is not limited to the above-described embodiments, but various additions and changes can be made. By increasing the processing function of the processor 5, the delay between terminals of the digital circuit can be improved. It is also possible to measure time etc. Further, by incorporating the function of the waveform check described with reference to FIGS. 1 to 3 in the in-circuit tester, the function tester, etc., it is possible to quickly determine whether there is a signal waveform abnormality.

[0034]

As described above, according to the present invention, the signal waveform is checked, the signal waveform abnormality such as overshoot, undershoot, or waveform breakage is detected, and the signal waveform abnormality is displayed by the light emitting diode or the buzzer. Therefore, it is possible to quickly confirm whether the signal waveform is abnormal or normal simply by bringing the probe 14 into contact with the measurement target terminal. Therefore, in a large-scale digital circuit, even if many terminals to be measured exist, it is possible to sequentially check. Further, as shown in FIG. 5, if it is stored in a small housing, there is an advantage that it is possible to easily and quickly determine whether or not there is an abnormality in the signal waveform. Further, by selectively switching and connecting the terminating circuit 12, there is an advantage that it becomes easy to find a countermeasure against an abnormal signal waveform.

[Brief description of drawings]

FIG. 1 is a functional block diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of an overshoot and undershoot waveform detection unit according to the embodiment of this invention.

FIG. 3 is an explanatory diagram of a waveform crack detection unit according to the embodiment of this invention.

FIG. 4 is an operation explanatory diagram of the embodiment of the present invention.

FIG. 5 is a schematic perspective view of the waveform checking device according to the embodiment of the present invention.

[Explanation of symbols]

1 Buffer amplifier 2 Phase synchronization circuit (PLL) 3 AD converter (A / D) 4 memory (MEM) 5 processors (CPU) 6 Control circuit (CON) 7 Radio transceiver (TR) 8 antenna 9 LCD panel 10,11 Light emitting diode

Claims (6)

[Claims] 1. A phase synchronization circuit for generating a clock signal phase-synchronized with a signal taken in from a terminal to be measured, and an AD converter for sampling the signal in accordance with the clock signal from the phase synchronization circuit and converting the signal into a digital signal. A memory for storing the signal waveform data of the digital signal converted by the AD converter; a processor for processing the signal waveform data stored in the memory to detect an abnormality in the signal waveform; A waveform check device comprising a light emitting diode for detecting and displaying an abnormality or an abnormality display means for a buzzer. 2. A processor according to claim 2, wherein the peak hold value of the high level peak hold circuit of the signal waveform data, the low level peak hold circuit, and the high level peak hold circuit exceeds a first reference voltage. A first comparator that sometimes detects the occurrence of overshoot in the signal waveform and a second comparator that detects the occurrence of undershoot in the signal waveform when the peak hold value of the low level peak hold circuit is lower than the second reference voltage. 3. The waveform check according to claim 1, further comprising an abnormality display means including a light emitting diode or a buzzer, which includes a function of a light emitting diode or a buzzer, which indicates a signal waveform abnormality according to detection signals of the first and second comparators. apparatus. 3. The processor compares a limiter circuit that limits the peak of the signal waveform data with the signal waveform data that has passed through the limiter circuit and the previous sample hold value, and performs a rising process of the signal waveform. A third comparator that determines a waveform break when the signal waveform data in the signal waveform data is lower than the previous sample hold value, and the signal waveform data in the falling process of the signal waveform is less than the previous sample hold value. An abnormality display means including a light emitting diode or a buzzer for displaying a signal waveform abnormality by a detection signal of the third and fourth comparators, the function including a function of a fourth comparator which determines that the waveform is broken when it is high. The waveform check device according to claim 1, wherein: 4. The waveform check according to claim 1, further comprising a transmitting unit that transfers the signal waveform data stored in the memory to the outside under the control of the processor. apparatus. 5. A probe for contacting with the terminal to be measured to capture a signal is provided at the tip of the housing, and an abnormality display means including a light emitting diode or a buzzer for displaying the signal waveform abnormality is provided on the surface of the housing. 5. The waveform according to claim 1, further comprising a liquid crystal panel provided on the surface of the housing, the liquid crystal panel displaying the signal waveform based on the signal waveform data stored in the memory. Checking device. 6. A probe for contacting the measurement target terminal to capture a signal is provided at a tip of a housing, and a termination circuit is provided to the probe so as to be selectively connectable via a switch circuit. The waveform check device according to any one of claims 1 to 5.