JP2003197691A - Cof board - Google Patents
Cof boardInfo
- Publication number
- JP2003197691A JP2003197691A JP2001399856A JP2001399856A JP2003197691A JP 2003197691 A JP2003197691 A JP 2003197691A JP 2001399856 A JP2001399856 A JP 2001399856A JP 2001399856 A JP2001399856 A JP 2001399856A JP 2003197691 A JP2003197691 A JP 2003197691A
- Authority
- JP
- Japan
- Prior art keywords
- mounting area
- lead
- resist film
- film
- bare chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ベアチップが搭載
されるＣＯＦ（ｃｈｉｐ ｏｎ ｆｉｌｍ）基板に関
し、さらに詳しく言えば、ベアチップの実装領域内に引
き出されているリード電極の剥離防止技術に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a COF (chip on film) substrate on which a bare chip is mounted, and more particularly, to a technique for preventing peeling of a lead electrode drawn into a mounting area of the bare chip. .
【０００２】[0002]
【従来の技術】液晶表示素子を例にして説明すると、そ
の端子部にはＴＣＰ（ｔａｐｅ ｃａｒｒｉｅｒ ｐａ
ｃｋａｇｅ）基板などのフレキシブル基板が接続される
が、この種のフレキシブル基板には、主としてポリイミ
ドフィルム（ベースフィルム）に接着材層を介して銅箔
を貼り付けた３層基板が用いられている。2. Description of the Related Art A liquid crystal display element will be described as an example. A TCP (tape carrier pa) is provided at a terminal portion of the liquid crystal display element.
A flexible substrate such as a package (cage) substrate is connected, and a three-layer substrate in which a copper foil is mainly attached to a polyimide film (base film) via an adhesive layer is used for this type of flexible substrate.
【０００３】これに対して、ＣＯＦ基板では接着材層が
なく、ポリイミドフィルムに銅箔を直接貼り合わせた２
層構造となっている。一般的なＣＯＦ基板の厚みは、ベ
ースフィルムとしてのポリイミドフィルムが２５〜３８
μｍ，銅箔が８〜１２μｍであり、全体で５０μｍ以下
ときわめて薄い。On the other hand, the COF substrate does not have an adhesive layer, and a copper foil is directly bonded to a polyimide film.
It has a layered structure. A typical COF substrate has a thickness of 25 to 38 for a polyimide film as a base film.
μm, the copper foil is 8 to 12 μm, and is 50 μm or less in total, which is extremely thin.
【０００４】このように、ＣＯＦ基板は薄くて、軽くし
かも高いフレキシビリティを有することから、携帯電話
機を初めとして各種の電気機器に急速に採用されている
が、高温高湿環境下に置かれた場合、銅箔とベースフィ
ルムの密着力が低下し、銅箔端部から剥離が生ずること
がある。この剥離現象は、特にベアチップの実装領域内
において多く発生する。As described above, since the COF substrate is thin, light and has high flexibility, it has been rapidly adopted in various electric devices such as mobile phones, but it is placed in a high temperature and high humidity environment. In this case, the adhesive force between the copper foil and the base film is reduced, and peeling may occur from the copper foil end portion. This peeling phenomenon often occurs especially in the mounting area of the bare chip.
【０００５】すなわち、図５に示すように、ＣＯＦ基板
にはベアチップの実装領域ＭＡが設けられており、この
実装領域ＭＡ内に銅箔よりなる配線の各リード電極１１
が引き出されている。実装領域ＭＡ以外の部分は耐熱性
のコーティング材よりなるソルダレジスト膜２０で被覆
されているが、実装領域ＭＡ内では各リード電極１１は
露出状態で外気に晒される。That is, as shown in FIG. 5, a bare chip mounting area MA is provided on the COF substrate, and each lead electrode 11 of a wiring made of copper foil is provided in this mounting area MA.
Has been pulled out. The parts other than the mounting area MA are covered with a solder resist film 20 made of a heat-resistant coating material, but in the mounting area MA, each lead electrode 11 is exposed to the outside air.
【０００６】通常、電気的腐蝕対策として、銅箔上には
Ｎｉ／Ａｕのフラッシュめっきが施されているが高温高
湿環境下に長時間晒されると、図６に示すように、リー
ド電極１１がベースフィルム１０から剥がれる。この剥
がれはリード電極１１の端部から始まる。Normally, as a measure against electrical corrosion, Ni / Au flash plating is applied on the copper foil, but when exposed to a high temperature and high humidity environment for a long time, as shown in FIG. Is peeled off from the base film 10. This peeling starts from the end of the lead electrode 11.
【０００７】一旦、この剥離が生ずるとＮｉ／Ａｕのフ
ラッシュめっきは無意味なものとなり、剥離した銅箔に
水分が付着し、かつ、通電時において隣接するリード電
極との間に大きな電位差がある場合には、剥離した銅箔
面が電気化学的反応によって腐蝕し、場合によっては腐
蝕の進行により銅のマイグレーションが発生し、隣接リ
ード電極間が短絡してしまうことがある。Once this peeling occurs, the Ni / Au flash plating becomes meaningless, moisture adheres to the peeled copper foil, and there is a large potential difference between the adjacent lead electrodes during energization. In some cases, the peeled copper foil surface may be corroded by an electrochemical reaction, and in some cases, the migration of copper may occur due to the progress of corrosion, resulting in a short circuit between adjacent lead electrodes.
【０００８】なお、実装領域ＭＡにＬＳＩなどのベアチ
ップを例えば異方性導電フィルム（ＡＣＦ）を介して実
装したのち、そのベアチップ全体を保護樹脂で被覆して
も、それ以前にリード電極１１の端部に剥離が発生して
いる場合には、保護樹脂による効果は見られない。Even if a bare chip such as an LSI is mounted on the mounting area MA via an anisotropic conductive film (ACF) and then the entire bare chip is covered with a protective resin, the end of the lead electrode 11 is not covered yet. When peeling occurs in the part, the effect of the protective resin is not seen.
【０００９】また、リード電極間の距離を広げることに
より、リード電極間での電気化学反応の進行をある程度
抑えることができるが、これはベアチップ側の仕様であ
るＬＳＩバンプのファインピッチ化の要求に逆行するこ
とになり、現実的な解決策とは言えない。Further, by increasing the distance between the lead electrodes, the progress of the electrochemical reaction between the lead electrodes can be suppressed to some extent, but this is a requirement for fine pitch LSI bumps, which is a specification on the bare chip side. It goes backwards and is not a realistic solution.
【００１０】[0010]
【発明が解決しようとする課題】したがって、本発明の
課題は、ＣＯＦ基板のベアチップ実装領域に露出されて
いるリード電極の剥離を確実に防止することができる実
用的な技術を提供することにある。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a practical technique capable of reliably preventing peeling of the lead electrode exposed in the bare chip mounting region of the COF substrate. .
【００１１】[0011]
【課題を解決するための手段】上記課題を解決するた
め、本発明は、ベースフィルムの少なくとも片面に直接
的に貼り合わされた銅箔を所定形状にパターニングして
なる複数の配線を有し、その配線の各リード電極をベア
チップの実装領域内に引き出し、上記実装領域以外の部
分をレジスト膜にて被覆してなるＣＯＦ基板において、
上記実装領域内に露出されている上記各リード電極の端
部を被覆するように、上記ベースフィルム上に形成され
たリード剥離防止用レジスト膜を備えていることを特徴
としている。In order to solve the above-mentioned problems, the present invention has a plurality of wirings formed by patterning a copper foil directly bonded to at least one surface of a base film into a predetermined shape. In a COF substrate in which each lead electrode of the wiring is drawn out into the mounting area of the bare chip, and a portion other than the mounting area is covered with a resist film,
It is characterized in that a lead peeling prevention resist film formed on the base film is provided so as to cover the end portions of the lead electrodes exposed in the mounting region.
【００１２】実装領域以外の部分を被覆するレジスト膜
とリード剥離防止用レジスト膜は同一の耐熱性コーティ
ング材からなることが好ましく、例えばポリイミド系，
エポキシ系，ウレタン系などから選択される。It is preferable that the resist film covering the portion other than the mounting region and the resist film for preventing lead peeling are made of the same heat-resistant coating material.
It is selected from epoxy type and urethane type.
【００１３】また、形成方法としては、レジストインク
を用いるスクリーン印刷法や、感光性レジストインクも
しくは感光性フィルムを用いるフォトリソ法などがある
が、リード剥離防止用レジスト膜の形成には高精度な位
置制御が要求されることから、フォトリソ法が好まし
い。Further, as a forming method, there are a screen printing method using a resist ink, a photolithography method using a photosensitive resist ink or a photosensitive film, and the like. The photolithography method is preferable because control is required.
【００１４】[0014]
【発明の実施の形態】次に、図１ないし図３を参照し
て、本発明の実施形態について説明する。図１はこのＣ
ＯＦ基板におけるベアチップ実装領域ＭＡの部分を示す
先の図５と同様の平面図、図２はその要部拡大平面図、
図３は図２のＡ−Ａ線断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described with reference to FIGS. Figure 1 is this C
FIG. 2 is a plan view similar to FIG. 5 showing the bare chip mounting area MA on the OF substrate, and FIG.
FIG. 3 is a sectional view taken along the line AA of FIG.
【００１５】このＣＯＦ基板においても、ベアチップ実
装領域ＭＡ以外はソルダレジスト膜２０にて被覆され、
ベアチップ実装領域ＭＡ内には銅箔を所定にパターニン
グしてなる配線の各リード電極１１が引き出されてい
る。図示しないが、銅箔上には上記従来例と同じくＮｉ
／Ａｕのフラッシュめっきが施されていてよい。Also in this COF substrate, the area other than the bare chip mounting area MA is covered with the solder resist film 20,
In the bare chip mounting area MA, each lead electrode 11 of a wiring formed by patterning a copper foil in a predetermined pattern is drawn out. Although not shown in the figure, Ni is formed on the copper foil in the same manner as in the conventional example.
/ Au may be flash plated.
【００１６】この実施形態によると、各リード電極１１
は上記従来例よりも０．４ｍｍ長くされており、それら
の各端部１１ａに跨ってリード剥離防止用レジスト膜２
１が形成されている。According to this embodiment, each lead electrode 11
Is 0.4 mm longer than that of the above-mentioned conventional example, and the lead peeling prevention resist film 2 is formed across the respective end portions 11a.
1 is formed.
【００１７】具体的数値をもって説明すると、この例に
おいて、リード剥離防止用レジスト膜２１は幅０．５ｍ
ｍの帯状であり、各リード電極１１の端部１１ａをその
先端から０．３ｍｍ入ったところまで被覆している。Describing with specific numerical values, in this example, the lead peeling prevention resist film 21 has a width of 0.5 m.
Each of the lead electrodes 11 covers the end portion 11a of the lead electrode 11 up to 0.3 mm from the tip.
【００１８】したがって、リード剥離防止用レジスト膜
２１がポリイミドからなるベースフィルム１０と密着し
ている部分は、各リード電極１１の端部１１ａの間と、
その端部１１ａから０．２ｍｍ先に出た部分である。Therefore, the portions where the lead peeling prevention resist film 21 is in close contact with the base film 10 made of polyimide are between the end portions 11a of the lead electrodes 11, and
This is a portion 0.2 mm ahead of the end 11a.
【００１９】リード剥離防止用レジスト膜２１の厚み
は、一般的な銅箔の厚みが８〜１５μｍで、また、リー
ド電極１１上に載せられる図示しないＬＳＩチップのバ
ンプの高さが１５〜２０μｍであることから、１０〜２
０μｍの範囲から選択されることが好ましい。Regarding the thickness of the resist film 21 for preventing lead peeling, the thickness of a general copper foil is 8 to 15 μm, and the height of bumps of an LSI chip (not shown) mounted on the lead electrodes 11 is 15 to 20 μm. Because there is, 10-2
It is preferably selected from the range of 0 μm.
【００２０】リード剥離防止用レジスト膜２１はソルダ
レジスト膜２０と同一の耐熱性コーティング材にて形成
されることが好ましく、そのコーティング材としてはポ
リイミド系，エポキシ系，ウレタン系などが使用可能あ
る。The lead peeling prevention resist film 21 is preferably formed of the same heat-resistant coating material as the solder resist film 20, and as the coating material, polyimide series, epoxy series, urethane series or the like can be used.
【００２１】また、リード剥離防止用レジスト膜２１は
ソルダレジスト膜２０と同一の工程で形成されることが
好ましい。その形成方法には、レジストインクを用いる
スクリーン印刷法や、感光性レジストインクもしくは感
光性フィルムを用いるフォトリソ法などがあるが、リー
ド剥離防止用レジスト膜２１はＬＳＩチップのバンプ付
近に配置される関係上、高精度な位置制御が要求される
ことから、フォトリソ法が好ましい。The lead peeling prevention resist film 21 is preferably formed in the same step as the solder resist film 20. The forming method includes a screen printing method using a resist ink, a photolithography method using a photosensitive resist ink or a photosensitive film, and the like. The lead peeling prevention resist film 21 is arranged near the bumps of the LSI chip. In addition, the photolithography method is preferable because high-precision position control is required.
【００２２】なお、上記実施形態では、ベアチップ実装
領域ＭＡをベースフィルム１０の片側に設けているが、
本発明は、これに限定されるものではなく、ベアチップ
実装領域ＭＡをベースフィルム１０の両面に設ける場合
にも、当然に適用可能であることを理解されたい。Although the bare chip mounting area MA is provided on one side of the base film 10 in the above embodiment,
It should be understood that the present invention is not limited to this, and is naturally applicable to the case where the bare chip mounting areas MA are provided on both surfaces of the base film 10.
【００２３】[0023]
【実施例】次に、実際に行った本発明の実施例１とその
比較例１について説明する。双方の例ともに、リード電
極１１の形状は図４に示すように、上辺１０μｍ，底辺
２０μｍの二等辺台形で、リード電極１１，１１間の間
隔は１８μｍとした。また、ベースフィルム（ポリイミ
ドフィルム）１０の厚みは２５μｍ，銅箔の厚みは１２
μｍで、その上に０．５〜３．０μｍのニッケルめっき
を形成した後、０．０５〜０．１μｍの金めっきを施し
た。EXAMPLES Next, Example 1 of the present invention and Comparative Example 1 which were actually carried out will be described. In both examples, as shown in FIG. 4, the shape of the lead electrode 11 was an isosceles trapezoid having an upper side of 10 μm and a bottom side of 20 μm, and the interval between the lead electrodes 11 and 11 was 18 μm. The thickness of the base film (polyimide film) 10 is 25 μm, and the thickness of the copper foil is 12 μm.
.mu.m, 0.5-3.0 .mu.m nickel plating was formed thereon, and then 0.05-0.1 .mu.m gold plating was applied.
【００２４】（実施例１） 厚み２０μｍのエポキシ系
リード剥離防止用レジスト膜２１を各リード電極１１，
１１の端部に沿って形成し、そのリード剥離防止用レジ
スト膜２１にて各リード電極１１，１１の端部を０．３
ｍｍの範囲にわたって被覆した。各リード電極１１，１
１間にＤＣ１２Ｖの電位差をかけて、６０℃，相対湿度
９０％の高温高湿度環境下に５００時間放置しても、各
リード電極１１，１１に剥離は見られず、また、電気化
学的腐蝕も生じなかった。Example 1 An epoxy-based lead peeling-preventing resist film 21 having a thickness of 20 μm was formed on each lead electrode 11,
11 is formed along the end portions of the lead electrodes 11 and the lead peeling prevention resist film 21 is used to form the end portions of the lead electrodes 11, 11 by 0.3.
Coated over a range of mm. Each lead electrode 11,1
No peeling was observed on each of the lead electrodes 11 and 11, even if a potential difference of DC12V was applied between them for 500 hours in a high temperature and high humidity environment of 60 ° C. and a relative humidity of 90%, and electrochemical corrosion was observed. Also did not occur.
【００２５】（比較例１） リード剥離防止用レジスト
膜２１を形成することなく、各リード電極１１，１１間
にＤＣ１２Ｖの電位差をかけて、上記実施例１と同じく
６０℃，相対湿度９０％の高温高湿度環境下に５００時
間放置したところ、２５０時間経過後にリード電極１１
の端部に剥離が起こり、電気化学的腐蝕が発生した。そ
の後、腐蝕は端部から中央部にまで進行し、５００時間
経過後には広範囲にわたって腐蝕が認められた。(Comparative Example 1) A DC12V potential difference was applied between the lead electrodes 11 without forming the lead peeling prevention resist film 21. When left in a high temperature and high humidity environment for 500 hours, the lead electrode 11 is left after 250 hours.
Peeling occurred at the end of the and electrochemical corrosion occurred. After that, the corrosion progressed from the edge to the center, and after 500 hours, the corrosion was observed over a wide area.
【００２６】[0026]
【発明の効果】以上説明したように、本発明によれば、
ベースフィルムの少なくとも片面に直接的に貼り合わさ
れた銅箔を所定形状にパターニングしてなる複数の配線
を有し、その配線の各リード電極をベアチップの実装領
域内に引き出し、上記実装領域以外の部分をレジスト膜
にて被覆してなるＣＯＦ基板において、上記実装領域内
に露出されている上記各リード電極の端部を被覆するよ
うに、上記ベースフィルム上にリード剥離防止用レジス
ト膜を形成したことにより、ＣＯＦ基板のベアチップ実
装領域に露出しているリード電極の剥離を確実に防止し
得る実用的な技術が提供される。As described above, according to the present invention,
It has a plurality of wirings formed by patterning a copper foil directly attached to at least one surface of the base film into a predetermined shape, and each lead electrode of the wirings is drawn out into the mounting area of the bare chip, and a portion other than the mounting area In a COF substrate obtained by coating with a resist film, a lead peeling prevention resist film is formed on the base film so as to cover the end portions of the lead electrodes exposed in the mounting area. As a result, a practical technique capable of reliably preventing peeling of the lead electrode exposed in the bare chip mounting region of the COF substrate is provided.
【図１】本発明によるＣＯＦ基板におけるベアチップ実
装領域の部分を示す平面図。FIG. 1 is a plan view showing a portion of a bare chip mounting area in a COF substrate according to the present invention.
【図２】上記ベアチップ実装領域の要部拡大平面図。FIG. 2 is an enlarged plan view of an essential part of the bare chip mounting area.
【図３】図２のＡ−Ａ線拡大断面図。3 is an enlarged cross-sectional view taken along the line AA of FIG.
【図４】本発明による実施例と比較例を示したリード電
極の断面図。FIG. 4 is a sectional view of a lead electrode showing an example according to the present invention and a comparative example.
【図５】従来例のＣＯＦ基板におけるベアチップ実装領
域の部分を示す平面図。FIG. 5 is a plan view showing a portion of a bare chip mounting area in a conventional COF substrate.
【図６】上記従来例の一部拡大断面図。FIG. 6 is a partially enlarged sectional view of the conventional example.
１１ リード電極 １１ａ リード電極の端部 ２０ ソルダレジスト ２１ リード剥離防止用レジスト膜 11 Lead electrode 11a End of lead electrode 20 Solder resist 21 Lead peeling prevention resist film
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 2H092 GA50 GA51 MA15 NA11 NA27 NA29 PA06 5C094 AA31 BA01 BA43 CA19 DB10 FB15 HA08 5F044 MM24 MM25 MM48 5G435 AA14 BB12 CC09 EE42 HH14 LL06 LL07 LL08 ─────────────────────────────────────────────────── ─── Continued front page F-term (reference) 2H092 GA50 GA51 MA15 NA11 NA27 NA29 PA06 5C094 AA31 BA01 BA43 CA19 DB10 FB15 HA08 5F044 MM24 MM25 MM48 5G435 AA14 BB12 CC09 EE42 HH14 LL06 LL07 LL08
Claims (2)
的に貼り合わされた銅箔を所定形状にパターニングして
なる複数の配線を有し、その配線の各リード電極をベア
チップの実装領域内に引き出し、上記実装領域以外の部
分をレジスト膜にて被覆してなるＣＯＦ基板において、 上記実装領域内に露出されている上記各リード電極の端
部を被覆するように、上記ベースフィルム上に形成され
たリード剥離防止用レジスト膜を備えていることを特徴
とするＣＯＦ基板。1. A base film having a plurality of wirings formed by patterning a copper foil directly attached to at least one surface thereof into a predetermined shape, each lead electrode of the wirings being drawn out into a mounting area of a bare chip, In a COF substrate formed by coating a portion other than the mounting area with a resist film, the lead peeling formed on the base film so as to cover the end portions of the lead electrodes exposed in the mounting area. A COF substrate comprising a resist film for prevention.
光性レジストインクもしくは感光性フィルムからなる請
求項１に記載のＣＯＦ基板。2. The COF substrate according to claim 1, wherein the lead peeling prevention resist film comprises a photosensitive resist ink or a photosensitive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001399856A JP2003197691A (en) | 2001-12-28 | 2001-12-28 | Cof board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001399856A JP2003197691A (en) | 2001-12-28 | 2001-12-28 | Cof board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003197691A true JP2003197691A (en) | 2003-07-11 |
Family
ID=27604711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001399856A Withdrawn JP2003197691A (en) | 2001-12-28 | 2001-12-28 | Cof board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003197691A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010114159A (en) * | 2008-11-04 | 2010-05-20 | Meijo Univ | Light emitting device and method of manufacturing the same |
-
2001
- 2001-12-28 JP JP2001399856A patent/JP2003197691A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010114159A (en) * | 2008-11-04 | 2010-05-20 | Meijo Univ | Light emitting device and method of manufacturing the same |
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