JP2003195339A - Liquid crystal display panel - Google Patents

Liquid crystal display panel

Info

Publication number
JP2003195339A
JP2003195339A JP2001399267A JP2001399267A JP2003195339A JP 2003195339 A JP2003195339 A JP 2003195339A JP 2001399267 A JP2001399267 A JP 2001399267A JP 2001399267 A JP2001399267 A JP 2001399267A JP 2003195339 A JP2003195339 A JP 2003195339A
Authority
JP
Japan
Prior art keywords
electrode
arrester
substrate
electrode substrate
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001399267A
Other languages
Japanese (ja)
Other versions
JP3921386B2 (en
Inventor
Masayuki Kato
正行 加藤
Hiroyoshi Yanagi
裕喜 柳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Seiki Co Ltd
Kyocera Display Corp
Original Assignee
Nippon Seiki Co Ltd
Kyocera Display Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Seiki Co Ltd, Kyocera Display Corp filed Critical Nippon Seiki Co Ltd
Priority to JP2001399267A priority Critical patent/JP3921386B2/en
Publication of JP2003195339A publication Critical patent/JP2003195339A/en
Application granted granted Critical
Publication of JP3921386B2 publication Critical patent/JP3921386B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To make an arrester electrode ready to effectively operate without requiring high precision for relative positioning between two electrode substrates. <P>SOLUTION: A liquid crystal display panel is constituted by: connecting a layout wire 12 on the side of one electrode substrate 10 which is formed in a non-display area at the circumferential part of a seal material 30 and a dummy electrode 22 which is formed on the side of the other electrode substrate 20 opposite to it through conductive particles in the seal material; and providing the electrode substrates 10 and 20 with external electrodes 13 and 23 which are led into a seal material coated area from a substrate end surface and form arrester electrodes with an end part 12a of the layout wire and an end part 22a of the dummy electrode. The arrester electrodes P10a and P20a of the respective electrode substrates are shaped in a Λ shape which have abutting vertexes 12g and 13g, and 22g and 23g facing at one side of a boltlike pattern, and the arrester electrode P10a of one electrode substrate side and the arrester electrode P20a of the other electrode substrate side are arranged in opposite directions. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、液晶表示パネルに
関し、さらに詳しく言えば、静電気に起因する表示ムラ
を可及的に低減し得る静電気放電手段(アレスター電
極)を備えた液晶表示パネルに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel, and more particularly to a liquid crystal display panel provided with electrostatic discharge means (arrester electrodes) capable of reducing display unevenness caused by static electricity as much as possible. Is.

【0002】[0002]

【従来の技術】図3に示すように、液晶表示パネルは、
表示電極11が形成された第1電極基板10と、上記表
示電極11と対向する表示電極21を有する第2電極基
板20とを例えばエポキシ系のシール材30を介して圧
着してなる。
2. Description of the Related Art As shown in FIG.
The first electrode substrate 10 having the display electrodes 11 formed thereon and the second electrode substrate 20 having the display electrodes 21 facing the display electrodes 11 are pressure-bonded to each other with an epoxy-based sealing material 30 interposed therebetween.

【0003】その場合、表示電極11と表示電極21と
が実質的に対向している部分が実際の表示に寄与する表
示領域Aであり、シール材30の周辺部分は対向する表
示電極が存在しない非表示領域Bであって、例えば表示
電極の引き回し配線などが形成される。
In this case, the portion where the display electrode 11 and the display electrode 21 substantially face each other is the display region A which contributes to the actual display, and the peripheral portion of the sealing material 30 does not have the display electrodes which face each other. In the non-display area B, for example, the lead wiring of the display electrode is formed.

【0004】設計の都合上、非表示領域Bには引き回し
配線が存在する部分と存在しない部分とができる場合が
ある。そうすると、表示領域Aと非表示領域Bのギャッ
プが異なり、これが原因で表示領域Aと非表示領域Bと
で背景色に差が出てしまうことがある。
For the sake of design, the non-display area B may have a portion where the lead wiring exists and a portion where the lead wiring does not exist. Then, the gap between the display area A and the non-display area B is different, which may cause a difference in the background color between the display area A and the non-display area B.

【0005】そこで、非表示領域Bにおいて、例えば第
1電極基板10には引き回し配線12があるが、第2電
極基板20にはその引き回し配線12と対向するものが
ない場合には、図3に例示するように、第2電極基板2
0に第1電極基板10側の引き回し配線12と対向する
ダミー電極22を形成し、表示領域Aと非表示領域Bの
双方のギャップの均一化を図るようにしている。
Therefore, in the non-display area B, for example, when the first electrode substrate 10 has the lead wiring 12 but there is no second electrode substrate 20 facing the lead wiring 12, FIG. As illustrated, the second electrode substrate 2
The dummy electrode 22 facing the lead wiring 12 on the side of the first electrode substrate 10 is formed at 0 to make the gaps of both the display area A and the non-display area B uniform.

【0006】この場合、引き回し配線12とダミー電極
22とを同電位として非表示領域B内で液晶が駆動され
ないようにする必要がある。そのため、シール材30内
にトランスファ材としての導電性粒子を含ませて、引き
回し配線12とダミー電極22とを導通させるようにし
ている。
In this case, it is necessary to set the routing wiring 12 and the dummy electrode 22 to the same potential so that the liquid crystal is not driven in the non-display area B. Therefore, conductive particles as a transfer material are included in the sealing material 30 so that the routing wiring 12 and the dummy electrode 22 are electrically connected.

【0007】ところで、液晶表示パネルの製造に際して
は、種々の工程で静電気が発生しパネルを帯電させる
が、偏光膜の貼り付け時の帯電量がもっとも多いと言わ
れており、その帯電量によっては表示領域A内の表示電
極間で放電が発生し、その部分の配向制御膜を破壊した
り、表示電極の断線を引き起こすことがある。
By the way, in manufacturing a liquid crystal display panel, static electricity is generated in various steps to charge the panel, but it is said that the amount of charge when the polarizing film is attached is the largest, and depending on the amount of charge, Discharge may occur between the display electrodes in the display area A, destroying the alignment control film in that portion, or breaking the display electrodes.

【0008】これを防止するため、この従来例において
は、シール材30の塗布領域内にアレスター電極を設け
て静電気を放電させるようにしている。その構成を図4
の斜視図に示す。
In order to prevent this, in this conventional example, an arrester electrode is provided in the application area of the sealing material 30 to discharge static electricity. The structure is shown in FIG.
Is shown in the perspective view of FIG.

【0009】アレスター電極は第1電極基板10と第2
電極基板20の双方に設けられる。すなわち、第1電極
基板10と第2電極基板20ともに、その基板端面10
a,20a側から外部電極13,23がシール材30の
塗布領域内にまで引き込まれる。
The arrester electrode includes a first electrode substrate 10 and a second electrode substrate 10.
It is provided on both of the electrode substrates 20. That is, both the first electrode substrate 10 and the second electrode substrate 20 have their substrate end faces 10
The external electrodes 13 and 23 are drawn into the application area of the sealing material 30 from the a and 20a sides.

【0010】外部電極13は、第1電極基板10側に形
成されている引き回し配線12の端部との間でアレスタ
ー電極P10を形成する。同様に、外部電極23は、第
2電極基板20側に形成されているダミー電極22との
間でアレスター電極P20を形成する。
The external electrode 13 forms an arrester electrode P10 with the end portion of the lead wiring 12 formed on the first electrode substrate 10 side. Similarly, the external electrode 23 forms an arrester electrode P20 with the dummy electrode 22 formed on the second electrode substrate 20 side.

【0011】図5(a)の平面図を併せて参照して、ア
レスター電極P10は外部電極13の端部13aと引き
回し配線12の端部12aとを、また、アレスター電極
P20は外部電極23の端部23aとダミー電極22の
端部22aとをそれぞれ山形の尖鋭突起状として対向的
に突き合わせてなる。
Referring also to the plan view of FIG. 5A, the arrester electrode P10 includes the end portion 13a of the external electrode 13 and the end portion 12a of the leading wiring 12, and the arrester electrode P20 includes the external electrode 23. The end portion 23a and the end portion 22a of the dummy electrode 22 are formed as chevron-shaped sharp projections and face each other.

【0012】各アレスター電極P10,P20の電極間
ギャップは、引き回し配線12およびダミー電極22の
線間幅よりも狭いことがアレスターとしての必須条件で
あり、例えば5〜10μmに設定される。これにより、
例えば、偏光膜の貼り付け時に静電気が大きく帯電され
た場合、アレスター電極P10,P20のいずれかが有
効に働いて、シール材30の塗布領域内で静電気が放電
される。
It is an essential condition for the arrester that the inter-electrode gap between the arrester electrodes P10 and P20 is narrower than the line width between the lead wiring 12 and the dummy electrode 22, and is set to, for example, 5 to 10 μm. This allows
For example, when static electricity is greatly charged when the polarizing film is attached, one of the arrester electrodes P10 and P20 works effectively, and the static electricity is discharged in the application area of the sealing material 30.

【0013】[0013]

【発明が解決しようとする課題】引き回し配線12とそ
のダミー電極22は、シール材30内の導電性粒子を介
して導通がとられるため、各アレスター電極P10,P
20は、図5(a)の平面図に示すように、いずれか一
方が、いずれか他方の投影面積内に配置されることにな
る。すなわち、上下に重ねられた関係となる。
Since the lead-out wiring 12 and the dummy electrode 22 therefor are electrically connected through the conductive particles in the sealing material 30, the arrester electrodes P10, P are provided.
As shown in the plan view of FIG. 5A, one of 20 is arranged within the projected area of the other. That is, the relationship is such that they are vertically stacked.

【0014】したがって、第1電極基板10と第2電極
基板20とを圧着する際、それらの間にアレスター電極
間ギャップ方向に相対的な位置ずれが生ずると、図5
(b)の平面図に示すように、例えば第2電極基板20
側の外部電極23と第1電極基板10側の引き回し配線
12とがシール材30内の導電性粒子を介して電気的に
接続されてしまうことになる。
Therefore, when the first electrode substrate 10 and the second electrode substrate 20 are pressure-bonded to each other, if a relative displacement occurs between them in the gap direction between the arrester electrodes, FIG.
As shown in the plan view of (b), for example, the second electrode substrate 20
Therefore, the external electrode 23 on the side and the leading wiring 12 on the side of the first electrode substrate 10 are electrically connected via the conductive particles in the sealing material 30.

【0015】これは、第1電極基板10側の引き回し配
線12が、第2電極基板20側の外面に露出することを
意味し、その後の製品使用時などにおいて、第2電極基
板20の外部電極23が他の電気的導体に接触した場合
には、表示外乱を起こす原因となる。
This means that the lead-out wiring 12 on the first electrode substrate 10 side is exposed on the outer surface on the second electrode substrate 20 side, and the external electrode of the second electrode substrate 20 is used when the product is used thereafter. When 23 contacts another electric conductor, it causes a display disturbance.

【0016】これを防止するには、別の見方をすれば、
第1電極基板10と第2電極基板20とを貼り合わせる
際の位置決め精度に、アレスター電極P10,P20の
電極間ギャップである5〜10μmよりも高精度が要求
されることになる。
To prevent this, from another viewpoint,
The positioning accuracy when the first electrode substrate 10 and the second electrode substrate 20 are bonded together is required to be higher than the interelectrode gap of the arrester electrodes P10 and P20 of 5 to 10 μm.

【0017】したがって、本発明の課題は、2枚の電極
基板間の相対的な位置決めに高精度を要求されることな
く、アレスター電極を有効に動作させる技術を提供する
ことにある。
Therefore, an object of the present invention is to provide a technique for effectively operating an arrester electrode without requiring high precision in relative positioning between two electrode substrates.

【0018】[0018]

【課題を解決するための手段】上記課題を解決するた
め、本発明は、第1電極基板と第2電極基板とをシール
材を介して圧着してなり、そのセルギャップ内における
上記シール材の周辺部分の非表示領域内の上記第1電極
基板側に表示電極の引き回し配線が形成され、上記非表
示領域内の上記第2電極基板側には上記引き回し配線と
対向するダミー電極が形成されているとともに、上記引
き回し配線と上記ダミー電極とが上記シール材に含まれ
ているトランスファ材にて導通されており、上記電極基
板の各々に、基板端面から上記シール材塗布領域内に引
き込まれ、上記引き回し配線の端部および上記ダミー電
極の端部との間で、それぞれアレスター電極を形成する
外部電極が設けられている液晶表示パネルにおいて、上
記各電極基板のアレスター電極がともに、帯状パターン
の一方の辺側に互いに対向する突き合わせ頂点を持ち、
他方の辺に向けて漸次間隔が広くなるハ字状電極からな
り、上記第1電極基板側のアレスター電極と上記第2電
極基板側のアレスター電極とが逆向きに配置されている
ことを特徴としている。
In order to solve the above-mentioned problems, the present invention comprises a first electrode substrate and a second electrode substrate which are pressure-bonded to each other with a sealing material interposed therebetween. Display wirings for the display electrodes are formed on the side of the first electrode substrate in the non-display area of the peripheral portion, and dummy electrodes facing the wirings are formed on the side of the second electrode substrate in the non-display area. In addition, the lead wiring and the dummy electrode are conducted by a transfer material included in the seal material, and each of the electrode substrates is drawn from the substrate end surface into the seal material application region, In a liquid crystal display panel in which external electrodes that form arrester electrodes are respectively provided between the ends of the lead-out wiring and the ends of the dummy electrodes, the array of each electrode substrate is arranged. Both Tha electrode has a vertex abutting face each other on one side of the band-shaped pattern,
It is characterized in that it is composed of a C-shaped electrode having a gradually increasing distance toward the other side, and the arrester electrode on the side of the first electrode substrate and the arrester electrode on the side of the second electrode substrate are arranged in opposite directions. There is.

【0019】本発明の好ましい態様によれば、上記第1
電極基板の上記外部電極側アレスター電極の斜辺と上記
第2透明電極の上記ダミー電極側アレスター電極の斜辺
とが平行で、かつ、上記第2電極基板の上記外部電極側
アレスター電極の斜辺と上記第1透明電極の上記引き回
し配線側アレスター電極の斜辺とが平行とされる。
According to a preferred aspect of the present invention, the first
The oblique side of the arrester electrode on the external electrode side of the electrode substrate and the oblique side of the arrester electrode on the dummy electrode side of the second transparent electrode are parallel to each other, and the oblique side of the arrester electrode on the external electrode side of the second electrode substrate and the oblique side. (1) The transparent electrode is parallel to the oblique side of the lead-out wiring side arrester electrode.

【0020】[0020]

【発明の実施の形態】次に、図1および図2を参照し
て、本発明の実施形態について説明する。図1は本発明
が備えるアレスター電極を示す模式的斜視図である。図
2はその平面図で、同図(a)は電極基板間にずれがな
い場合を示し、同図(b)はずれがある場合を示してい
る。なお、この実施形態に係る液晶表示パネルの基本的
な構成は、先に説明した図3を参照されたい。
BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic perspective view showing an arrester electrode included in the present invention. 2A and 2B are plan views thereof, FIG. 2A shows a case where there is no deviation between the electrode substrates, and FIG. 2B shows a case where there is a deviation. For the basic configuration of the liquid crystal display panel according to this embodiment, refer to FIG. 3 described above.

【0021】本発明においても、第1電極基板10と第
2電極基板20の基板端面10a,20aから外部電極
13,23がシール材30の塗布領域内に引き込まれ、
外部電極13は引き回し配線12と対向してアレスター
電極P10aを形成し、外部電極23はダミー電極22
と対向してアレスター電極P20aを形成する。
Also in the present invention, the external electrodes 13 and 23 are drawn from the substrate end faces 10a and 20a of the first electrode substrate 10 and the second electrode substrate 20 into the coating region of the seal material 30,
The external electrode 13 forms the arrester electrode P10a facing the lead wiring 12, and the external electrode 23 is the dummy electrode 22.
To form an arrester electrode P20a.

【0022】外部電極13,23,引き回し配線12お
よびダミー電極22はともに、ITOにより帯状パター
ンとして形成されるが、本発明において、アレスター電
極を形成するそれらの各端部は、上記従来例のような尖
鋭な山形状ではなく、斜めにカットされる。
The external electrodes 13 and 23, the lead-out wiring 12 and the dummy electrode 22 are all formed of ITO in the form of a strip pattern. In the present invention, the respective end portions forming the arrester electrodes are the same as in the above-mentioned conventional example. It is cut diagonally instead of a sharp mountain shape.

【0023】まず、第1電極基板10側のアレスター電
極P10aについて説明すると、そのギャップポイント
(突き合わせ頂点)12g,13gが帯状パターンの一
方の辺側に設けられ、引き回し配線12の端部12aと
外部電極13の端部13aには、上記ギャップポイント
12g,13gから帯状パターンの他方の辺に向けて漸
次間隔が広くなる斜辺12b,13bがそれぞれ形成さ
れている。
First, the arrester electrode P10a on the side of the first electrode substrate 10 will be described. Gap points (butting apexes) 12g and 13g are provided on one side of the strip-shaped pattern, and the end 12a of the routing wiring 12 and the outside are provided. On the end portion 13a of the electrode 13, oblique sides 12b and 13b are formed in which the distance gradually increases from the gap points 12g and 13g toward the other side of the strip-shaped pattern.

【0024】第2電極基板20側のアレスター電極P2
0aも同様に、そのギャップポイント22g,23gが
帯状パターンの一方の辺側に設けられ、ダミー電極22
の端部22aと外部電極23の端部23aには、上記ギ
ャップポイント22g,23gから帯状パターンの他方
の辺に向けて漸次間隔が広くなる斜辺22b,23bが
それぞれ形成されている。
The arrester electrode P2 on the second electrode substrate 20 side
0a is also provided with the gap points 22g and 23g on one side of the strip-shaped pattern.
At the end portion 22a of the external electrode 23 and the end portion 23a of the external electrode 23, oblique sides 22b and 23b are formed, each of which the distance gradually increases from the gap points 22g and 23g toward the other side of the strip-shaped pattern.

【0025】なお、ギャップポイント12g,13g;
22g,23gの間隔は、上記従来例と同じく5〜10
μm程度に設定され、また、斜辺12b,13b;22
b,23bの各開き角は任意に選択されてよいが、その
開き角は同一であることが好ましい。
The gap points 12g and 13g;
The distance between 22 g and 23 g is 5 to 10 as in the conventional example.
.mu.m and the hypotenuses 12b, 13b; 22
The opening angles of b and 23b may be arbitrarily selected, but the opening angles are preferably the same.

【0026】このように、各アレスター電極P10a,
P20aはともに、ハ字状に形成されるが、図2(a)
の平面図に示すように、アレスター電極P10aとアレ
スター電極P20aは、逆向きの配置とされる。
In this way, each arrester electrode P10a,
Both P20a are formed in a V shape, but FIG. 2 (a)
As shown in the plan view of 1, the arrester electrode P10a and the arrester electrode P20a are arranged in opposite directions.

【0027】すなわち、図2(a)において、アレスタ
ー電極P10aのギャップポイント12g,13gが右
側に配置されるとすると、アレスター電極P20aのギ
ャップポイント22g,23gは反対の左側に配置され
る。
That is, in FIG. 2A, if the gap points 12g and 13g of the arrester electrode P10a are arranged on the right side, the gap points 22g and 23g of the arrester electrode P20a are arranged on the opposite left side.

【0028】なお、第1電極基板10の外部電極側アレ
スター電極の斜辺13bと第2透明電極20のダミー電
極側アレスター電極の斜辺22bとが平行で、かつ、第
2電極基板20の外部電極側アレスター電極の斜辺23
bと第1透明電極10の引き回し配線側アレスター電極
の斜辺12bとが平行であることが好ましい。
The oblique side 13b of the arrester electrode on the external electrode side of the first electrode substrate 10 and the oblique side 22b of the arrester electrode on the dummy electrode side of the second transparent electrode 20 are parallel to each other, and the external electrode side of the second electrode substrate 20. The hypotenuse 23 of the arrester electrode
It is preferable that b and the oblique side 12b of the lead-out wiring side arrester electrode of the first transparent electrode 10 are parallel to each other.

【0029】斜辺12b,13b;22b,23bの各
開き角が同一とすることにより、上記のように斜辺13
bと斜辺22bとが平行で、かつ、斜辺23bと斜辺1
2bとが平行となり、本発明においては、アレスター電
極間ギャップ方向に沿った斜辺13bと斜辺22b間
(斜辺23bと斜辺12b間)の距離Lが、ずれ許容範
囲となる。
By setting the respective opening angles of the hypotenuses 12b, 13b; 22b, 23b to be the same, as described above, the hypotenuse 13
b and the hypotenuse 22b are parallel, and the hypotenuse 23b and the hypotenuse 1
In the present invention, the distance L between the oblique side 13b and the oblique side 22b (between the oblique side 23b and the oblique side 12b) along the direction of the gap between the arrester electrodes is the allowable deviation range.

【0030】すなわち、図2(b)に示すように、第1
電極基板10と第2電極基板20とを圧着する際、それ
らの間にアレスター電極間ギャップ方向に相対的な位置
ずれが生じたとしても、その位置ずれ量が許容範囲L未
満であれば、第1電極基板10側の引き回し配線12が
第2電極基板20側の外部電極23と、もしくは第2電
極基板20側のダミー電極22と第1電極基板10側の
外部電極13とがシール材30内の導電性粒子を介して
接続されることがない。
That is, as shown in FIG. 2B, the first
When the electrode substrate 10 and the second electrode substrate 20 are pressure-bonded to each other, even if a relative positional deviation occurs in the gap between the arrester electrodes between them, if the positional deviation amount is less than the allowable range L, The lead wiring 12 on the side of the first electrode substrate 10 and the external electrode 23 on the side of the second electrode substrate 20, or the dummy electrode 22 on the side of the second electrode substrate 20 and the external electrode 13 on the side of the first electrode substrate 10 are inside the sealing material 30. No conductive particles are connected.

【0031】位置ずれ量の許容範囲Lは、斜辺12b,
13b;22b,23bの開き角によって決まり、その
角度によっては、アレスター電極間ギャップの数倍とす
ることができ、これにより各電極基板を圧着する際の位
置合わせに高精度を要求されることなく、アレスター電
極を有効に動作させることができる。
The permissible range L of the amount of positional deviation is the hypotenuse 12b,
13b; 22b, 23b are determined by the opening angle, and depending on the angle, the gap between the arrester electrodes can be set to several times, whereby high precision is not required for the alignment when the electrode substrates are pressure-bonded. , The arrester electrode can be effectively operated.

【0032】[0032]

【発明の効果】以上説明したように、本発明によれば、
シール材の周辺部分の非表示領域に形成されている一方
の電極基板側の引き回し配線と、これと対向して他方の
電極基板側に形成したダミー電極とをシール材内の導電
性粒子を介して接続するとともに、電極基板の各々に、
基板端面からシール材塗布領域内に引き込まれ、上記引
き回し配線の端部および上記ダミー電極の端部との間
で、それぞれアレスター電極を形成する外部電極を設け
てなる液晶表示パネルにおいて、各電極基板のアレスタ
ー電極をともに、帯状パターンの一方の辺側に互いに対
向する突き合わせ頂点を持ち、他方の辺に向けて漸次間
隔が広くなるハ字状電極として、一方の電極基板側のア
レスター電極と他方の電極基板側のアレスター電極とを
逆向きに配置したことにより、2枚の電極基板間の相対
的な位置決めに高精度を要求されることなく、アレスタ
ー電極を有効に動作可能な状態とすることができる。
As described above, according to the present invention,
The lead-out wiring on one electrode substrate side formed in the non-display area in the peripheral portion of the sealing material and the dummy electrode formed on the other electrode substrate side opposite to this are connected via conductive particles in the sealing material. Connected to each of the electrode substrates,
In the liquid crystal display panel, which is drawn from the end face of the substrate into the sealing material application region, and which is provided with external electrodes that form arrester electrodes between the end of the lead wiring and the end of the dummy electrode, each electrode substrate Both of the arrester electrodes of 1) have abutting vertices facing each other on one side of the strip-shaped pattern and have a gradually increasing distance toward the other side. By arranging the arrester electrode on the electrode substrate side in the opposite direction, it is possible to effectively operate the arrester electrode without requiring high accuracy in relative positioning between the two electrode substrates. it can.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明が備えるアレスター電極を示す模式的斜
視図。
FIG. 1 is a schematic perspective view showing an arrester electrode included in the present invention.

【図2】上記アレスター電極のずれがない場合と、ずれ
がある場合の双方の状態を示す平面図。
FIG. 2 is a plan view showing both states of the case where the arrester electrode is not displaced and the case where the arrester electrode is displaced.

【図3】液晶表示パネルの従来例を示した模式的縦断面
図。
FIG. 3 is a schematic vertical sectional view showing a conventional example of a liquid crystal display panel.

【図4】上記従来例が備えているアレスター電極を示す
模式的斜視図。
FIG. 4 is a schematic perspective view showing an arrester electrode provided in the conventional example.

【図5】上記従来例おけるアレスター電極のずれがない
場合と、ずれがある場合の双方の状態を示す平面図。
FIG. 5 is a plan view showing both states in the case where there is no displacement of the arrester electrode in the above-mentioned conventional example and in the case where there is displacement.

【符号の説明】[Explanation of symbols]

10 第1電極基板 11 表示電極 12 引き回し配線 20 第2電極基板 21 表示電極 22 ダミー電極 30 シール材 10a,20a 基板端面 13,23 外部電極 12b,13b,22b,23b 斜辺 12g,13g,22g,23g ギャップポイント P10a,P20a アレスター電極 10 First electrode substrate 11 Display electrode 12 routing wiring 20 Second electrode substrate 21 Display electrode 22 Dummy electrode 30 sealing material 10a, 20a substrate end face 13,23 External electrode 12b, 13b, 22b, 23b hypotenuse 12g, 13g, 22g, 23g Gap point P10a, P20a arrester electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 柳 裕喜 新潟県長岡市東蔵王2丁目2番34号 日本 精機株式会社内 Fターム(参考) 2H092 GA32 GA61 GA64 NA14 PA04 5C094 AA03 AA42 BA43 EA01 EA02 EA10 FA01 HA08    ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yuki Yanagi             2-3 2-3 Higashi Zao, Nagaoka City, Niigata Japan             Within Seiki Co., Ltd. F-term (reference) 2H092 GA32 GA61 GA64 NA14 PA04                 5C094 AA03 AA42 BA43 EA01 EA02                       EA10 FA01 HA08

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 第1電極基板と第2電極基板とをシール
材を介して圧着してなり、そのセルギャップ内における
上記シール材の周辺部分の非表示領域内の上記第1電極
基板側に表示電極の引き回し配線が形成され、上記非表
示領域内の上記第2電極基板側には上記引き回し配線と
対向するダミー電極が形成されているとともに、上記引
き回し配線と上記ダミー電極とが上記シール材に含まれ
ているトランスファ材にて導通されており、上記電極基
板の各々に、基板端面から上記シール材塗布領域内に引
き込まれ、上記引き回し配線の端部および上記ダミー電
極の端部との間で、それぞれアレスター電極を形成する
外部電極が設けられている液晶表示パネルにおいて、 上記各電極基板のアレスター電極がともに、帯状パター
ンの一方の辺側に互いに対向する突き合わせ頂点を持
ち、他方の辺に向けて漸次間隔が広くなるハ字状電極か
らなり、上記第1電極基板側のアレスター電極と上記第
2電極基板側のアレスター電極とが逆向きに配置されて
いることを特徴とする液晶表示パネル。
1. A first electrode substrate and a second electrode substrate are pressure-bonded to each other with a sealing material interposed therebetween, and the first electrode substrate side is provided in a non-display area around the sealing material in the cell gap. A lead wire for the display electrode is formed, and a dummy electrode facing the lead wire is formed on the second electrode substrate side in the non-display area, and the lead wire and the dummy electrode are the sealing material. Is conducted by a transfer material included in the electrode substrate, is drawn into each of the electrode substrates from the end face of the substrate into the seal material application region, and is between the end of the lead wiring and the end of the dummy electrode. Thus, in the liquid crystal display panel provided with the external electrodes forming the arrester electrodes, the arrester electrodes of each of the above-mentioned electrode substrates are arranged on one side of the strip pattern. And an abutment electrode facing the first electrode substrate side and an arrester electrode on the second electrode substrate side opposite to each other. A liquid crystal display panel characterized by being arranged.
【請求項2】 上記第1電極基板の上記外部電極側アレ
スター電極の斜辺と上記第2透明電極の上記ダミー電極
側アレスター電極の斜辺とが平行で、かつ、上記第2電
極基板の上記外部電極側アレスター電極の斜辺と上記第
1透明電極の上記引き回し配線側アレスター電極の斜辺
とが平行である請求項1に記載の液晶表示パネル。
2. The oblique side of the external electrode side arrester electrode of the first electrode substrate and the oblique side of the dummy electrode side arrester electrode of the second transparent electrode are parallel to each other, and the external electrode of the second electrode substrate. The liquid crystal display panel according to claim 1, wherein a hypotenuse of the side arrester electrode and a hypotenuse of the lead wiring side arrester electrode of the first transparent electrode are parallel to each other.
JP2001399267A 2001-12-28 2001-12-28 LCD panel Expired - Fee Related JP3921386B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001399267A JP3921386B2 (en) 2001-12-28 2001-12-28 LCD panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001399267A JP3921386B2 (en) 2001-12-28 2001-12-28 LCD panel

Publications (2)

Publication Number Publication Date
JP2003195339A true JP2003195339A (en) 2003-07-09
JP3921386B2 JP3921386B2 (en) 2007-05-30

Family

ID=27604369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001399267A Expired - Fee Related JP3921386B2 (en) 2001-12-28 2001-12-28 LCD panel

Country Status (1)

Country Link
JP (1) JP3921386B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007065418A (en) * 2005-08-31 2007-03-15 Optrex Corp Display panel
US7304699B2 (en) 2003-03-31 2007-12-04 Sharp Kabushiki Kaisha Liquid crystal display panel
US7483110B2 (en) 2004-03-25 2009-01-27 Sharp Kabushiki Kaisha Liquid crystal display device
JP2012118621A (en) * 2010-11-29 2012-06-21 Dainippon Printing Co Ltd Color filter integrated touch panel sensor, display device with touch panel function and manufacturing method of polygonal work substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7304699B2 (en) 2003-03-31 2007-12-04 Sharp Kabushiki Kaisha Liquid crystal display panel
US7483110B2 (en) 2004-03-25 2009-01-27 Sharp Kabushiki Kaisha Liquid crystal display device
JP2007065418A (en) * 2005-08-31 2007-03-15 Optrex Corp Display panel
JP2012118621A (en) * 2010-11-29 2012-06-21 Dainippon Printing Co Ltd Color filter integrated touch panel sensor, display device with touch panel function and manufacturing method of polygonal work substrate

Also Published As

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JP3921386B2 (en) 2007-05-30

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