JP2003188749A - I/q converter ic and dbs tuner for receiving satellite broadcast - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DBS tuner for receiving satellite broadcast and an I/Q converter IC in which the number of part items is decreased and current consumption is reduced. <P>SOLUTION: An I/Q converter IC 52 forms an AGC signal on the basis of an intermediate frequency signal supplied from a high frequency signal processing circuit 50 and applies the AGC signal to an attenuator 14 of the high frequency signal processing circuit 50. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an I / Q converter IC (Integrated Circuit) for processing digital QPSK modulated signals used in satellite broadcasting and a DBS tuner for receiving satellite broadcasting equipped with the IC.

[0002]

2. Description of the Related Art In satellite broadcasting, for example, analog FM modulated signals and digital QPSK modulated signals coexist. Conventionally, satellite broadcasting broadcast by analog FM modulated signals is an analog receiver and is broadcast by digital QPSK modulated signals. I was receiving with a digital receiver. Therefore, 2
This requires two receivers, and thus a total of two set top boxes or a TV with two receivers built in.

[0003]

To reduce the cost, it is necessary to downsize the receiver and reduce the number of parts by sharing the circuit. Here, the high frequency signal processing circuit in the receiver that selects a high frequency signal received by an antenna or the like and outputs an intermediate frequency has a common function of analog and digital,
Can be shared. Specifically, as shown in FIG. 5, the high frequency signal processing circuit 50 includes high frequency amplifier circuits 12a and 12b, a filter 15, a mixer 16, a local oscillator circuit 17, a PLL (Ph).
ase Lock Loop) synthesizer 18, intermediate frequency band pass filters 22A, 22B, intermediate frequency amplifier circuit 2
3 is provided, and these circuits can be commonly used in analog and digital.

In the subsequent stage of the high frequency signal processing circuit 50, an analog FM FM demodulation IC 51 and a QP are provided.
An I / Q converter IC 53 for SK demodulation is provided.
Furthermore, the FM demodulation IC 51 or the I / Q converter IC 5
In order to make the input signal level to 3 the optimum value,
The detection circuits 24 and 27 and the attenuator 14 for controlling the attenuation amount of the high frequency signal by the RF AGC control current from the AGC detection circuits 24 and 27 are used as the high frequency signal processing circuit 5.
It is necessary to prepare for the inside of 0. As a result, the attenuator 14 controls the amount of attenuation of the high frequency signal, and secures the desired performance of the intermodulation interference suppression characteristic and the noise figure as a tuner.

As shown in FIG. 5, a conventional FM demodulation IC has been used.
In general, 51 has a built-in AGC detection circuit 27 and generally supplies current to the outside of the FM demodulation IC 51. However, the I / Q converter IC53
In order to perform control by the RFAGC control current from the QPSK demodulation unit that receives the I signal and the Q signal output from the I / Q converter IC53 and performs QPSK demodulation, the I / Q converter IC53 incorporates an AGC detection circuit. There was nothing. Therefore, in the conventional receiver described above, an independent AGC detection circuit 24, FM demodulation IC 51, and I / Q converter IC 5 are provided in the subsequent stage of the high-frequency signal processing circuit 50.
3 parts of 3 were needed. Therefore, the conventional receiver described above has a large number of parts and consumes high power.

The present invention solves the above-mentioned problems, and aims at reducing the number of receiver parts and the current consumption.
It is an object to provide a tuner and an I / Q converter IC used for the tuner.

[0007]

In order to achieve the above object, according to the present invention, in an I / Q converter IC which processes a digital QPSK modulated signal and outputs an I signal and a Q signal, AGC that performs AGC detection
It has a built-in detection circuit.

With such a configuration, the I / Q converter IC processes the digital QPSK modulated signal to process the QPSK.
It outputs I and Q signals for demodulation. Since the AGC detection circuit is built in the I / Q converter IC,
The Q converter IC can output the RFAGC control current. Therefore, when a satellite broadcast receiving DBS tuner that receives a digital QPSK modulated signal using the I / Q converter IC of this configuration is used, it is not necessary to further provide an AGC detection circuit, and the number of parts can be reduced.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below. FIG. 1 shows a satellite broadcast receiving DBS of this embodiment.
6 is a block diagram of the tuner, and the same parts as those in FIG. 5 are denoted by the same reference numerals. The DBS tuner for satellite broadcast reception of the present embodiment is a digital Q that is used in satellite broadcasts and the like.
It is possible to receive both PSK modulated signals and analog FM modulated signals. The DBS tuner for satellite broadcast reception includes a high frequency signal processing circuit 50, an FM demodulation IC 51, an I
The intermediate frequency output from the / Q converter IC 52 and the high frequency signal processing circuit 50 is converted to the FM demodulation circuit ICs 51 and I.
Power distributor 25 for distributed supply to the Q / Q converter IC 52
And consists of.

A high frequency signal received by an antenna (not shown) or the like is a BS (Broadcasting Satellite) converter (or LNB (Low Noise Block down Converter)).
It is divided into two systems of a horizontal polarization component and a vertical polarization component (not shown) and input to the high frequency signal processing circuit 50 from the high frequency input terminals 10a and 10b, respectively. Then, the high-frequency signal input from the terminal 10a has its low-frequency component removed by the capacitor 9a and the high-pass filter 11a. Further, the high frequency signal input from the terminal 10b has a low frequency component removed by the capacitor 9b and the high pass filter 11b. The high-frequency amplifier circuits 12a and 12b are controlled by the switching circuit 13 to switch and amplify one of the signals from the high-pass filters 11a and 11b and send the amplified signal to the attenuator 14 at the next stage.

The attenuator 14 controls the attenuation amount of the high frequency signal by the RFAGC control current. The RF AGC control current is input from the FM demodulation IC 51 and the I / Q converter IC 52 to the high frequency signal processing circuit 50, merged at the node 120 inside the high frequency signal processing circuit 50, and transmitted to the attenuator 14. Then, in the filter 15 of the next stage, P
Tuning is performed under the control of the LL synthesizer 18. A tracking filter or an image filter is used as the filter 15.

The signal passed through the filter 15 is
The mixer 16 mixes with the signal oscillated from the first local oscillation circuit 17 to perform frequency conversion (for example, 479.
5 MHz) and passes through the low pass filter 19. In addition,
The oscillation frequency of the local oscillation circuit 17 is the PLL synthesizer 1.
Controlled by 8.

After passing through the low-pass filter 19, the signal is amplified by the amplifier circuit 20, and the switching circuit 21 determines the supply destination of the signal to one of the intermediate frequency band filters 22A and 22B. Intermediate frequency band filters 22A, 2
2B has a different pass band, and the filter 22
The signal that has passed through the filter circuit 22 composed of A and 22B is amplified by the intermediate frequency amplifier circuit 23, and the intermediate frequency is output from the high frequency signal processing circuit 50.

For example, when a plurality of transponders are provided in the satellite and the transmission bandwidth of the transponders passing through differs depending on the broadcasting channel, the channel selected by a control means (not shown) such as a microcomputer is selected. Accordingly, the PLL synthesizer 18 controls the switch position of the switching circuit 21 so that the bandwidth is switched by the data from the terminal 103 and the clock from the terminal 104 via the bus. In the high frequency signal processing circuit 50, the terminals 101 and 102 are power supply terminals, and the terminal 10
Reference numeral 5 is a tuning power supply terminal. Also, the terminal 116,
Reference numeral 117 denotes a terminal provided to output data from the satellite broadcast receiving DBS tuner side.

The intermediate frequency output from the high frequency signal processing circuit 50 is sent to the power demodulator 25 by the FM demodulation IC 51 and I / I.
The signal is distributed and supplied to the Q converter IC 52. When processing the analog FM modulation signal, power is supplied from the terminal 106 to the FM demodulation IC 51 under the control of the control means (not shown), and the I / Q converter IC 52 is connected to the terminal 1.
The power supply from 14 is cut off. Conversely, digital QPS
When processing the K modulation signal, the I / Q from the terminal 114
Power is supplied to the converter IC 52, and the FM demodulation IC
The power supply to 51 is cut off. As described above, the control means (not shown) includes the FM demodulation IC 51 and the I / Q converter I.
One of C52 is turned on and the other is turned off.

In the FM demodulation IC 51, the input intermediate frequency is first amplified by the amplification circuit 26 and sent to the first AGC detection circuit 27 and the PLLFM demodulation circuit 28. Then, the PLLFM demodulation circuit 28 performs FM control by PLL control.
It demodulates and outputs the detection result from the terminal 107.

The AGC detection circuit 27 is an amplifier circuit 26.
AGC detection is performed according to the signal from the RF demodulation IC 51, and a current due to the RF AGC control current flows out from the FM demodulation IC 51. Further, the signal from the PLL FM demodulation circuit 28 is sent to the PLL synthesizer 18 of the window comparator 29 by the signal A.
FT1 and AFT2 are output. This is a BS converter (or LNB (Lo) that sends a signal to the PLL synthesizer 18.
w Noise Block down Converter)) (not shown) to correct an error in the signal input to the high frequency generation circuit 50 due to local drift or the like.

As shown in FIG. 2, signals AFT1 and AFT
2 are both high level (H) near the frequency f0, but the signal A is on the side where the frequency is somewhat lower than f0.
FT2 is at high level (H), but signal AFT1 is at low level (L). On the side where one frequency is higher than f0 to some extent, the signal AFT1 is at a high level,
The signal AFT2 becomes low level. The PLL synthesizer 18 controls the intermediate frequency so that the signals AFT1 and AFT2 are both at the high level. Also, the signal AFT1,
AFT2 is output from terminals 108 and 109.

Referring again to FIG. 1, the I / Q converter I
At C52, the intermediate frequency supplied from the power distributor 25 is amplified by the AGC amplifier circuit 30 and sent to the I-side mixer 32, the Q-side mixer 33, and the AGC detection circuit 31. A current due to the RF AGC control current flows out from the second AGC detection circuit 31. In the mixers 32 and 33, the phase shifter 34
Thus, signals whose phases are 90 degrees out of phase with each other are input and are divided into I signal and Q signal, respectively. The phase shifter 34 is oscillated by being supplied with power from the terminal 115.
The signal from the local oscillation circuit 43 is input.

The signal output from the mixer 32 is amplified by the baseband amplifier circuits 35 and 36, and the high frequency component is removed by the I side low pass filter 37. Further, the I signal is amplified by the baseband amplifier circuit 38 and output from the terminal 112. The signal output from the mixer 33 is amplified by the baseband amplifier circuits 39 and 40, and the high frequency component is removed by the Q side low pass filter 41. And Q
The signal is amplified by the baseband amplifier circuit 42, and the terminal 11
It is output from 3. The I and Q signals output from the I / Q converter IC 52 are QPSK provided in the subsequent stage.
QPSK demodulation is performed by a demodulation unit (not shown).

FIG. 3 is a circuit diagram of the attenuator 14.
A signal input from the terminal 200 is attenuated via the capacitor C1, pin diodes D1 and D2, and the capacitor C2, and output from the terminal 201. FM at the terminal 202
The RFAGC control current from the demodulation IC 51 flows. On the other hand, the terminal 203 is provided with an R from the I / Q converter IC 52.
The FAGC control current flows.

RFA input from terminals 202 and 203
The GC control currents merge at node 120 and flow to ground level through resistor R1, pin diodes D1, D2 and resistor R2. This current causes the pin diode D1,
The amount of attenuation at D2 is controlled. Thus, node 12
Since the control current is merged at 0 and then sent to the attenuator 14, the circuit of the attenuator 14 is simple.

In the above circuit shown in FIG. 4, a protective diode D5 is further inserted between the terminal 202 and the node 120 so that the anode faces the terminal 202 and the cathode faces the node 120. Further, a protection diode D6 is inserted between the terminal 203 and the node 120 such that the A node faces the terminal 203 and the cathode faces the node 120.

As a result, the current of the RF AGC control current sent from the turned-on side does not flow into the turned-off side of one of the FM demodulation IC 51 and the I / Q converter IC 52, and is turned off. FM demodulation IC on the side
51 and the I / Q converter IC 52 are protected.

Thus, in this embodiment, the FM demodulation IC
Since the AGC detection circuits 27 and 31 are built in both 51 and the I / Q converter IC 52, independent AG
It is not necessary to provide a C detection circuit, and the number of parts can be reduced. Therefore, the effect of lowering the cost of the DBS tuner for satellite broadcasting reception can be obtained. In addition, the FM demodulation IC 51 and the I / Q converter IC 52 are controlled by the modulated signal for signal processing.
Either one of them is turned off, resulting in low power consumption. In the present embodiment, the DBS tuner for satellite broadcast reception that receives the digital QPSK modulated signal and the analog FM modulated signal is used. It becomes possible to receive by providing accordingly.

[0026]

According to the present invention, an I / Q converter IC
Since the AGC detection circuit is built in, it is not necessary to provide the AGC detection circuit in the satellite broadcast receiving DBS tuner, and the number of parts can be reduced. Therefore, the price and power consumption of the satellite broadcast receiving DBS tuner can be reduced.

[Brief description of drawings]

FIG. 1 is a satellite broadcast receiving D according to a first embodiment of the present invention.
Block diagram of BS tuner.

[Fig. 2] Signal A of the DBS tuner for satellite broadcasting reception
The figure which shows the output state of FT1 and AFT2.

FIG. 3 is a circuit diagram of an example of an attenuator of a high frequency amplifier circuit of the satellite broadcast receiving DBS tuner.

FIG. 4 is a circuit diagram in which a diode is inserted on the input side of an RF AGC control current to the attenuator.

FIG. 5 is a block diagram of a conventional DBS tuner for satellite broadcast reception.

[Explanation of symbols]

10a, 10b High frequency input terminal 11a, 11b High-pass filter 12a, 12b high frequency amplifier circuit 13 Switching circuit 14 Attenuator 15 filters 16 mixer 17 First local oscillator circuit 18 PLL synthesizer 19 Low-pass filter 20 Intermediate frequency amplifier circuit 21 Switch circuit 22A, 22B Intermediate frequency band filter 23 Intermediate frequency amplification circuit 25 power distributor 26 AGC amplifier circuit 27 AGC detection circuit 28 PLLFM demodulation circuit 29 Window comparator 30 AGC amplifier circuit 31 AGC detection circuit 32 I side mixer 33 Q side mixer 34 Phase shifter 35, 36 I side baseband amplifier circuit 37 I side low pass filter 39, 40 Q side baseband amplifier circuit 41 Q side low pass filter 43 Second local oscillator circuit 50 High frequency signal processing circuit 51 FM demodulation IC 52 I / Q converter IC D1, D2 pin diode D5, D6 protection diode R1, R2 resistance

Claims (2)

[Claims] 1. A digital QPSK modulated signal is processed to I
In an I / Q converter IC that outputs a signal and a Q signal, an AGC detection circuit that performs AGC detection of an input intermediate frequency is built-in.
C. 2. A DBS tuner for satellite broadcast reception equipped with the I / Q converter IC of claim 1.