JP2003186555A - Circuit for power regulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit that allows efficient use of power voltage and limit overload current. <P>SOLUTION: The voltage at connecting point of a fist resistor 7 and a second resistor 8 is decreased due to a voltage drop at a power terminal 3, as well as a positive gate voltage, is decreased lower than the negative input voltage level of the first amplifier 5. Consequently, a first P-MOSFET 6 drops the gate voltage and the difference in the voltage between the source and the gate is increased. As a result, a load current works to increase the voltage at the power terminal 3, increases the positive input voltage, and equalizes the positive and negative voltages, if the positive voltage level is higher than the negative input voltage level, the load current works in the reverse direction and equalizes the positive and negative input voltages. If the voltage is decreased at a fourth resistor 16 and a fifth resistor 17 passes a voltage Vbe between a base and an emitter due to the load current increase, a collector current flows which decreases the voltage at a sixth resistor 18. If the voltage level passes a threshold voltage VT of the fourth P-MOSFET 19, drain current flows and increases the gate voltage of the first P-MOSFET 6, which limits the load current. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply regulator circuit, and more particularly to a power supply regulator circuit having a current limiting circuit for preventing destruction due to an excessive current.

[0002]

2. Description of the Related Art A conventional power supply regulator circuit is constructed as shown in the circuit diagram of FIG. In FIG. 4, 1
Is a power supply terminal, 2 is a ground terminal, 3 is an output terminal, 4 is a reference voltage source, 5 is an amplifier, and 6 is an output transistor.
Channel MOSFETs (hereinafter referred to as P-MOSFETs), 7 and 8 are first and second resistors for setting output voltage, 9 is a resistor for detecting load current, and 10 is a PNP transistor for detecting current.

In the power supply regulator circuit shown in FIG. 4, a first resistor 7 and a second resistor 8 are connected in series between an output terminal 3 and a ground terminal 2, and the voltage at the resistance division point and a reference voltage source 4 are connected. Is compared by the first amplifier 5, the first P-MOSFET 6 is driven by this comparison output, and a load current is supplied to a load (not shown) connected to the output terminal 3. The output voltage Vo of the output terminal 3 is equal to the first amplifier 5, the first PM
It is stabilized by a negative feedback loop configured by feeding back to the positive input of the first amplifier 5 via the series circuit of the OSFET 6 and the first resistor 7 and the second resistor 8.

When the voltage of the reference voltage source 4 is Vref, the resistance value of the first resistor 7 is R7, and the resistance value of the second resistor 8 is R8, the output voltage Vo is expressed by the following (Equation 1). be able to.

[0005]

## EQU1 ## Vo = Vref (R7 + R8) / R8 Next, in the current limiting circuit composed of the PNP transistor 10 and the resistor 9 for current detection, the load current becomes too large and the first P- It is provided to prevent the MOSFET 6 from being destroyed. When the voltage drop of the resistor 9 becomes larger than the base-emitter voltage Vbe (about 0.7V) of the PNP transistor 10, the PNP
The transistor 10 is turned on, the gate-source voltage of the first P-MOSFET 6 is reduced, and the first P-MOS is turned on.
The FET 6 is operated so as to be turned off to limit the load current.

Here, when the output voltage Vo = 2V is set, the operating characteristic of the conventional power supply regulator circuit is shown by a broken line C in FIG.

[0007]

However, the power supply regulator circuit having such a configuration is the first P shown in FIG.
-To detect the load current flowing in the MOSFET 6,
If the resistor 9 is connected in series, a voltage drop will occur between the terminals of the resistor 9. In order to detect the current when the load current is excessively large and to prevent the voltage drop of the resistor 9 from affecting much during normal operation, it is necessary to select a small resistance value for the resistor 9.

However, this means that the current limiting function is operated at a large current value, and when the load is short-circuited, most of the voltage of the power supply input is applied to the first P-MOSFET 6, and the first P-MOSFET 6 is applied. However, there is an inconvenience that the first P-MOSFET 6 is destroyed by exceeding the allowable loss of.

Further, there is a problem in that the voltage drop of the resistor 9 provided for detecting the current is unavoidable and the power source utilization efficiency is not always good.

The present invention is directed to solving the above-mentioned problems of the prior art, and limits an excessive load current without connecting a current detection resistor in series with an output transistor and utilizes the power supply voltage. An object is to provide an efficient power supply regulator circuit.

[0011]

In order to achieve this object, a power supply regulator circuit according to the present invention includes an amplifier having a reference voltage source and a negative input connected, an output and a gate of the amplifier, a power supply terminal and a source, and First P-channel MOSF that supplies load current with output terminal and drain connected
ET, the first and the first connected in series between the output terminal and the ground terminal
In a power supply regulator circuit having a second resistor and connecting a positive input of an amplifier to a connection point between the first resistor and the second resistor, a first P-channel MOSFET and a current mirror are configured, and a drain is connected via a third resistor. A second P-channel MOSFET connected to the output terminal, a source on the drain side of the second P-channel MOSFET in the third resistor,
Third P channel MOS with gate connected to output terminal side
FET and drain of the third P-channel MOSFET,
And the ground terminal and the base via the fourth and fifth resistors, the sixth
A first NPN transistor in which a power supply terminal and a collector and a ground terminal and an emitter are connected via a resistor, a fourth P-channel in which a collector and a gate of the first NPN transistor, a power supply terminal and a source, and a gate and a drain of a first P-channel MOSFET are connected. And a MOSFET.

Further, the above-mentioned fourth P-channel MOSF
It is characterized in that a PNP transistor is used instead of ET.

A first amplifier connected to the reference voltage source and the negative input, and a first P-channel MOSFET for supplying a load current connecting the output and gate of the first amplifier, the power supply terminal and the source, and the output terminal and the drain. A first regulator connected to the positive input of the first amplifier at a connection point of the first resistor and the second resistor, the first regulator having the first and second resistors connected in series between the output terminal and the ground terminal.
A second P-channel MOSFET in which a channel MOSFET and a current mirror are configured and a drain is connected to an output terminal through a third resistor, and a source is connected to the drain side of the second P-channel MOSFET in the third resistor and a gate is connected to the output terminal side. A third P-channel MOSFET,
A drain of the third P-channel MOSFET, a ground terminal and a base via the fourth and fifth resistors, a power supply terminal and a collector via a sixth resistor, and a first NPN transistor having a ground terminal and an emitter grounded; and a first NPN transistor. A connection point between a collector and a gate, a power supply terminal and a source, a fourth P-channel MOSFET in which a gate and a drain of the first P-channel MOSFET are connected, a reference voltage source and a positive input, an output terminal and a negative input, and a fourth resistance and a fifth resistance. And a second amplifier connected to the output, a first P-channel MOSFET and a current mirror, and a fifth P-channel MOSFET in which the drain is connected to the output terminal via the seventh resistor, and a fifth P-channel M in the seventh resistor.
The drain side of the OSFET is provided with a source and the sixth P-channel MOSFET having a gate connected to the output terminal side, and the drain current of the sixth P-channel MOSFET is used as the bias current of the second amplifier.

Further, the sixth P channel MOSFE
It is characterized in that a PNP transistor is used instead of T.

A first amplifier connected to the reference voltage source and the negative input, and a first P-channel MOSFET for supplying a load current connecting the output and gate of the first amplifier, the power supply terminal and the source, and the output terminal and the drain. , A positive input in a power regulator circuit having first and second resistors connected in series between the output terminal and the ground terminal, and connecting the positive input of the first amplifier to the connection point of the first resistor and the second resistor. A second amplifier connected to the power supply terminal via the eighth resistance and grounded via a constant current source, and a negative input connected to the power supply terminal via the ninth resistance; and a first P-MOSFE.
A seventh P-MOSFET in which the gate and the drain of T are connected in common and the negative input and the source of the second amplifier are connected, respectively, and the base is connected to the output of the second amplifier and connected in series. , Grounded through the fifth resistor, the collector through the sixth resistor to the power supply terminal,
The 1st N connecting the emitter to the ground terminal via the 9th resistor
PN transistor, collector and gate of first NPN transistor, power supply terminal and source, first P-MOSFET
P-MOSFET in which the gate and drain of the
A second NPN transistor in which a power supply terminal, a collector and a base are connected to form a diode connection, an emitter and a source of the second NPN transistor, an eighth P-MOSFET in which a gate and a gate of the first P-MOSFET are connected to each other, and a positive input is a reference voltage. A connection point of eleventh and twelfth resistors connected in series with the source, a negative input to an output terminal, and a third amplifier connected to a connection point of fourth and fifth resistors whose outputs are connected in series, and an eighth MOS- 3rd drain current of FET
It is characterized in that the bias current of the amplifier is used.

Further, a PNP transistor is used in place of the fourth MOSFET.

According to the above construction, the bias current at the time of no load does not increase, the power supply voltage utilization rate is not deteriorated, the overcurrent which the first P-MOSFET for supplying the load current breaks can be limited, and the load is short-circuited. Load current and power consumption can be reduced, protection from destruction can be achieved, and when the difference between the power supply voltage and the output voltage is small, excessive current limiting does not work, and the capacity of the first P-MOSFET for load supply is fully exerted. it can.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a circuit example of a power supply regulator circuit according to the first embodiment of the present invention. Here, components having equivalent functions corresponding to the constituent members described in FIG. 4 showing the above-mentioned conventional example are designated by the same reference numerals and shown, and the same applies to each of the following drawings. The operation of the power supply regulator circuit according to the first embodiment will be described with reference to FIG.

A constant current is supplied from the constant current source 11 connected to the power supply terminal 1 to the reference voltage source 4, and the reference voltage is supplied to the first amplifier 5.
Connect to the negative input of. The gate of the first P-MOSFET 6, which is the output transistor for supplying the load current, has the first
It is connected to the output of the amplifier 5 and the source is connected to the power supply terminal 1. The drain is connected to the output terminal 3 and is also connected to the positive input of the first amplifier 5 via the first resistor 7, and the positive input of the first amplifier 5 is connected to the ground terminal 2 via the second resistor 8. Connecting.

A second P-MOSFET 6 connected to a current mirror having a common gate and source.
-The drain of the MOSFET 12 is connected to the output terminal 3 via the third resistor 13, and the third P-MOSFET is connected.
Connect to 14 sources. Furthermore, the third P-MOSFE
The gate of T14 is connected to the output terminal 3. Also, the third P
The drain of the MOSFET 14 is connected to the base of the first NPN transistor 15 whose emitter is connected to the ground terminal 2, and the fourth and fifth resistors 16 and 17 are connected in series.
To the ground terminal 2 via.

The collector of the first NPN transistor 15 is connected to the other end of the sixth resistor 18 having one end connected to the power supply terminal 1, and the source is connected to the gate of the fourth P-MOSFET 19 connected to the power supply terminal 1. , 4P-M
The drain of the OSFET 19 is connected to the gate of the first P-MOSFET 6.

Further, in addition to the above configuration, the first P-MO
The drain of the fifth P-MOSFET 20 having the gate and the source commonly connected to the SFET 6 is connected to the output terminal 3 via the seventh resistor 21, and the sixth P-MOSFE is connected.
Connect to the source of T22. Furthermore, the 6th P-MOSFE
The gate of T22 is the output terminal 3, and the drain is the eighth resistor 2
3 is connected to the collector of the NPN transistor 24 connected to the current mirror forming the second amplifier 5 ′ and the connection point commonly connected to the base of the NPN transistor 25.

The emitters of the NPN transistors 24 and 25 are respectively connected to the ground terminal 2, and the collector of the NPN transistor 25 forming a current mirror is used as an N-channel MOSFET (hereinafter referred to as N-M) forming a differential amplifier circuit.
(Referred to as OSFET) and connected to the sources of N-MOSFETs 26 and 27, and the gate serving as the positive input of the N-MOSFET 26 is connected to the reference voltage source 4.
The gate that serves as the negative input of is connected to the output terminal 3.

The N-MO which constitutes the differential amplifier circuit
The drain of the SFET 26 is connected to the common connection point of the drain and gate of the P-MOSFET 28 that constitutes the active load, and the source of the P-MOSFET 28 is P-.
It is connected to the power supply terminal 1 together with the source of the MOSFET 29. The gate of the P-MOSFET 29 is P-MOSFE.
Connected to the gate and drain of T28, and connected to P-MOSFE
The drain of T29 (the output of the second amplifier 5 ′) is NM
It is connected to the drain of the OSFET 27 and also connected to the connection point of the fourth and fifth resistors 16 and 17 connected in series.

First P-MOSFET 6 and second P-MOS
The FET 12 and the fifth P-MOSFET 20 have a current mirror relationship. In addition, N- which constitutes the differential increasing circuit
MOSFETs 26 and 27 and P-MOSFET 29,
The second amplifier 5 ′ is constituted by 29.

With the configuration as described above, the output voltage Vo is controlled so that the negative input voltage and the positive input voltage value of the first amplifier 5 are equal.

[0028]

## EQU00002 ## Vo = Vref (R7 + R8) / R8 Vref: voltage of reference voltage source, R7: resistance value of first resistor,
R8: It becomes the resistance value of the second resistor, and (Equation 2) is established.

For example, if the voltage of the output terminal 3 drops for some reason, the connection point of the first and second resistors 7 and 8 connected in series, that is, the voltage of the positive input of the first amplifier 5 also drops. , The voltage of the positive input becomes lower than the voltage of the negative input, and the first P-MOSFET 6 for supplying the load current
, The gate voltage decreases and the source-gate voltage increases. This operates in the direction of increasing the load current,
The voltage at the output terminal 3 increases. As a result, the first amplifier 5
The voltage of the plus input also increases and the plus input voltage and the minus input voltage become equal.

Contrary to the above explanation of the operation, when the voltage of the plus input becomes higher than the voltage of the minus input, the operation is performed in the opposite direction to the above explanation, and similarly, the voltage of the plus input and the minus input. The operation of equalizing the voltages is executed.

Further, the load current increases, and the first P-M
Second P-MO that forms a current mirror with OSFET6
The drain current of the SFET 12 also increases, and when the voltage drop of the third resistor 13 exceeds the gate-source threshold voltage VT of the third P-MOSFET 14, the drain current of the third P-MOSFET 14 flows, and the fourth and fifth resistors 16, 17 are provided. When the voltage drop of the first NPN transistor 15 becomes larger than the base-emitter voltage Vbe of the first NPN transistor 15, the collector current of the first NPN transistor 15 flows, and a voltage drop occurs in the sixth resistor 18 and exceeds the threshold voltage VT of the fourth P-MOSFET 19. The drain current flows, the gate voltage of the first amplifier 5 and the connected first P-MOSFET 6 is increased, and the operation of limiting the load current, which is the drain current of the first P-MOSFET 6, is executed.

Further, the drain current also flows through the fifth P-MOSFET 20 which forms a current mirror with the first P-MOSFET 6, and the voltage drop of the seventh resistor 21 becomes the sixth P-MO.
When the gate-source threshold voltage VT of the SFET 22 is exceeded, a drain current flows through the sixth P-MOSFET 22,
N-MOSFETs 26 and 2 forming a differential amplifier circuit by the current mirrors of the NPN transistors 24 and 25.
A bias current is supplied as the source current of No. 7.

When the load current is further increased, the output voltage is lowered because the load current is limited as described above. When this output voltage becomes lower than the voltage of the reference voltage source 4, the N-MOSFET 26 and the P-MOSFET 28 of the differential amplifier circuit composed of the N-MOSFETs 26 and 27 are turned on.
Due to the current mirror configuration of the P-MOSFETs 28 and 29, the drain current of the P-MOSFET 29 flows to the connection point of the fourth and fifth resistors 16 and 17 connected in series to increase the base voltage of the first NPN transistor 15.
The collector current is increased, the drain current of the fourth P-MOSFET 19 is increased, the gate voltage of the first P-MOSFET 6 is increased, and the load current is further reduced.

Here, until the third P-MOSFET 14 and the sixth P-MOSFET 22 for bias current supply operate, the first P-MOSFET 6 for load current supply operates.
And a source and a gate are commonly connected (a current mirror is configured), second and fifth P-MOSFETs 12,
Since the drain of both 20 is connected to the output terminal 3,
All are supplied as load current, the bias current does not increase, and all are effectively supplied without waste.

The operation characteristic of the power supply regulator circuit according to the first embodiment described above is shown by the solid line A in FIG. Since there is no loss due to the current detection resistance as compared with the conventional broken line C, the power supply voltage can be effectively used and a large amount of load current can be supplied. Further, when the output voltage drops below the reference voltage due to current limitation, the load current is further limited, so that the load current can be greatly reduced and the power consumption can be reduced. This function is effective for protection when the load is short-circuited.

In the above description, the first P-MOSFET 6 for supplying the load current and the second and fifth P-MOSFETs 12, 20 forming a current mirror are connected to the third and seventh resistors 13, 21 for detecting the drain current. The P-MOSFET is used as the element to be operated, but
It goes without saying that the same effect can be obtained by using the NP transistor.

FIG. 2 is a diagram showing a circuit example of the power supply regulator circuit according to the second embodiment of the present invention. The operation of the power supply regulator circuit according to the second embodiment will be described with reference to FIG.

The power regulator circuit according to the second embodiment shown in FIG. 2 differs from that of the first embodiment shown in FIG. 1 in that the first NPN for detecting the limitation of the load current is used.
At the base of the transistor 15, P-MOSFETs 31 and 32 and N-MOSFET 3 that form a differential amplifier circuit
The drains of the P-MOSFETs 31 corresponding to the outputs of the output terminals 3, 34 and the gate of the N-MOSFET 34, which is the positive input of the differential amplifier circuit, are connected to the voltage drop portion of the eighth resistor 23 by the current of the constant current source 35 ( The other end of the 8th resistor)
And the reference voltage source 4 is connected to the positive input of the third amplifier 36, which further reduces the load current when the voltage of the output terminal 3 drops due to current limitation.
The main difference is that the tenth resistors 37 and 38 are divided and input.

The power regulator circuit shown in FIG. 2 is characterized in that the current limiting does not operate unless the voltage drop of the ninth resistor 39 occurs from the power supply voltage to the voltage corresponding to the voltage drop of the eighth resistor 23. When the power supply voltage input from the power supply terminal 1 is Vin, the output voltage of the output terminal 3 is Vo, and the load current is Iout, the power consumption Po of the entire circuit is approximately (Equation 3).

[0040]

[Equation 3] Po = (Vin−Vo) · Iout When the difference between the power supply voltage of the power supply terminal 1 and the output voltage is small,
Higher performance is obtained when the power consumption is reduced and the need for current limitation is low, and the current capability of the first P-MOSFET 6 for supplying the load current is sufficiently exerted. First P-MOS
W / which is the size ratio of the seventh P-MOSFET 40 in which the FET 6 and the gate and drain are commonly connected
By changing L, the first P-MOSFET 6 is made larger,
-Set MOSFET 40 small. First P-MOS
Since the FET 6 is for supplying load current, it naturally becomes large,
Since the seventh P-MOSFET 40 may be small, it may have a small area, which improves the area efficiency in the case of an integrated circuit.

When the difference between the power supply voltage and the output voltage is small, the drain current of the seventh P-MOSFET 40 is equal to the first P-M.
The gate voltage of the N-MOSFET 33 that constitutes the differential amplifier circuit is much smaller than that of the OSFET 6 and is NM
It does not drop below the gate voltage of OSFET 34, and thus no current limiting operation is performed.

In the circuit operation described below, the operation of the first amplifier 5 is the same as the conventional one, and therefore the description thereof is omitted. When the load current increases, the gate-source voltage Vgs of the first P-MOSFET 6 for supplying the load current increases unless the current limiting operation is performed.

[0043]

## EQU00004 ## Vgs = Vbe41 + VT42 where Vbe41 is the base-emitter voltage of the second NPN transistor 41, and VT42 is the eighth P-MOSFET.
42 threshold voltage.

When the gate-source voltage Vgs of the first P-MOSFET 6 increases and reaches the threshold voltage of the eighth P-MOSFET 42, a drain current flows through the eighth P-MOSFET 42 and a bias current flows through the third amplifier 36. Set to active state. In addition, the constant current sources 30, 35
Also in the above, if the setting is made based on this drain current, the bias can be greatly reduced when the load current is small.

Further, the load current increases and the first P-MO
If the gate voltage of the SFET 6 also drops and a difference voltage between the power supply voltage and the output voltage is generated to some extent, the 8th P-MO
The source and drain currents of the SFET 42 also increase, and a voltage drop occurs in the ninth resistor 39. If the voltage drop of the ninth resistor 39 becomes larger than the voltage drop of the eighth resistor 23,
N-MOSFET 33 is OFF, N-MOSFET 34
Is turned on and the P-MOSF that forms the current mirror
A drain current flows through the ETs 31 and 32, the base-emitter voltage Vbe of the first NPN transistor 15 rises,
If it becomes more than about 0.7V, the collector current will flow and the 4th P-
The gate voltage of the MOSFET 19 decreases and the drain current flows, the gate voltage of the first P-MOSFET 6 for supplying the load current increases, and the current limiting operation of reducing the load current is executed. When the load current is further increased, the output voltage drops due to current limitation.

When the voltage of the output terminal 3 becomes lower than the voltage of the positive input of the third amplifier 36, that is, the voltage obtained by dividing the reference voltage source 4 by the eleventh and twelfth resistors 37 and 38, the output of the third amplifier 36 becomes high. Becomes the first N through the fourth resistor 16.
The base voltage of the PN transistor 15 becomes high, and the first N
The collector current of the PN transistor 15 increases and the fourth P-
The drain current is increased by further lowering the gate voltage of the MOSFET 19, and the first P for supplying the load current is supplied.
Further increase the gate voltage of MOSFET 6 to further reduce and limit the load current.

In the above description, the first NPN transistor 1
As the element that operates by the collector current of No. 5, the fourth P-
Although the MOSFET 19 has been shown and described, a P
It is needless to say that the same operation is performed as the NP transistor to obtain the same effect.

The operation characteristic of the power supply regulator circuit according to the second embodiment described above is shown by a chain line B in FIG.
When the voltage difference between the power supply voltage of the power supply terminal 1 and the output voltage of the output terminal 3 is small, the current limiting circuit does not operate and the capacity of the first P-MOSFET 6 for supplying the load current is fully utilized,
It is possible to obtain a large load current with which the output voltage can be controlled to be constant. Moreover, the bias current is the same as in FIG.
Similar to the circuit example shown in Fig. 6, it operates with a small bias current of 20 μA or less when there is no load, and supplies a MOS for load current supply.
A current limiting circuit for FET protection, which does not increase even if a load short-circuit protection circuit is added, and when the difference between the power supply voltage and the output voltage is small, a current limiting circuit that can fully demonstrate the capability of the MOSFET for load current supply. It is possible to realize a power regulator circuit having

[0049]

As described above, according to the present invention,
The bias current at no load does not increase, the utilization factor of the power supply voltage does not deteriorate, and the overcurrent that may destroy the first P-MOSFET for supplying the load current can be limited, and the load can be short-circuited. It can reduce the load current and power consumption and protect it from damage. Furthermore, when the difference between the power supply voltage and the output voltage is small, excessive current limiting does not work, the capacity of the first P-MOSFET for load supply can be fully exerted, and the current limiting circuit has a great industrial utility value. This has the effect of realizing a power regulator circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit example of a power supply regulator circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a circuit example of a power supply regulator circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing operating characteristics of a power regulator circuit.

FIG. 4 is a diagram showing a circuit example of a conventional power supply regulator circuit.

[Explanation of symbols]

1 power supply terminal 2 Ground terminal 3 output terminals 4 Reference voltage source 5 First amplifier 5'second amplifier 6 P-MOSFET 7 First resistance 8 Second resistance 9 resistance 10 PNP transistor 11, 30, 31 constant current source 12 Second P-MOSFET 13th resistance 14 Third P-MOSFET 15 First NPN transistor 16 Fourth resistance 17 Fifth resistance 18th resistance 19 Fourth P-MOSFET 20 Fifth P-MOSFET 21 7th resistance 22 6th P-MOSFET 23 8th resistance 24,25 NPN transistor 26, 27, 33, 34 N-MOSFET 28, 29, 31, 32 P-MOSFET 36 Third Amplifier 37th resistance 38 12th resistance 39 9th resistance 40 7th P-MOSFET 41 Second NPN transistor 42 8th P-MOSFET

Continued front page    (72) Inventor Yasuo Higuchi             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F term (reference) 5H430 BB01 BB09 BB11 BB12 EE04                       FF02 FF07 FF13 GG01 HH03                       LA07

Claims (6)

[Claims] 1. An amplifier having a reference voltage source connected to a negative input, a first P-channel MOSFET for supplying a load current having an output and a gate of the amplifier, a power supply terminal and a source, and an output terminal and a drain, and the output. A power regulator circuit having a first resistor and a second resistor connected in series between a terminal and a ground terminal, wherein a positive input of the amplifier is connected to a connection point between the first resistor and the second resistor, the first P-channel MOSFET A second P-channel MOSFET having a drain connected to the output terminal via a third resistor, a source on the drain side of the second P-channel MOSFET in the third resistor, and a gate on the output terminal side. Connected 3rd P
A channel MOSFET and the third P channel MO
A first N connecting the ground terminal and the base via the drain of the SFET and the fourth and fifth resistors, the power supply terminal and the collector via the sixth resistor, and the ground terminal and the emitter.
A power supply regulator circuit comprising a PN transistor, a fourth P-channel MOSFET in which a collector and a gate of the first NPN transistor, the power supply terminal and a source, and a gate and a drain of the first P-channel MOSFET are connected. 2. The fourth P-channel MOS according to claim 1.
A power supply regulator circuit using a PNP transistor instead of an FET. 3. A first amplifier connected to a reference voltage source and a negative input, and a first P-channel MOSFET for supplying a load current connecting an output and a gate of the first amplifier, a power supply terminal and a source, and an output terminal and a drain. And a first and a second resistor connected in series between the output terminal and the ground terminal, wherein the positive input of the first amplifier is connected to the connection point of the first resistor and the second resistor. A second P-channel MOSFET having a current mirror formed with the first P-channel MOSFET and having a drain connected to the output terminal via a third resistor; a source on the drain side of the second P-channel MOSFET in the third resistor; 3rd P with a gate connected to the output terminal side
A channel MOSFET and the third P channel MO
A first N connecting the ground terminal and the base via the drain of the SFET and the fourth and fifth resistors, the power supply terminal and the collector via the sixth resistor, and the ground terminal and the emitter.
A PN transistor, a collector and a gate of the first NPN transistor, a power supply terminal and a source, a fourth P-channel MOSFET connecting the gate and drain of the first P-channel MOSFET, a reference voltage source, a positive input, and an output terminal A negative amplifier, a second amplifier in which a connection point between the fourth resistor and the fifth resistor is connected to an output, a current mirror with the first P-channel MOSFET, and a drain to the output terminal via a seventh resistor. A sixth P-channel MOSFET having a source connected to the drain side of the fifth P-channel MOSFET in the seventh resistor and a gate connected to the output terminal side of the fifth P-channel MOSFET connected to the sixth resistor;
A power supply regulator circuit, wherein a drain current of a channel MOSFET is used as a bias current of the second amplifier. 4. A sixth P-channel MOS according to claim 3.
A power supply regulator circuit using a PNP transistor instead of an FET. 5. A first amplifier connected to a reference voltage source and a negative input, and a first P-channel MOSFET for supplying a load current connecting an output and a gate of the first amplifier, a power supply terminal and a source, and an output terminal and a drain. And a first and a second resistor connected in series between the output terminal and the ground terminal, wherein the positive input of the first amplifier is connected to the connection point of the first resistor and the second resistor. A second amplifier having a positive input connected to the power supply terminal via an eighth resistor and grounded via a constant current source, and a negative input connected to the power supply terminal via a ninth resistor, and the first P-channel A seventh P-channel MOSFET in which the gate and the drain of the MOSFET are commonly connected to each other and the negative input and the source of the second amplifier are connected to each other. A base connected to the output of the second amplifier and grounded via fourth and fifth resistances connected in series, a collector connected to the power supply terminal via a sixth resistance, and an emitter connected to the power supply via a tenth resistance. First connected to ground terminal
NPN transistor, collector and gate of the first NPN transistor, the power supply terminal and source, the first P
A fourth P-channel MOSFET in which the gate and drain of the channel MOSFET are connected, and a second NPN in which the power supply terminal, collector and base are connected and diode-connected
A transistor, an eighth P-channel MOSFET in which an emitter and a source of the second NPN transistor and a gate of the first P-channel MOSFET are connected to each other
And a positive input connected in series with the reference voltage source.
A drain point of the eighth P-channel MOSFET, including a connection point of the first and twelfth resistors, a negative input of the output terminal, and a third amplifier connected to the connection points of the fourth and fifth resistors of which outputs are connected in series. Is a bias current of the third amplifier. 6. The fourth P-channel MOS according to claim 5.
A power supply regulator circuit using a PNP transistor instead of an FET.