JP2006350722A - Constant voltage circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a constant voltage circuit provided with an overcurrent protection circuit having a fold-back type drooping characteristic, which is capable of reducing power consumption to power consumption approximately equivalent to that for load short-circuit regardless of falling into a partial short-circuit state of a load. <P>SOLUTION: When an overcurrent protection circuit 3 is operated to reduce an output voltage Vout to a prescribed voltage or reduce an output current iout to a prescribed current value, a voltage reduction circuit 4 is operated to turn off a switching element SW, and supply of the output voltage Vout to a series circuit of resistances R3 and R4 is broken, and a divided voltage V1 is reduced to 0V, whereby the output current iout becomes a prescribed short-circuit current. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a constant voltage circuit including an overcurrent protection circuit that limits an output current, and more particularly, an overcurrent protection circuit that can significantly reduce power loss in an output transistor and a load when an output terminal is in a partial short state. The present invention relates to a constant voltage circuit comprising:

Conventionally, an overcurrent protection circuit is generally added to a constant voltage circuit to protect a load or an output transistor from an overcurrent. Generally used overcurrent protection circuits include a current limiting type that suppresses an increase in output current when the output current reaches a predetermined current value, and a decrease in output current when the output current exceeds the predetermined current value. There was a type with a so-called “figure-shaped characteristic” in which the output voltage was lowered while being reduced.
FIG. 7 is a diagram showing a conventional example of a constant voltage circuit provided with an overcurrent protection circuit of a type having “F-shaped characteristics”.
In FIG. 7, a constant voltage circuit 100 that constitutes a series regulator converts an input voltage Vin input to an input terminal IN into a predetermined constant voltage and outputs it to a load 110 connected to an output terminal OUT.

The constant voltage circuit 100 includes a reference voltage generation circuit 101 that generates and outputs a predetermined reference voltage Vref, an error amplifier circuit AMP, an output transistor M101 including an enhancement type PMOS transistor (hereinafter referred to as a PMOS transistor), and an output voltage detection Resistors R101 and R102 and an overcurrent protection circuit 102.
The overcurrent protection circuit 102 includes four PMOS transistors M102, M103, M106, M107, two depletion type NMOS transistors M104, M105, three resistors R103 to R105, and a current source i101. The PMOS transistors M102 and M103, the depletion type NMOS transistors M104 and M105, and the current source i101 form a differential amplifier circuit.

  The drain current id106 of the PMOS transistor M106 is proportional to the drain current id101 of the output transistor M101. The drain current id106 of the PMOS transistor M106 is supplied to the resistor R105 and converted into the voltage Vb, and the voltage Vb is input to the gate of the depletion type NMOS transistor M105 that forms one input terminal of the differential amplifier circuit. . A voltage Va obtained by dividing the output voltage Vout by the resistor R103 and the resistor R104 is input to the gate of the depletion type NMOS transistor M104 that forms the other input terminal of the differential amplifier circuit.

FIG. 8 is a diagram illustrating the relationship between the output current iout (= id101) and the output voltage Vout when the overcurrent protection circuit 102 is activated, and the output current iout and the power consumption PW101 of the output transistor M101.
As can be seen from FIG. 8, as the drain current id101 of the output transistor M101 increases, the drain current id106 of the PMOS transistor M106 also increases, so that the voltage drop of the resistor R105 increases and the voltage Vb also increases. When the voltage Vb increases, the drain voltage of the depletion type NMOS transistor M105 decreases, so the impedance of the PMOS transistor M107 decreases, the gate voltage of the output transistor M101 increases, and the drain current id101 of the output transistor M101 is limited. .

  When the drain current id101 of the output transistor M101 reaches a predetermined current (500 mA in FIG. 8), the drain current id101 of the output transistor M101 cannot be increased by the action of the PMOS transistor M107, and the output voltage Vout starts to decrease (FIG. 8). A point). When the output voltage Vout decreases, the voltage Va input to the other input terminal of the differential amplifier circuit also decreases. Therefore, the gate voltage Vb of the depletion type NMOS transistor M105 is higher than the gate voltage Va of the depletion type NMOS transistor M104. And the drain voltage of the depletion type NMOS transistor M105 further decreases. As a result, the drain current id101 of the output transistor M101 further decreases, and at the same time, the output voltage Vout further decreases. Since such an operation is repeated, the relationship between the output current iout and the output voltage Vout during operation of the overcurrent protection circuit 102 is such that the output voltage Vout and the output current iout simultaneously decrease as shown by the broken line in FIG.

  The power PW101 consumed by the output transistor M101 during operation of the overcurrent protection circuit 102 is indicated by a solid line in FIG. 8, which is that the input voltage Vin is 3.6V, the rated output voltage is 3V, and the overcurrent protection circuit The case where the short circuit current is 40 mA is shown. As can be seen from FIG. 8, the peak value of the power consumption PW101 of the output transistor M101 is about 570 mW when the output current iout is about 300 mA. In addition, when the load is short-circuited, the power consumption is very small at 144 mW, but when the output current iout is around 300 mA, it is 1/3 or less compared to the maximum value of 1800 mW in the case of an overcurrent protection circuit with only current limiting. However, it still consumes considerable power.

In particular, when a device breaks down, a so-called partial short state often occurs in which the current flowing through the load 110 is smaller than the case where the load 110 is short-circuited. For this reason, the load current is stabilized at 200 mA to 300 mA, and the state where the power consumption is large may be sustained for a long time. If such a state continues for a long time, the temperature of the device rises due to the heat generated by the output transistor M101 and the load 110, and there is a risk that the device will malfunction.
FIG. 9 is a circuit diagram showing another example of a conventional overcurrent protection circuit (see, for example, Patent Document 1).

The circuit shown in FIG. 9 has the characteristics shown in FIG. 10 and has first and second “f-shaped characteristics”. The output current iout and the output voltage Vout at the point A By switching from the “2” character property to the first “1” character property, it has an “A character property” as shown by a solid line.
In the overcurrent protection circuit as shown in FIG. 9, the output current of the second U-shaped characteristic can be decreased more rapidly than in the case of FIG. In the output current region until it starts to work, the power consumption of the output transistor Q1 can be made smaller than that of a normal “f-shaped” overcurrent protection circuit.
JP-A-6-291558

However, the conventional overcurrent protection circuit having the U-shaped characteristic greatly reduces the output current when the load is short-circuited and the output voltage Vout drops to near 0 V, greatly reducing the power consumption of the output transistor and the load. However, in a so-called partial short state where the output voltage does not sufficiently decrease, the power consumption cannot be reduced much.
Further, even if two “f-character characteristics” as shown in FIG. 9 are switched, the improvement in power consumption in the vicinity of the point A shown in FIG. 10 cannot be expected so much. Furthermore, there is a problem that the short-circuit current increases and the power consumption when the load is short-circuited increases.

  The present invention has been made in order to solve the above-described problems. Even when the load is in a partial short state, the U-shaped characteristic can be suppressed to substantially the same power consumption as when the load is short-circuited. An object of the present invention is to obtain a constant voltage circuit including an overcurrent protection circuit.

The constant voltage circuit according to the present invention includes an output transistor that outputs a current corresponding to a signal input to the control electrode from the input terminal to the output terminal;
An output voltage controller that generates a predetermined reference voltage and generates a first proportional voltage proportional to the voltage of the output terminal, and controls the operation of the output transistor so that the first proportional voltage becomes the reference voltage;
An overcurrent protection circuit unit that limits the output current to the output transistor so that the current output from the output transistor does not exceed a predetermined value;
In a constant voltage circuit that converts the input voltage input to the input terminal into a predetermined constant voltage and outputs it to the output terminal,
The overcurrent protection circuit unit is
A second proportional voltage proportional to the voltage of the output terminal is generated, and a proportional current proportional to the output current of the output transistor is generated and converted into a voltage, and a difference between the second proportional voltage and the converted voltage is calculated. By amplifying and outputting to the control electrode of the output transistor, when the current output from the output transistor exceeds a first predetermined value, the output current from the output transistor is reduced to a predetermined value while lowering the voltage at the output terminal. An overcurrent protection circuit having a U-shaped characteristic for reducing to a short-circuit current;
A voltage lowering circuit that reduces the second proportional voltage to a ground voltage when the proportional current becomes a predetermined second predetermined value smaller than the first predetermined value;
Is provided.

  Specifically, the overcurrent protection circuit includes an output voltage detection circuit that divides the voltage of the output terminal to generate and output the second proportional voltage, and the voltage reduction circuit includes the proportional current when the proportional current is the first voltage. 2 When the predetermined value is reached, the supply of the voltage at the output terminal to the output voltage detection circuit is cut off.

  In this case, the output voltage control unit amplifies a difference between the reference voltage and the first proportional voltage by using the second proportional voltage as the first proportional voltage, and outputs the amplified difference to the control electrode of the output transistor. did.

  The output voltage detection circuit divides the voltage of the output terminal to generate the first proportional voltage, and the output voltage control unit and the overcurrent protection circuit share the output voltage detection circuit. Also good.

  The overcurrent protection circuit unit limits the output current to a third predetermined value when the output current from the output transistor reaches a third predetermined value between the first predetermined value and the second predetermined value. However, a current limiting circuit for controlling the operation of the output transistor may be provided so that the voltage at the output terminal decreases.

  According to the constant voltage circuit of the present invention, it is possible to detect a partial short state of an overcurrent protection circuit having a U-shaped characteristic and shift to a load short-circuit state by adding a small number of components. The output current at the time of load short-circuit can be instantaneously transferred without staying in the partial short state that consumes a long time, and the heat generation at the time of failure can be greatly reduced, preventing the occurrence of malfunction of the equipment be able to.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a diagram showing a circuit example of a constant voltage circuit according to the first embodiment of the present invention. FIG. 1 shows an example in which the constant voltage circuit is used as a series voltage regulator.
In FIG. 1, a constant voltage circuit 1 converts an input voltage Vin input to an input terminal IN into a predetermined constant voltage and outputs it to a load 10 connected to an output terminal OUT.
The constant voltage circuit 1 includes a reference voltage generation circuit 2 that generates and outputs a predetermined reference voltage Vref, an error amplifier circuit AMP, an output transistor M1 formed of a PMOS transistor, output voltage detection resistors R1 and R2, The overcurrent protection circuit 3 and the voltage drop circuit 4 are configured.

The overcurrent protection circuit 3 includes four PMOS transistors M2, M3, M6, and M7, two depletion type NMOS transistors M4 and M5, three resistors R3 to R5, and a current source i1. The PMOS transistors M2 and M3, the depletion type NMOS transistors M4 and M5, and the current source i1 form a differential amplifier circuit.
The voltage drop circuit 4 includes a PMOS transistor M8, a depletion type NMOS transistor M9, an AND circuit A1, a current source i2, and a switching element SW. The reference voltage generation circuit 2, the error amplifier circuit AMP, and the resistors R1 and R2 form an output voltage control unit, and the overcurrent protection circuit 3 and the voltage drop circuit 4 form an overcurrent protection circuit unit. The resistors R3 and R4 form an output voltage detection circuit.

An output transistor M1 is connected between the input terminal IN and the output terminal OUT, and resistors R1 and R2 are connected in series between the output terminal OUT and the ground voltage. The resistors R1 and R2 divide the output voltage Vout to generate a divided voltage Vfb, which is output to the non-inverting input terminal of the error amplifier circuit AMP. The reference voltage Vref is input to the inverting input terminal of the error amplifier circuit AMP, and the error amplifier circuit AMP controls the operation of the output transistor M1 so that the divided voltage Vfb becomes the reference voltage Vref. A load 10 is connected between the output terminal OUT and the ground voltage.
Further, the switching element SW and the resistors R3 and R4 are connected in series between the output terminal OUT and the ground voltage. When the switching element SW is turned on and is in the conductive state, the resistors R3 and R4 are The divided voltage V1 is generated by dividing Vout and supplied to the gate of the depletion type NMOS transistor M4.

  The depletion type NMOS transistors M4 and M5 form a differential pair, the sources of the depletion type NMOS transistors M4 and M5 are connected, and a current source i1 is connected between the connection and the ground voltage. A predetermined bias current is supplied to the differential pair. Further, the PMOS transistors M2 and M3 form a current mirror circuit, and constitute a load of the differential pair. The gates of the PMOS transistors M2 and M3 are connected, and the connection is connected to the drain of the PMOS transistor M2. Each source of the PMOS transistors M2 and M3 is connected to the input voltage Vin. A PMOS transistor M6 and a resistor R5 are connected in series between the input voltage Vin and the ground voltage, and the connection is connected to each gate of the depletion type NMOS transistors M5 and M9. The gate of the PMOS transistor M6 is connected to the gate of the output transistor M1, and the PMOS transistor M6 outputs a drain current id6 proportional to the drain current id1 of the output transistor M1.

  A PMOS transistor M7 is connected between the input voltage Vin and the gate of the output transistor M1, and the gate of the PMOS transistor M7 is a connection portion between the PMOS transistor M3 and the depletion type NMOS transistor M5 that form the output terminal of the differential amplifier circuit. It is connected to the. A PMOS transistor M8, a depletion type NMOS transistor M9 and a current source i2 are connected in series between the input voltage Vin and the ground voltage, and the gate of the PMOS transistor M8 is connected to the PMOS transistor M3 and the depletion type NMOS transistor M5. Connected to the connection. A connection portion between the PMOS transistor M8 and the depletion type NMOS transistor M9 is connected to one input terminal of the AND circuit A1, and the activation signal Sc is input to the other input terminal of the AND circuit A1 from the outside. Switching of the switching element SW is controlled by the output signal of the AND circuit A1.

In such a configuration, the currents flowing through the resistors R1 and R2 and the currents flowing through the resistors R3 and R4 are negligibly small compared with the output current iout output from the output terminal OUT to the load 10, so that the output transistor The description will be made assuming that the drain current id1 of M1 is equal to the output current iout.
FIG. 2 is a diagram showing a characteristic example of output voltage Vout−output current iout in the constant voltage circuit 1 of FIG. 1 and a characteristic example of power consumption PW1−output current iout of the output transistor M1, and refer to FIG. The operation of the constant voltage circuit 1 will now be described. 2 is an example in which the input voltage Vin is 3.6 V, the rated output voltage of the constant voltage circuit 1 is 3 V, and the short-circuit current of the overcurrent protection circuit 3 is 40 mA. Is shown.

The activation signal Sc input to one input terminal of the AND circuit A1 is at a low level when the constant voltage circuit 1 is activated, but becomes a high level after the output voltage Vout rises to the rated voltage. When the overcurrent protection circuit 3 is not operating, the PMOS transistor M8 is off and the drain of the PMOS transistor M8 is at a low level, so that the constant voltage circuit 1 is operating normally. In the meantime, the output terminal of the AND circuit A1 is at a low level.
The switching element SW is composed of a PMOS transistor or the like, and is turned on when a low level signal is input to the control electrode and becomes conductive, and is turned off when a high level signal is input to the control electrode. It will be cut off. That is, while the constant voltage circuit 1 is operating normally, the switching element SW is on.

  In this state, as the drain current id1 of the output transistor M1 increases, the drain current id6 of the PMOS transistor M6 also increases, so that the voltage drop of the resistor R5 increases and the voltage V2 also increases. When the voltage V2 increases, the drain voltage of the depletion type NMOS transistor M5 decreases, so the impedance of the PMOS transistor M7 decreases, the gate voltage of the output transistor M1 increases, and the drain current id1 of the output transistor M1 is limited. .

  When the drain current id1 of the output transistor M1 reaches a predetermined current (500 mA in FIG. 2), the drain current id1 of the output transistor M1 cannot be increased by the action of the PMOS transistor M7, and the output voltage Vout starts to decrease. Note that the power consumption of the output transistor M1 at this time is about 300 mW at point A in FIG. When the output voltage Vout decreases, the divided voltage V1 also decreases. Therefore, the gate voltage V2 of the depletion type NMOS transistor M5 becomes larger than the gate voltage V1 of the depletion type NMOS transistor M4, and the drain voltage of the depletion type NMOS transistor M5 becomes Further decrease. As a result, the drain current id1 of the output transistor M1 further decreases, and at the same time, the output voltage Vout further decreases.

  Since the source and gate of the PMOS transistor M8 are connected in common with the PMOS transistor M7, the impedance of the PMOS transistor M8 decreases as the output voltage Vout decreases, and the drain voltage of the PMOS transistor M8 gradually increases. When the output voltage Vout decreases to a predetermined voltage or when the output current iout decreases to a predetermined current value, one input terminal of the AND circuit A1 is set to a high level. For this reason, the output signal of the AND circuit A1 is inverted from the low level to the high level. Until the output voltage Vout or the output current iout reaches a predetermined value, that is, until the point B in FIG. 2 is reached, the power consumption of the output transistor M1 is the same as the conventional one.

  When the output signal of the AND circuit A1 changes to the high level, the switching element SW is switched from on to off, so that the current supply to the resistors R3 and R4 is stopped, and the divided voltage V1 decreases to 0V. Then, the overcurrent protection circuit 3 controls the gate voltage of the output transistor M1 so as to reduce the output current iout to 40 mA that is a short-circuit current at once. As a result, the power consumption PW1 of the output transistor M1 is a value from about 560 mW at the point B in FIG. 2 to any value from the point C to the point D, and decreases rapidly to any value in the range from 66 to 144 mW. That is, the power consumption of the output transistor M1 is set by setting the value of the output voltage Vout or the output current iout at the point B in FIG. 2 to be larger than the output current iout or the output voltage Vout at the time of the assumed partial short. In the graph of PW1, since the value shifts from the point C to the point D without staying long from the point A to the point B, the heat generation of the output transistor M1 and the load 10 can be suppressed.

  In FIG. 2, a thin broken line indicates a state where the overcurrent protection circuit 3 is not operated, that is, a state where the output voltage Vout is the rated voltage 3 V, and a thick broken line indicates a state where the overcurrent protection circuit 3 is activated. Changes in the output voltage Vout and the output current iout are shown. A solid line indicates a change in the power consumption PW1 of the output transistor M1, and a thin solid line portion connected with the thick solid line to draw an arc indicates the power consumption of the output transistor of the conventional circuit. In FIG. 2, a portion indicated by a one-dot chain line indicates a conventional U-shaped characteristic, and a portion indicated by a two-dot chain line does not actually exist for the power consumption PW1 of the output transistor M1. Shows the part.

In FIG. 1, the divided voltage V1 may be substituted for the divided voltage Vfb. In this case, FIG. 1 is as shown in FIG.
3 differs from FIG. 1 in that the resistors R1 and R2 in FIG. 1 are deleted and the divided voltage V1 is input to the non-inverting input terminal of the error amplifier circuit AMP. Since it is the same as FIG. 1, its description is omitted. In FIG. 3, the same voltage is input to the non-inverting input terminal of the error amplifier circuit AMP and the gate of the depletion type NMOS transistor M4, but three or more resistors are used instead of the resistors R3 and R4. It is connected in series so that two or more divided voltages can be output, and the different divided voltages correspond to the non-inverting input terminal of the error amplifier circuit AMP and the gate of the depletion type NMOS transistor M4, respectively. May be input.

FIG. 4 is a diagram illustrating another circuit example of the voltage drop circuit 4 of FIG. 1, and the circuit of FIG. 4 may be used instead of the voltage drop circuit 4 of FIG. In FIG. 4, the same components as those in FIG. 1 are denoted by the same reference numerals.
4 includes PMOS transistors M11 and M12, an NMOS transistor M13, a current source i3, and resistors R11 and R12.
Resistors R11 and R12 are connected in series between the output terminal OUT and the ground voltage. A divided voltage V3 obtained by dividing the output voltage Vout by the resistors R11 and R12 is input to the gate of the PMOS transistor M13. Further, a PMOS transistor M13 and a current source i3 are connected in series between the output terminal OUT and the ground voltage, and a connection portion between the drain of the PMOS transistor M13 and the current source i3 is a PMOS transistor M11 and an NMOS transistor. It is connected to each gate of M12. Further, a PMOS transistor M11 and an NMOS transistor M12 are connected in series between the output terminal OUT and the ground voltage, and a connection portion between the PMOS transistor M11 and the NMOS transistor M12 is connected to a control electrode of the switching element SW. Yes.

When the output voltage Vout is the rated voltage, since the voltage across the resistor R11 is large, the impedance of the PMOS transistor M13 is small and the drain voltage of the PMOS transistor M13 is large. The drain voltage exceeds the threshold value of the inverter composed of the PMOS transistor M11 and the NMOS transistor M12, and a low level signal is input to the control electrode of the switching element SW. It is in a state.
Next, when the output voltage Vout decreases and the voltage across the resistor R11 decreases, the impedance of the PMOS transistor M13 increases, the drain voltage of the PMOS transistor M13 decreases, and the PMOS transistor M11 and the NMOS transistor M12 are configured. A high level signal is output from the inverter to the control electrode of the switching element SW. For this reason, the switching element SW is turned off, and the divided voltage V1 in FIG. 1 is reduced to 0V.

Further, when the constant voltage circuit 1 starts up, if the output voltage Vout rises, the PMOS transistor M13 is turned on to turn on the switching element SW, so that the activation signal Sc in FIG. 1 is not necessary.
Various methods are conceivable for the voltage drop circuit added to the overcurrent protection circuit having a U-shaped characteristic. However, any method that reduces the divided voltage V1 to 0 V in the middle of the F-shaped characteristic can be applied to the present invention. Needless to say, it is included.

  As described above, in the constant voltage circuit according to the first embodiment, when the overcurrent protection circuit 3 operates and the output voltage Vout decreases to a predetermined voltage, or the output current iout decreases to a predetermined current value. In this case, the voltage reduction circuit 4 is operated to reduce the divided voltage V1 to 0 V, so that the output current iout becomes a predetermined short-circuit current. As a result, the output current can be instantaneously transferred to the short-circuit current when the load is short-circuited without staying in a partial short state that consumes large power for a long time. The power consumption can be reduced to almost the same level.

Second embodiment.
A current limiting circuit may be added to the first embodiment, and this is the second embodiment of the present invention.
FIG. 5 is a circuit diagram showing an example of a constant voltage circuit according to the second embodiment of the present invention. 5 shows an example in which the circuit configuration of FIG. 1 is provided. The same or similar parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted here and the difference from FIG. Only the point will be described.
5 is different from FIG. 1 in that a current limiting circuit 5 is added. Accordingly, the constant voltage circuit 1 of FIG. 1 is changed to a constant voltage circuit 1a.
In FIG. 5, the constant voltage circuit 1a converts the input voltage Vin input to the input terminal IN into a predetermined constant voltage, and outputs it to the load 10 connected to the output terminal OUT.
The constant voltage circuit 1a includes a reference voltage generation circuit 2, an error amplification circuit AMP, an output transistor M1, output voltage detection resistors R1 and R2, an overcurrent protection circuit 3, a voltage drop circuit 4, and an output current. The current limiting circuit 5 limits the iout so as not to exceed a predetermined current value and reduces only the output voltage Vout.

The current limiting circuit 5 includes PMOS transistors M20 and M21, enhancement type NMOS transistors (hereinafter referred to as NMOS transistors) M22 and M23, and a resistor R21.
A PMOS transistor M20 and an NMOS transistor M22 are connected in series between the input voltage Vin and the ground voltage, and the gate of the PMOS transistor M20 is connected to the gate of the output transistor M1. The NMOS transistor M22 forms a current mirror circuit with the NMOS transistor M23, the gates of the NMOS transistors M22 and M23 are connected, and the connection is connected to the drain of the NMOS transistor M22. The drain of the NMOS transistor M23 is connected to the input voltage Vin via the resistor R21, and the source of the NMOS transistor M23 is grounded. A PMOS transistor M21 is connected between the input voltage Vin and the gate of the output transistor M1, and the gate of the PMOS transistor M21 is connected to a connection portion between the resistor R21 and the NMOS transistor M23.

The drain current id20 of the PMOS transistor M20 is a current proportional to the drain current id1 of the output transistor M1. The current mirror circuit composed of the NMOS transistors M22 and M23 supplies a current proportional to the drain current id20 to the resistor R21 and supplies the voltage V4 to the gate of the PMOS transistor M21. When the output current iout increases and reaches a predetermined limit current value, for example, 400 mA, the gate voltage of the output transistor M1 is controlled by the action of the PMOS transistor M21 to suppress the increase in the output current iout and lower the output voltage Vout.
FIG. 6 is a diagram illustrating a characteristic example of output voltage Vout−output current iout and a characteristic example of power consumption PW1−output current iout of the output transistor M1 in the constant voltage circuit 1a of FIG. 6 is similar to FIG. 2 in that the input voltage Vin is 3.6V, the rated output voltage of the constant voltage circuit 1 is 3V, and the short-circuit current of the overcurrent protection circuit 3 is as follows. The case where it is 40 mA is shown as an example.

The operation of the constant voltage circuit 1a will be described with reference to FIG.
When the output current iout reaches 400 mA, which is the limit current value, the output voltage Vout decreases due to the action of the current limit circuit 5 as described above. The power consumption PW1 of the output transistor M1 at this time is 240 mW at point A in FIG. When the output voltage Vout further decreases and decreases to a point where it intersects the U-shaped characteristic of the overcurrent protection circuit 3, the overcurrent protection circuit 3 starts to operate, and both the output voltage Vout and the output current iout decrease. The power consumption PW1 of the output transistor M1 at this time is about 500 mW at point B in FIG. Since the subsequent operation is the same as that in FIG. 1, the description thereof is omitted.

  As described above, the constant voltage circuit according to the second embodiment is obtained by adding a current limiting circuit to the first embodiment. Even in such a case, the constant voltage circuit is the same as the first embodiment. Similar effects can be obtained.

It is the figure which showed the circuit example of the constant voltage circuit in the 1st Embodiment of this invention. FIG. 2 is a diagram illustrating a characteristic example of output voltage Vout−output current iout in FIG. 1 and a characteristic example of power consumption PW1−output current iout. It is the figure which showed the other circuit example of the constant voltage circuit in the 1st Embodiment of this invention. FIG. 6 is a diagram illustrating another circuit example of the voltage drop circuit 4. It is the circuit diagram which showed the example of the constant voltage circuit in the 2nd Embodiment of this invention. FIG. 6 is a diagram illustrating a characteristic example of output voltage Vout−output current iout and a characteristic example of power consumption PW1−output current iout in FIG. It is the figure which showed the prior art example of the constant voltage circuit provided with the overcurrent protection circuit. FIG. 8 is a diagram illustrating a characteristic example of output voltage Vout−output current iout and a characteristic example of power consumption PW101−output current iout in FIG. It is the circuit diagram which showed the other example of the conventional constant voltage circuit. It is the figure which showed the example of a characteristic of the constant voltage circuit of FIG.

Explanation of symbols

1, 1a Constant voltage circuit 2 Reference voltage generation circuit 3 Overcurrent protection circuit 4 Voltage drop circuit 5 Current limit circuit 10 Load M1 Output transistor AMP Error amplification circuit R1, R2 Resistance

Claims (5)

An output transistor for outputting a current corresponding to a signal input to the control electrode from the input terminal to the output terminal;
An output voltage controller that generates a predetermined reference voltage and generates a first proportional voltage proportional to the voltage of the output terminal, and controls the operation of the output transistor so that the first proportional voltage becomes the reference voltage;
An overcurrent protection circuit unit that limits the output current to the output transistor so that the current output from the output transistor does not exceed a predetermined value;
In a constant voltage circuit that converts the input voltage input to the input terminal into a predetermined constant voltage and outputs it to the output terminal,
The overcurrent protection circuit unit is
A second proportional voltage proportional to the voltage of the output terminal is generated, and a proportional current proportional to the output current of the output transistor is generated and converted into a voltage, and a difference between the second proportional voltage and the converted voltage is calculated. By amplifying and outputting to the control electrode of the output transistor, when the current output from the output transistor exceeds a first predetermined value, the output current from the output transistor is reduced to a predetermined value while lowering the voltage at the output terminal. An overcurrent protection circuit having a U-shaped characteristic for reducing to a short-circuit current;
A voltage lowering circuit that reduces the second proportional voltage to a ground voltage when the proportional current becomes a predetermined second predetermined value smaller than the first predetermined value;
A constant voltage circuit comprising:   The overcurrent protection circuit includes an output voltage detection circuit that divides the voltage of the output terminal to generate and output the second proportional voltage, and the voltage reduction circuit includes the proportional current when the proportional current reaches the second predetermined value. 2. The constant voltage circuit according to claim 1, wherein supply of the voltage of the output terminal to the output voltage detection circuit is cut off.   The output voltage control unit uses the second proportional voltage as the first proportional voltage, amplifies a difference between the reference voltage and the first proportional voltage, and outputs the amplified voltage to a control electrode of the output transistor. The constant voltage circuit according to claim 2.   The output voltage detection circuit divides a voltage of the output terminal to generate the first proportional voltage, and the output voltage control unit and the overcurrent protection circuit share the output voltage detection circuit. The constant voltage circuit according to claim 2. When the output current from the output transistor reaches a third predetermined value between the first predetermined value and the second predetermined value, the overcurrent protection circuit unit limits the output current to a third predetermined value. 5. The constant voltage circuit according to claim 1, further comprising a current limiting circuit that controls an operation of the output transistor so that a voltage of the output terminal decreases.

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