JP2003185708A - Ic tester - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow use in both a per-pin system and a shared system. <P>SOLUTION: The present invention provides an improved IC tester for testing a tested object. This tester has a memory part for storing a test program for testing the tested object, and a control means for conducting control by the per-pin system and the shared system by the test program stored in the memory part, based on the per-pin system and the shared system. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester for testing an object to be tested, for example, IC, LSI, etc., and relates to an IC tester usable in both the per-pin system and the shared system.

[0002]

2. Description of the Related Art An IC tester is an object to be tested (hereinafter referred to as DUT).
(Abbreviated), for example, a test pattern is given to an IC, an LSI or the like, the output of the DUT is compared with an expected value pattern, and the quality is judged. The IC tester has a per pin system and a shared system. Per pin method is D
The shared system is a configuration in which a pattern memory or the like is provided for each UT, and the shared system is a configuration in which a pattern memory or the like is provided for each of a plurality of pins of the DUT. Such a device will be described below.

First, a per-pin type IC tester will be described with reference to FIG. In FIG. 4, the test head 1 is electrically connected to a DUT (not shown) and is provided with a plurality of pin electronics 11. The pin electronics 11 is electrically connected to the DUT and performs at least one of signal transmission and reception. Further, the pin electronics 11 usually shows a device having a driver, a comparator and the like, but it also includes a timing generator and the like. That is, the pin electron varnish 11 may have any configuration capable of exchanging signals with the DUT. The main body 2 is electrically connected to the test head 1 to control the whole, and is provided with a plurality of pattern memories 21. The pattern memory 21 stores a test pattern including a test pattern and an expected value pattern, and outputs the test pattern to the pin electronics 11.

The operation of such a device will be described below.
The pattern memory 21 sequentially outputs the test patterns in accordance with the address instruction of the control means (not shown). With this test pattern, the pin electronics 11 provides the test pattern to the DUT. The DUT outputs based on the test pattern, and the pin electronics 11 inputs this output and compares the output with the expected value pattern of the test pattern to determine pass / fail.

Next, a shared type IC tester will be described with reference to FIG. In FIG. 5, the test head 3 is electrically connected to a DUT (not shown) and is provided with a plurality of pin electronics 31 and 32. The pin electronics 31 and 32 are electrically connected to the first and second DUTs, respectively, and perform at least one of signal transmission and reception. The main body 4 is electrically connected to the test head 3 to control the whole and is provided with a plurality of pattern memories 41. The pattern memory 41 stores a test pattern including a test pattern and an expected value pattern, and stores the test pattern in the pin electronics 31, 32.
Output to.

The operation of such a device will be described below.
The pattern memory 41 sequentially outputs the test patterns in accordance with the address instruction of the control means (not shown). With this test pattern, the pin electronics 31 and 32 give the same test pattern to the first and second DUTs, respectively. First and second DUT
Output to the pin electronics 31 and 32, respectively, based on the test pattern. Pin Electronics 3
Reference numerals 1 and 32 respectively compare the output of the first and second DUTs with the expected value pattern of the test pattern to determine pass / fail.

[0007]

Since the per-pin type IC tester has an individual pattern memory 21 for each pin (pin electronics 11), each pin can operate independently. However, since the pattern memory 21 must be provided for each pin, the IC tester becomes expensive.

On the other hand, in the shared type IC tester, the pattern memory 41 is shared by a plurality of pins (pin electronics 31, 32). Therefore, the pins sharing the same pattern memory 41 perform the same operation. Therefore,
It is used when a plurality of DUTs are simultaneously inspected, or when pins having the same function as the DUTs are inspected at the same time. Since the pattern memory 41 is provided for each of a plurality of pins, the IC tester can be made inexpensive, but the flexibility of pin operation is limited.

As described above, the characteristics of the per-pin type and shared type IC testers are different. Therefore, at the time of introduction, IC
I had to choose one considering the price of the tester and future test plans.

Therefore, an object of the present invention is to use a per pin system,
It is to realize an IC tester that can be used for both shared systems.

[0011]

According to a first aspect of the present invention, in an IC tester for testing an object to be tested, a storage unit for storing a test program for testing the object to be tested, a per-pin system and a shared system are provided. Based on the test program of the storage unit, there is provided a control means for performing control in a per pin system or a shared system.

According to a second aspect of the present invention, in the present invention according to the first aspect, a pattern memory that stores a test pattern and can output a plurality of outputs, a switching unit that switches the output of the pattern memory, and this switching are provided. It is characterized in that a recognition means for recognizing the per-pin system or the shared system and instructing the control means is provided according to the switching state of the parts.

According to a third aspect of the present invention, in the present invention according to the first aspect, a DC source for performing a plurality of outputs or a plurality of measurements of a DC current and a voltage, and a switching unit for switching between outputs or measurements of the DC source. And a recognition means for recognizing the per-pin system or the shared system and instructing the control means according to the switching state of the switching unit.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, the test head 5 is a DUT.
A plurality of pin electronics 51 are provided that are electrically connected to A and B. The pin electronics 51 is
It is electrically connected to DUTA and B to perform at least one of signal transmission and reception. Further, although the pin electronics 51 usually shows a device having a driver, a comparator and the like, it also includes a timing generator and the like. In other words, the pin electron varnish 51 may have a configuration capable of exchanging signals with DUTA and B.

The main body 6 is electrically connected to the test head 5, and is provided with a plurality of pattern memories 61, a switching unit 62, a recognition unit 63, a storage unit 64, and a control unit 65. The pattern memory 61 stores a test pattern including a test pattern and an expected value pattern, and
The output of the test pattern from 2 is given to the pin electronics 51 of the test head 5. The switching unit 62 switches the connectors 611 and 612 of the pattern memory 61. The recognizing means 63 gives an instruction for the per-pin method or the shared method according to the connection state of the test heads 5 and the switching state of the switching unit 62, and also notifies the number of the test heads 5.
The storage unit 64 stores a test program for testing DUTA, B. Here, the test program includes a tester pattern. The control unit 65 controls the entire system in a per-pin system or a shared system based on the test program in the storage unit 64 according to the instruction and the notification from the recognition unit 63.

The operation of such a device will be described below.
FIG. 2 is a flow chart showing the operation of the apparatus shown in FIG. First, the case of the shared method will be described. The contacts 611 and 612 of the pattern memory 61 are electrically connected to the pin electronics 51, respectively. Then, the switching unit 62 sets the pattern memory 61 to output from both the contacts 611 and 612. The pin electronics 51 receiving the output of the contact 611 of the pattern memory 61 is connected to one DUTA, and the pin electronics 51 receiving the output of the contact 612 of the pattern memory 61 is the other DUTB.
Connect to.

The recognition means 63 recognizes the test head 5 and switches the switching section 62, that is, the contact 61.
The settings output from both 1 and 612 are recognized. Here, the test head 5 is recognized by, for example, accessing an address assigned to the pin electronics 51 and if there is a target, recognizing that the test head 5 is present. Since the contacts 611 and 612 are both output, the recognition unit 63 instructs the control unit 65 in the shared system to notify that the number of test heads 5 is one (S).
1).

Then, the control means 65 executes the test program of the storage section 64 by the shared method under the limitation of the shared method, and stores the test pattern in the pattern memory 61. The pattern memory 61 has a control means 65.
The test patterns are sequentially output according to the address instruction of. With this test pattern, the pin electronics 51 gives the test pattern to DUTA, B. DUT
A and B output based on the test pattern, and the pin electronics 51 inputs this output, and compares the expected value pattern of the test pattern to determine pass / fail (S2.
S3).

Next, the case of the per-pin system will be described. FIG. 3 is a configuration diagram for explaining the per-pin type connection. The contact 611 of the pattern memory 61 is electrically connected to the pin electronics 51. In this case, twice as many pattern memories 61 are mounted as compared with the device shown in FIG. The contact 612 does not make a connection. Then, the switching unit 62 sets the pattern memory 61 to output only from the contact 611.

The recognition means 63 recognizes the test head 5 and switches the switching section 62, that is, the contact 611.
Recognize the setting to output from only. Since the recognition means 63 outputs only the contact 611, the recognition means 63 gives an instruction to the control means 65 to notify that the number of test heads 5 is one (S1).

Then, the control means 65 executes the test program in the storage section 64 as a per-pin method without being restricted by the shared method, and stores the test pattern in the pattern memory 61. The pattern memory 61 sequentially outputs the test patterns according to the address instruction of the control means 65. With this test pattern,
Pin electronics 51 provides the DUT with a test pattern. The DUT outputs an output based on the test pattern, and the pin electronics 51 inputs this output and compares the output with the expected value pattern of the test pattern to determine pass / fail (S2, S4).

In this way, the recognition means 63 recognizes the per-pin method or the shared method, and the control means 65 controls the per-pin method or the shared method based on the test program in the storage section 64. An IC tester can be used for both methods. As a result, it is possible to easily switch to the per-pin system or the shared system, and it is possible to eliminate the need to strictly select the per-pin system or the shared system when the IC tester is introduced, and it is possible to increase the degree of freedom. That is,
Initially, the shared system will be introduced, and at a later date, it will be possible to change to the perpin system, which has a high degree of freedom.

Although the present invention is not limited to this, the pattern memory 61 is shown to be of the per-pin type or the shared type, but the pattern memory 61 is a DC source for outputting or measuring DC current, voltage. May be provided instead of the above.

Further, in FIG. 2 showing the per-pin system,
The test head 5 may be newly provided and connected to the connector 612 of the pattern memory 61. At this time,
The switching unit 62 is set to output only one of the two when outputting to the pattern memory 61. The recognition means 63 recognizes this setting, recognizes that there are two test heads 5, and notifies the control means 65.

Although the pattern memory 61 has shown an example of performing two outputs, it is sufficient that a plurality of outputs can be performed.

[0027]

According to the present invention, since the control means performs control according to the per-pin system or the shared system based on the test program of the storage section, the IC tester can be used for both the per-pin system and the shared system. . As a result, it is possible to easily switch to the per-pin method or the shared method, and it is possible to eliminate the need to strictly select the per-pin method or the shared method when the IC tester is introduced, and it is possible to increase the degree of freedom. There is.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the apparatus shown in FIG.

FIG. 3 is an example in which the device shown in FIG. 1 is applied to a per pin system.

FIG. 4 is a diagram showing a configuration of a conventional per-pin type IC tester.

FIG. 5 is a diagram showing a configuration of a conventional shared type IC tester.

[Explanation of symbols]

61 pattern memory 611,612 connector 62 switching unit 63 recognition means 64 storage 65 Control means

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Claims (3)

[Claims] 1. An IC tester for testing an object to be tested, a storage section for storing a test program for testing the object to be tested, and a per-pin method by a test program in the storage section based on a per-pin method or a shared method. Alternatively, an IC tester having control means for performing control in a shared system. 2. A pattern memory that stores a test pattern and can output a plurality of outputs, a switching unit that switches the output of the pattern memory, and a per pin system or a shared system is recognized and controlled by the switching state of the switching unit. The IC tester according to claim 1, further comprising a recognition means for instructing the means. 3. A DC source for performing multiple outputs or multiple measurements of DC current and voltage, a switching unit for switching between outputs or measurements of this DC source, and a per pin system or a shared system depending on the switching state of the switching unit. The IC tester according to claim 1, further comprising: a recognition unit that recognizes and instructs the control unit.