JP2003185707A - Calibration circuit, ic-testing device, and method of calibrating timing - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To conduct timing calibration using a built-in circuit, in an IC testing device. <P>SOLUTION: A first waveform serving as a reference, and a second waveform delayed from the first waveform are output from a TG 12 to be input to a direct current characteristic measuring circuit 17 via a driver 14. The direct current characteristic measuring circuit 17 outputs an integrated waveform as to the input waveform, and a CPU 11 inputs the integrated waveform to find a difference between voltage values of the integrated waveforms in the first and second waveforms. The TG 12 corrects timing of the waveform to be output, based on a lag time. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a calibration circuit and the like for performing timing calibration.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a calibration circuit 600 of a conventional IC test apparatus. The calibration circuit 600 is a DUT (device under test:
DeviceUnder Test) 200 is a device for inputting a test waveform and taking in an output waveform thereof to judge pass / fail of the DUT 200. Calibration circuit 600
Is a timing generator (hereinafter referred to as TG) 6
1, pass / fail judgment circuit 13, driver 14, comparator 1
5 and a delay time measuring circuit 62. The output of the calibration circuit 600 is connected to the input / output pin of the DUT 200.

The TG 61 is a circuit for outputting a waveform to the driver 14 according to the set timing. TG61
Details of the circuit configuration will be described later.

The quality determination circuit 13 is a circuit for determining whether the DUT 200 is a good product or a defective product based on the output signal of the comparator 15.

The driver 14 applies a test waveform to the input / output pin of the DUT 200 based on the waveform input from the TG 61, and the comparator 15 applies "Hi" to the waveform output from the input / output pin of the DUT 200. Alternatively, it is a circuit for determining "Low".

The delay time measuring circuit 62 is a circuit which compares the set reference time Tref3 with the timing of the test waveform output from the driver 14 and measures the time difference.

FIG. 6 is a circuit block diagram of the TG 61. The TG 61 includes registers 21 and 25, a SET delay circuit 22, a RESET delay circuit 24, and an output buffer 23. The TG 61 operates in synchronization with the input clock signal CLK, and SE is stored in the register 21 as setting data.
The timing of generating a T (rising) edge and the timing of generating a RESET (falling) edge are input to the register 25. That is, the set time from the reference time Tref2 to the occurrence of the SET edge is input to the register 21, and the set time from the reference time Tref2 to the occurrence of the RESET edge is input to the register 25.

The SET delay circuit 22 receives timing data for SETting a waveform from the register 21, outputs a SET edge obtained by delaying the set time from the reference time Tref2 to the output buffer 23 according to the data, and the output buffer 23 is external. Output waveform to.

The RESET delay circuit 24 includes a register 25.
Input the timing data to reset the waveform from
The RESET edge obtained by delaying the set time from the reference time Tref2 according to the data is output to the output buffer 23, and the output buffer 23 outputs the waveform to the outside.

FIG. 7 is a timing chart of the calibration circuit 600. 7A is an 11th waveform, FIG. 7B is a 12th waveform, FIG. 7C is a 13th waveform, and FIG. 7D is a 14th waveform.

In the eleventh waveform, Te1 is TG6.
It is a set time from the reference time Tref2 set to 1 to the SET edge. In the 13th waveform, Te1 ′
Is the measurement time in the delay time measuring circuit 62 of the SET edge output at the set time of Te1, and is the delay time from the reference time Tref3 held by the delay time measuring circuit 62.

Similarly, in the twelfth waveform, Te2
From the reference time Tref2 set in TG61 to SE
This is the set time until the T edge. In the 14th waveform, Te2 ′ is the SET output at the set time of Te2.
It is the measurement time of the edge delay time measuring circuit 62, and is the delay time from the reference time Tref3 of the delay time measuring circuit 62. Comparing the change times of Te1 ′ and Te2 ′ with the change time when Te1 is changed to Te2, T
A time difference occurs due to the error of the delay circuit in G61.

In this way, the waveform output by the TG 61 is
Due to the influence of the error of the delay circuit, it is not possible to apply an accurate waveform to the DUT 200 for the set time of the TG 61.

Therefore, by correcting the set time in consideration of the error of the delay circuit of the TG61, the TG61 is set to the DUT.
A waveform can be output to 200 at a desired timing.
FIG. 8 is a graph showing the relationship between the set time and the measurement time. Set times Te1, Te2, Te from the reference time Tref2 to the SET edge or the RESET edge
3 ... With Ten as the horizontal axis, measurement times Te1 ′, Te from the reference time Tref3 to the SET edge or the RESET edge of the waveform output based on the set time
The vertical axis represents 2 ', Te3' ... Ten '. Thus, the error of the delay circuit of the TG 61 is calculated from the relationship between the set time and the measurement time, and the set time is corrected to correct the DUT2.
A desired test waveform is output to 00.

[0015]

However, in the conventional timing calibration method, it is necessary to newly provide the delay time measuring circuit 62 in the calibration circuit 600, which allows the calibration circuit 60 to be provided.
0 circuit scale and cost increase.

An object of the present invention is to perform timing calibration using a circuit built in an IC test apparatus.

[0017]

In order to solve the above problems, the calibration circuit according to claim 1 applies a waveform of a predetermined voltage to a DUT application line at a preset timing. 1) and a DC characteristic measuring unit (for example, the DC characteristic measuring circuit 17 in FIG. 1) for measuring the DC characteristic of the DUT connected to the DUT applying line, the applying unit is , First timing means for applying the waveform at the first timing (for example, SET delay circuit 22 in FIG. 6), and second timing means for applying the waveform at the second timing (for example, SET delay circuit 22 in FIG. 6). )
And a first input unit (for example, the timing generator 12 in FIG. 1) for inputting a first integrated value of the voltage of the DUT applied line measured by the DC characteristic measuring unit corresponding to the first timing, Second input means (for example, the timing generator 12 in FIG. 1) for inputting a second integrated value of the voltage of the DUT applied line measured by the DC characteristic measuring unit corresponding to the second timing; and the first timing. And a calibration means (for example, the timing generator 12 of FIG. 1) that calibrates the timing of applying the waveform based on the time difference between the second timing and the difference between the first integrated value and the second integrated value. It is characterized by having.

The IC test apparatus according to the third aspect is D
A DC characteristic measuring unit for measuring the DC characteristic of the DUT connected to the UT application line (for example, the DC characteristic measuring circuit 1 in FIG. 1).
7) and the DC characteristic measuring unit, and the calibration circuit according to claim 1 or 2 (for example, FIG. 1).
And the calibration circuit 100) of 1).

According to the invention described in claim 1, the correction time is obtained from the difference between the first integral value of the waveform applied at the first timing and the second integral value of the waveform applied at the second timing. By calibrating the timing of applying the waveform based on the correction time, the waveform at the desired timing can be applied accurately. Further, in general, since the DC characteristic measuring unit is provided in the IC test apparatus, the following advantages are obtained when the calibration circuit of the present invention is incorporated in the IC test apparatus. That is, for example, if the DC characteristic measuring unit included in the IC test apparatus is used as in the invention according to claim 3, there is no need to install a new circuit for performing the timing calibration, and the circuit scale is reduced. Also, it is possible to prevent an increase in cost.

A calibration circuit according to a second aspect of the present invention is a controller for setting timing (for example, CP of FIG. 1).
U11), an applying unit (for example, TG12 in FIG. 1) that applies a waveform to the DUT applying line according to the timing set by the control unit, and the DC characteristics of the DUT connected to the DUT applying line are measured. In a calibration circuit including a direct current characteristic measuring unit (for example, the direct current characteristic measuring circuit 17 in FIG. 1), the control unit sets a first timing timing by a first timing unit (for example, the CPU 11 in FIG. 1). And second timing means for setting the timing of the second timing (for example, C in FIG. 1).
PU11) and first input means (for example, C in FIG. 1) for inputting a first integrated value of the voltage of the DUT applied line measured by the DC characteristic measuring unit corresponding to the first timing.
PU11) and second input means (for example, C in FIG. 1) for inputting the second integrated value of the voltage of the DUT application line measured by the DC characteristic measuring unit corresponding to the second timing.
PU11), a calibration means for calibrating the content of the output timing based on the time difference between the first timing and the second timing and the difference between the first integrated value and the second integrated value (for example, FIG. 1). And a CPU 11) of the above.

According to the second aspect of the invention, the correction time is obtained from the difference between the first integral value of the waveform applied at the first timing and the second integral value of the waveform applied at the second timing, By calibrating the timing of applying the waveform based on the correction time, the waveform at the desired timing can be applied accurately. Further, if the DC characteristic measuring unit included in the IC test apparatus is used as in the third aspect of the invention, there is no need to install a new circuit for performing the timing calibration, and the circuit scale and cost increase. Can be prevented.

A timing calibration method according to a fourth aspect of the present invention is an applying section which applies a waveform of a predetermined voltage to a DUT applying line at a preset timing (for example, FIG. 1).
TG12) and D connected to the DUT application line
A timing calibration method in an IC test apparatus comprising: a DC characteristic measuring unit (for example, the DC characteristic measuring circuit 17 in FIG. 1) that measures the DC characteristic of the UT,
The first applying unit applies the waveform at a first timing.
Timing step (for example, step A3 in FIG. 4: CPU 11 in FIG. 1), and a first integration step in which the DC characteristic measuring unit integrates a waveform of a predetermined voltage corresponding to the first timing and outputs it as a first average potential. (For example, step A4 in FIG. 4: CPU 11 in FIG. 1) and a second timing step in which the applying section applies the waveform at the second timing (for example, step A5 in FIG. 4: CPU 1 in FIG. 1).
1) and a second integration step in which the direct current characteristic measuring unit integrates the waveform of the predetermined voltage corresponding to the second timing and outputs the second average potential (for example, step A in FIG. 4).
6: CPU 11) in FIG. 1, timing at which the applying unit applies the waveform based on a time difference between the first timing and the second timing and a potential difference between the first average potential and the second average potential. A calibration step for calibrating (for example, step A8 in FIG. 4; CPU 11 in FIG. 1).

According to the invention described in claim 4, the correction time is calculated from the difference between the first average potential of the waveform applied in the first timing step and the second average potential of the waveform applied in the second timing step. By obtaining and calibrating the timing of applying the waveform based on the correction time, the waveform of the desired timing can be accurately applied.

A timing calibration method according to a fifth aspect of the present invention is a control unit (for example, CPU 1 in FIG. 1) for setting timing including a first timing and a second timing.
1) and an application unit that applies a waveform to the DUT application line according to the timing set by the control unit (for example,
A timing calibration method in an IC test apparatus including the TG 12 of FIG. 1) and a DC characteristic measuring unit (for example, the DC characteristic measuring circuit 17 of FIG. 1) that measures the DC characteristic of the DUT connected to the DUT application line. And a first timing step in which the applying section applies the waveform at the first timing (for example, step A3 in FIG. 4: CPU 11 in FIG. 1) and a waveform of a predetermined voltage corresponding to the first timing. A first integration step (for example, step A4 in FIG. 4: CPU 11 in FIG. 1) in which the DC characteristic measuring unit integrates and outputs as a first average potential, and the applying unit applies the waveform at the second timing. Second
Timing step (for example, step A5 in FIG. 4: CPU 11 in FIG. 1) and a second integration step in which the DC characteristic measuring unit integrates the waveform of a predetermined voltage corresponding to the second timing and outputs the second average potential. (For example, step A6 in FIG. 4: CPU 11 in FIG. 1), the control unit based on the time difference between the first timing and the second timing and the potential difference between the first average potential and the second average potential. Calibration step for calibrating the timing at which is set (for example, step A8 in FIG. 4: CPU 11 in FIG. 1)
It is characterized by including and.

According to the fifth aspect of the invention, the correction time is calculated from the difference between the first average potential of the waveform applied in the first timing step and the second average potential of the waveform applied in the second timing step. Since the contents of the waveform output timing set based on the correction time can be calibrated, the waveform at the desired timing can be accurately output.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of a calibration circuit 100 of an IC test apparatus to which the present invention is applied. In FIG. 1, the calibration circuit 1
00 is a CPU (Central Processing Unit) 11, TG
12, a pass / fail judgment circuit 13, a driver 14, a comparator 15, a switch 16 and a DC characteristic measuring circuit 17. The output of the calibration circuit 100 is DUT2.
00 is connected.

Hereinafter, functional blocks different from those in FIG. 5 in the block configuration of the calibration circuit 100 according to the present embodiment will be described, the same functional blocks are designated by the same reference numerals, and detailed description thereof will be omitted.

The CPU 11 outputs a control signal for instructing the timing of outputting the waveform to the TG 12, inputs the output signal of the pass / fail judgment circuit 13, and details of the judgment are displayed on a display screen or the like although not shown in detail. Perform the processing to be displayed on. Further, the switching of the switch 16 is controlled, a signal is input from the DC characteristic measuring circuit 17, and the TG1 is input based on the signal.
It controls each circuit that constitutes the calibration circuit 100, such as outputting a control signal to the circuit 2.

The TG 12 is a circuit for outputting a waveform to the driver 14 according to the set timing. Its configuration is the same as the functional block shown in FIG. Register 2
Reference numeral 1/25 is a circuit for setting the delay time of the waveform output from the TG 12 in the SET delay circuit 22 or the RESET delay circuit 24 based on the setting data.

The switch 16 is a switch that is controlled by the CPU 11 and switches connection / disconnection according to the test mode and the waveform calibration mode of the DUT 200. CPU
11 disconnects the switch 16 when executing the test mode and connects the switch 16 when executing the calibration mode. Here, the test mode is a mode in which a test waveform is applied to the DUT 200 and the quality of the DUT 200 is determined based on the output waveform. The calibration mode is the DUT 20.
In this mode, the timing of the test waveform input to 0 is adjusted.

The DC characteristic measuring circuit 17 is a circuit for outputting an integrated waveform with respect to the input waveform. The circuit is
Instead of a circuit newly installed to apply the present invention,
A circuit installed in advance in the IC test device is used. FIG. 2 is a diagram showing an equivalent circuit of the DC characteristic measuring circuit 17. The DC characteristic measuring circuit 17 has an equivalent circuit of a resistor 3
1, is represented by a large integration circuit and the operational amplifier 33 of the time constant that consists in capacitor 32.

FIG. 3 is a timing chart of the calibration circuit 100 in the calibration mode. Figure 3
(A) shows two waveforms, a waveform set in the TG 12 (dotted line) and a waveform output from the TG 12 based on the set time (solid line). Hereinafter, these two waveforms are collectively referred to as the first waveform. Waveform. FIG. 3B shows the SE of the first waveform.
This waveform has a delayed T edge, and will be referred to as a second waveform hereinafter.

In the first waveform, Ts1 is TG12.
It is a set time from the reference time Tref1 set in step 1 to the SET edge, and is “zero” because it is the same time as the reference time Tref1. Ts1 ′ is the time from the reference time Tref1 of the output waveform from the TG 12 to the SET edge. Tr is RESE from the reference time Tref1
It is the set time until the T edge, and Tr ′ is the reference time Tref1 to RESET in the output waveform from the TG12.
It is the time to the edge. Further, Ts1 and Tr are set with the cycle of the waveform as T. The time difference between Ts1 and Ts1 ′ and the time difference between Tr and Tr ′ are caused by an error in the delay circuit in the TG 12.

Similarly, in the second waveform, Ts2 is
It is a set time from the reference time Tref1 to the SET edge. Ts2 ′ is the time from the reference time Tref1 to the SET edge in the output waveform from the TG12.
This time difference between Ts2 and Ts2 'is also caused by an error in the delay circuit in the TG 61. The RESET edge of the second waveform has the same timing as the RESET edge of the first waveform.

When the first waveform and the second waveform are input to the DC characteristic measuring circuit 17, the integrated waveform of each waveform is output. When the integrated waveform of the first waveform is Vs1 and the integrated waveform of the second waveform is Vs2, the waveforms of Vs1 and Vs2 are shown in FIG.
It shows in (c). The voltage values of Vs1 and Vs2 at this time are: Vs1 = (Tr'-Ts1 ') * (Vh-Vl) / T + Vl ... (1) Vs2 = (Tr'-Ts2') * (Vh-Vl) / T + Vl (2) Vh is a Hi level voltage value of the first waveform and the second waveform, and Vl is a Low level voltage value of the first waveform and the second waveform. Then, the change amount Td1 of the SET edge of the first waveform and the second waveform input to the DC characteristic measuring circuit 17 is calculated by using the change amounts of Vs1 and Vs2 obtained by the equations (1) and (2). It is calculated by the following formula. Td1 = Ts2′−Ts1 ′ = (Vs1−Vs2) × T / (Vh−Vl) (3)

Ts1 and Ts2 set in TG12
Change amount and Ts1 ′ and Ts2 ′ obtained by the equation (3)
The difference from the change amount (= Td1) is defined as the correction time. That is,
By setting the time obtained by adding the correction time to Ts2 to the TG12, the TG12 can set the Ts to the DUT200.
The SET edge can be accurately output with the amount of change in time from 1 to Ts2.

FIG. 4 is a flow chart showing the operation of the calibration circuit 100. This program is CP
It is stored in a memory or the like built in U11. Alternatively, a memory is independently installed in the calibration circuit 100, the program is stored in the memory, and the CPU
11 may execute by reading a program.

First, the CPU 11 determines whether the calibration circuit 100 executes the test mode or the calibration mode (step A1). When it is determined to execute the calibration mode (step A1: calibration), C
The PU 11 connects the switch 16 (step A2), and T
An instruction signal for outputting the first waveform is output to G12 (step A3). As a result, the TG 12 outputs a waveform according to the set time. The waveform output from TG12 is
It is input to the DC characteristic measuring circuit 17 via the driver 14. The CPU 11 inputs the integrated waveform output from the DC characteristic measuring circuit 17, and obtains Vs1 using the equation (1) (step A4).

Next, the CPU 11 outputs the second value to the TG 12.
Output an instruction signal to output the waveform of (Step A
6). As a result, the TG 12 outputs a waveform according to the set time. Then, the CPU 11 controls the DC characteristic measuring circuit 17
The output waveform is input and Vs2 is calculated using the equation (2) (step A6).

Next, the CPU 11 uses the equation (3) to calculate Td.
1 is calculated (step A7), and the timing of the output waveform is calibrated using the calculated Td1 as a correction time (step A7).
8). Then, the CPU 11 determines whether or not to end the process (step A9), and when the process is to be ended (step A9:
Yes) The process ends. If not completed (step A9: No), the process proceeds to step A1.

When it is determined in step A1 that the test mode is to be executed (step A1: test), C
The PU 11 disconnects the switch 16 (step A10),
Perform a test on the DUT 200 (step A1)
1). At this time, the CPU 11 outputs the setting data to the TG 12 based on the correction time, and outputs the waveform at the corrected timing from the TG 12. When the DUT 200 test is completed, the CPU 11 advances the process to step 9.

As described above, the TG 12 outputs the first waveform and the second waveform, and the DC characteristic measuring circuit 17 outputs the second waveform.
The integrated waveform of two waveforms is obtained, and the time difference between the first waveform and the second waveform is obtained from the potential difference. The potential difference and TG1
The TG 12 is set by obtaining the difference between the time difference between the set times of the first waveform and the second waveform set to 2, and correcting the difference with respect to the set time based on the correction time. The waveform can be output accurately.

Although the present embodiment has explained the timing calibration of the SET edge using two waveforms with the RESET edge having the same timing, if the timing calibration is performed with the SET edge having the same timing, the RESET edge will be described. Can be corrected.

The DC characteristic measuring circuit 17 is essentially
This is a circuit for measuring the DC characteristics of the DUT 200 by the C test device, and is a circuit that is provided as standard, so that it is possible to prevent an increase in circuit scale and cost.

[0045]

According to the first and second aspects of the invention, the difference between the first integral value of the waveform applied at the first timing and the second integral value of the waveform applied at the second timing is set to the first value. The correction time is obtained by comparing the difference between the set value of the timing and the set value of the second timing, and the timing of applying the waveform is calibrated based on the correction time, so that the waveform of the desired timing is accurately applied. be able to.
Further, if the DC characteristic measuring unit included in the IC test apparatus is used as in the third aspect of the invention, there is no need to install a new circuit for performing the timing calibration, and the circuit scale and cost increase. Can be prevented.

According to the invention described in claim 4, the difference between the first average potential of the waveform applied in the first timing step and the second average potential of the waveform applied in the second timing step is calculated as the first timing step. The correction time is obtained by comparing the setting value of the waveform of the waveform with the setting value of the waveform of the second timing step, and the waveform of the desired timing is obtained by calibrating the timing of applying the waveform based on the correction time. It can be applied accurately.

According to the fifth aspect of the invention, the difference between the first average potential of the waveform applied in the first timing step and the second average potential of the waveform applied in the second timing step is calculated as the first timing step. Since the correction time is obtained by comparing the difference between the set value of the waveform and the set value of the waveform of the second timing step and the content of the timing of the waveform output set based on the corrected time can be calibrated, The timing waveform can be output accurately.

[Brief description of drawings]

FIG. 1 is a block diagram of an IC test apparatus.

FIG. 2 is an equivalent circuit of a DC characteristic measuring circuit.

FIG. 3 is a timing chart of the IC test apparatus in the calibration mode.

FIG. 4 is a flowchart showing the operation of the IC test apparatus.

FIG. 5 is a block diagram of a conventional IC test apparatus.

FIG. 6 is a block diagram of a conventional TG.

FIG. 7 is a timing chart of a conventional IC test device.

FIG. 8 is a graph showing the relationship between set time and measurement time.

[Explanation of symbols]

100 calibration circuit 11 CPU 12 TG 13 Pass / fail judgment circuit 14 drivers 15 Comparator 16 switch 17 DC characteristics measurement circuit 200 DUT

Claims (5)

[Claims] 1. A calibration comprising: an applying unit for applying a waveform of a predetermined voltage to a DUT applying line at a preset timing; and a DC characteristic measuring unit for measuring a DC characteristic of a DUT connected to the DUT applying line. In the application circuit, the applying section includes first timing means for applying the waveform at a first timing, second timing means for applying the waveform at a second timing, and the DC characteristic corresponding to the first timing. A first input means for inputting a first integral value of the voltage of the DUT applied line measured by a measuring unit; and a voltage of the DUT applied line measured by the DC characteristic measuring unit corresponding to the second timing. Second input means for inputting a second integrated value; a time difference between the first timing and the second timing; and the first integrated value and the second integrated value Based on the difference,
A calibration circuit configured to calibrate the timing of applying the waveform; 2. A control unit for setting timing, an applying unit for applying a waveform to a DUT applying line according to the timing set by the controlling unit, and a DC characteristic of the DUT connected to the DUT applying line. In the calibration circuit including a direct current characteristic measuring unit, the control unit includes a first timing unit that sets a timing of a first timing, a second timing unit that sets a timing of a second timing, and the first timing unit. First input means for inputting a first integrated value of the voltage of the DUT applied line measured by the DC characteristic measuring unit corresponding to timing, and the DC characteristic measuring unit measuring corresponding to the second timing. , Second input means for inputting a second integrated value of the voltage of the DUT application line, at the time of the first timing and the second timing Difference, and, based on the difference between the second integral value from the first integral value,
A calibration circuit comprising: a calibration unit that calibrates the content of the output timing. 3. The direct current characteristic measuring section for measuring the direct current characteristic of the DUT connected to the DUT application line, and the direct current characteristic measuring section.
An IC test apparatus comprising: the calibration circuit described above. 4. An applying section for applying a waveform of a predetermined voltage to a DUT applying line at a preset timing, and the DUT.
A timing calibration method in an IC test apparatus, comprising: a DC characteristic measuring unit that measures a DC characteristic of a DUT connected to an application line, wherein the applying unit applies the waveform at a first timing.
A timing step; a first integration step in which the DC characteristic measuring unit integrates a waveform of a predetermined voltage corresponding to the first timing and outputs the waveform as a first average potential; and the applying unit applies the waveform at a second timing. Second
A timing step, a second integration step in which the direct current characteristic measuring unit integrates a waveform of a predetermined voltage corresponding to the second timing and outputs the second average potential, a time difference between the first timing and the second timing, And a calibration step of calibrating the timing at which the applying unit applies the waveform based on the potential difference between the first average potential and the second average potential. 5. A control unit for setting a timing including a first timing and a second timing, an applying unit for applying a waveform to a DUT applying line according to the timing set by the controlling unit, and the DUT applying line. D connected
A timing calibration method in an IC test apparatus, comprising: a DC characteristic measuring unit that measures a DC characteristic of a UT; a first timing step in which the applying unit applies the waveform at the first timing; A first integration step in which the direct current characteristic measuring unit integrates a waveform of a predetermined voltage corresponding to a timing and outputs the waveform as a first average potential; and a second timing step in which the applying unit applies the waveform at the second timing. A second integration step in which the direct current characteristic measuring unit integrates a waveform of a predetermined voltage corresponding to the second timing and outputs a second average potential; a time difference between the first timing and the second timing; Based on the potential difference between the first average potential and the second average potential, the controller calibrates the contents of the set timing. Timing calibration method which comprises the steps, a.