JP2012068091A - Testing device and method for adjusting the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately adjust a testing device.SOLUTION: A testing device for testing a device to be tested comprises a supply part for supplying a test signal to the device to be tested, a measuring part for measuring a DC voltage of the signal output from the supply part and a first calculation part for calculating the output time difference, which is the time difference between the output time of the supply part in the case of outputting a rising edge and the output time of the supply part in the case of outputting a falling edge based on the periodic signal voltage measured by the measuring part when a predetermined periodic signal is output from the supply part.

Description

  The present invention relates to a test apparatus and an adjustment method.

  The test apparatus acquires the value of the signal output from the device under test at a predetermined timing. Then, the test apparatus compares the acquired value with the expected value and determines pass / fail of the device under test based on the comparison result.

  Here, the test apparatus converts the signal output from the device under test into a logical value by a comparator, and acquires the logical value of the signal value at the timing of the strobe signal. However, the comparator has a difference between the rising response and the falling response. Therefore, prior to the test, the test apparatus must correct the difference between the rising response and the falling response of the comparator by adjusting the logical value acquisition timing.

  For example, Patent Document 1 describes a technique in which the output timing of a driver is adjusted in advance so that the timing of a rising edge and the timing of a falling edge of a signal output from a driver in a test apparatus are matched. . In Patent Document 1, the signal output from the adjusted driver is directly supplied to the comparator so that the rising edge acquisition timing and the falling edge acquisition timing of the signal logically converted by the comparator are matched. A technique for adjusting the acquisition timing of a logical value is described.

  Patent Document 1 International Publication No. 2010/086971

  By the way, an inexpensive test apparatus does not include a mechanism for adjusting the output timing of the driver. Therefore, such a test apparatus cannot accurately match the rising edge acquisition timing and the falling edge acquisition timing of the signal logically converted by the comparator. Therefore, it has been difficult for such a test apparatus to test accurately.

  In order to solve the above-described problem, in a first aspect of the present invention, a test apparatus for testing a device under test, the supply unit supplying a test signal to the device under test, and the output from the supply unit A measurement unit that measures a DC voltage of a signal to be output, and the supply in the case of outputting a rising edge based on a periodic signal voltage measured by the measurement unit when a predetermined periodic signal is output from the supply unit There is provided a test apparatus and an adjustment method including a first calculation unit that calculates an output time difference that is a time difference between an output time of the unit and an output time of the supply unit when a falling edge is output.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

1 shows a configuration of a test apparatus 10 according to the present embodiment. An example of the structure of the supply part 16 which concerns on this embodiment is shown. An example of a structure of the acquisition part 18 which concerns on this embodiment is shown. An example of a structure of the measurement part 22 which concerns on this embodiment is shown. 2 shows a processing flow in calibration of the test apparatus 10 according to the present embodiment. An example of the waveform of the signal including the rising edge output from the driver 58 of the acquisition unit 18 according to the present embodiment and the waveform of the signal including the falling edge output from the driver 58 is shown. The waveform of the signal including the rising edge input to the H-side comparator 62 of the supply unit 16 according to the present embodiment, the waveform of the signal output from the H-side comparator 62, and the input to the L-side comparator 64 of the supply unit 16. An example of a waveform of a signal including a falling edge and a waveform of a signal output from the H-side flip-flop 66 are shown. The detailed processing flow of the calibration part 34 in FIG.5 S11 is shown. The connection state of the 1st relay 24 and the 2nd relay 26 in FIG.8 S21 is shown. An example of the waveform of an ideal periodic signal to be output in step S24 of FIG. 8 is shown. An example of the waveform of the actual periodic signal output in step S24 of FIG. 8 is shown. An example of the table which registered each of a plurality of difference voltages and the corresponding output time difference beforehand is shown. The detailed process flow of the calibration part 34 in FIG.5 S12 is shown. The connection state of the 1st relay 24 and the 2nd relay 26 in FIG.8 S31 is shown. An example of the adjustment process by the adjustment part 42 in step S13 of FIG. 5 is shown.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 shows a configuration of a test apparatus 10 according to the present embodiment. The test apparatus 10 tests a device under test (DUT) such as a semiconductor device.

  The test apparatus 10 includes a pattern generation unit 12, a timing generation unit 14, a supply unit 16, an acquisition unit 18, a determination unit 20, a measurement unit 22, a first relay 24, a second relay 26, and a control. Device 30.

  The pattern generator 12 outputs a test pattern that specifies the waveform of the test signal and an expected value pattern of the response signal to be output from the device under test. The timing generator 14 outputs a timing signal indicating the edge timing of the test signal and a strobe signal indicating the acquisition timing of the value of the response signal.

  The supply unit 16 receives the timing signal and the test pattern, generates a test signal having a waveform specified by the test pattern, and supplies the generated test signal to the device under test via the pin 28. The acquisition unit 18 receives the response signal output from the device under test via the pin 28, and acquires the value of the received response signal at the timing of the strobe signal. The signal output end of the supply unit 16 and the signal input end of the acquisition unit 18 are connected by a signal line. The determination unit 20 determines whether or not the value of the response signal acquired by the acquisition unit 18 matches the expected value generated from the pattern generation unit 12.

  The measurement unit 22 measures the DC voltage of the signal output from the supply unit 16. The first relay 24 connects or disconnects between the pin 28 connected to the device under test and the signal output terminal of the supply unit 16. More specifically, the signal line connecting the supply unit 16 and the acquisition unit 18 and the pin 28 are connected or disconnected. The second relay 26 connects or disconnects the signal output terminal of the supply unit 16 and the measurement unit 22. More specifically, the second relay 26 connects or disconnects the signal line connecting the pin 28 and the first relay 24 and the measurement unit 22.

  The control device 30 controls the entire test apparatus 10. The control device 30 is realized by a computer. The control device 30 includes a test control unit 32 and a calibration unit 34.

  The test control unit 32 controls each unit of the test apparatus 10 during the test. The test control unit 32 is a functional block realized by a computer executing a test program.

  The calibration unit 34 performs calibration of the test apparatus 10 prior to the test. The calibration unit 34 is realized by a computer executing a calibration program.

  The calibration unit 34 includes a calibration control unit 36, a first calculation unit 38, a second calculation unit 40, and an adjustment unit 42. Each of the calibration control unit 36, the first calculation unit 38, the second calculation unit 40, and the adjustment unit 42 is a functional block realized by the computer executing a calibration program.

  The calibration control unit 36 controls each unit of the test apparatus 10 during calibration. The first calculation unit 38 calculates an output time difference that is a time difference between the output time of the supply unit 16 when the rising edge is output and the output time of the supply unit 16 when the falling edge is output.

  The second calculation unit 40 calculates an acquisition time difference that is a time difference between the acquisition time of the acquisition unit 18 when acquiring the rising edge and the acquisition time of the acquisition unit 18 when acquiring the falling edge. The adjustment unit 42 adjusts the acquisition unit 18 based on the acquisition time difference calculated by the second calculation unit 40 so as to match the acquisition time when acquiring the rising edge and the acquisition time when acquiring the falling edge. .

  Such a test apparatus 10 supplies a test signal to a device under test during a test. Then, the test apparatus 10 acquires the value of the response signal output from the device under test in response to the test signal being supplied during the test, and compares the acquired value of the response signal with the expected value. Judge the quality of the device under test. Thereby, the test apparatus 10 can test the device under test.

  Further, the test apparatus 10 performs calibration prior to the test. In the calibration, the test apparatus 10 eliminates a deviation between the acquisition time of the acquisition unit 18 when acquiring a signal including a rising edge and the acquisition time of the acquisition unit 18 when acquiring a signal including a falling edge. In addition, the signal acquisition timing in the acquisition unit 18 is adjusted. Thereby, the test apparatus 10 can acquire the value of the response signal output from the test apparatus 10 with high accuracy.

  FIG. 2 shows an example of the configuration of the supply unit 16 according to the present embodiment. The supply unit 16 according to this example includes a rising delay unit 52, a falling delay unit 54, an SR flip-flop 56, and a driver 58.

  The rising delay unit 52 receives from the pattern generation unit 12 a rising pattern that specifies the timing of the rising edge of the test signal. More specifically, the rising delay unit 52 receives from the pattern generation unit 12 a rising pattern that specifies a delay amount from the reference timing to the rising edge. The rising delay unit 52 also receives a pulse wave timing signal indicating the reference timing from the timing generation unit 14. Then, the rising delay unit 52 delays the rising timing signal by the time specified by the rising pattern. Accordingly, the rising delay unit 52 can output a pulse wave timing signal at the rising edge timing specified by the test pattern.

  The falling delay unit 54 receives from the pattern generation unit 12 a falling pattern that specifies the timing of the falling edge of the test signal. More specifically, the falling delay unit 54 receives from the pattern generation unit 12 a falling pattern that specifies a delay amount from the reference timing to the falling edge. Further, the falling delay unit 54 receives a timing signal of a pulse wave indicating the reference timing from the timing generation unit 14. Then, the falling delay unit 54 delays the falling timing signal by the time specified by the falling pattern. As a result, the falling delay unit 54 can output a pulse wave timing signal at the falling edge timing specified by the test pattern.

  The SR flip-flop 56 inputs the timing signal output from the rising delay unit 52 to the set terminal, and inputs the timing signal output from the falling delay unit 54 to the reset terminal. Accordingly, the SR flip-flop 56 can output a test signal that rises at the timing of the timing signal output from the rising delay unit 52 and falls at the timing of the timing signal output from the falling delay unit 54.

  The driver 58 supplies the test signal output from the SR flip-flop 56 to the device under test (DUT). Such a supply unit 16 can supply a test signal having a waveform specified by the test pattern to the device under test at a timing specified by the test pattern.

  FIG. 3 shows an example of the configuration of the acquisition unit 18 according to the present embodiment. The acquisition unit 18 according to this example includes an H-side comparator 62, an L-side comparator 64, an H-side flip-flop 66, an L-side flip-flop 68, a logic comparison unit 70, an H-side minute delay element 72, Side minute delay element 74.

The H-side comparator 62 receives the response signal output from the device under test, and outputs a logic signal indicating whether or not the level of the response signal is the H logic level. H-side comparator 62, as an example, and compares the set level of the response signal H side threshold level V _OH. For example, the H-side comparator 62 becomes L logic when the level of the response signal is larger than the set H-side threshold level V _OH, and when the response signal level is not higher than the H-side threshold level V _OH. Outputs a logic signal of H logic.

The L-side comparator 64 receives the response signal output from the device under test, and outputs a logic signal indicating whether or not the level of the response signal is the L logic level. L-side comparator 64, as an example, and compares the set level of the response signal L side threshold level V _OL. Then, L-side comparator 64, as an example, the level of the response signal becomes the L logic when the L-side threshold level V _OL smaller, when the level of the response signal is not smaller than the L side threshold level V _OL is H logic Is output as a logic signal.

  The H-side flip-flop 66 receives from the timing generator 14 an H logic strobe signal that indicates the timing at which the H logic value of the response signal is fetched. The H-side flip-flop 66 takes in the value of the logic signal output from the H-side comparator 62 at the timing of the strobe signal for H logic and stores it inside. As a result, the H-side flip-flop 66 can capture a value indicating whether or not the response signal is H logic at the timing designated by the timing generator 14.

  The L-side flip-flop 68 receives from the timing generator 14 an L logic strobe signal that indicates the timing at which the L logic value of the response signal is captured. The L-side flip-flop 68 takes in the value of the logic signal output from the H-side comparator 62 at the timing of the L logic strobe signal and stores it inside. As a result, the L-side flip-flop 68 can capture a value indicating whether or not the response signal is L logic at the timing specified by the timing generator 14.

  The logic comparison unit 70 determines the value of the response signal based on the values fetched by the H side flip-flop 66 and the L side flip-flop 68. As an example, the logic comparison unit 70 determines whether the value of the response signal is H logic, L logic, or an indeterminate value. Then, the logic comparison unit 70 outputs the determination result to the determination unit 20 as a response signal value.

  The H-side minute delay element 72 is provided in a path for propagating the H logic strobe signal output from the timing generation unit 14 to the H-side flip-flop 66. The H-side minute delay element 72 delays the H logic strobe signal applied to the H-side flip-flop 66 by a preset delay amount. The delay amount of the H-side minute delay element 72 is adjusted by the adjustment unit 42 in calibration.

  The L-side minute delay element 74 is provided in a path for propagating the L logic strobe signal output from the timing generation unit 14 to the L-side flip-flop 68. The L-side minute delay element 74 delays the L logic strobe signal applied to the L-side flip-flop 68 by a preset delay amount. The delay amount of the L-side minute delay element 74 is adjusted by the adjustment unit 42 in calibration.

  Such an acquisition unit 18 can acquire the logical value of the response signal output from the device under test at the timing specified by the adjustment unit 42. Furthermore, the acquisition unit 18 can separately adjust the timing for acquiring the H logic of the response signal and the timing for acquiring the L logic of the response signal.

  FIG. 4 shows an example of the configuration of the measurement unit 22 according to the present embodiment. The measurement unit 22 according to this example includes a filter unit 82 and an AD conversion unit 84.

  The filter unit 82 performs low-pass filtering on the signal output from the supply unit 16. Thereby, the filter part 82 can output the direct-current component showing the average value of a periodic signal, when the periodic signal is output from the supply part 16. FIG.

  The AD conversion unit 84 AD converts the signal filtered by the filter unit 82. As a result, when the periodic signal is output from the supply unit 16, the AD conversion unit 84 can output a digital value representing a DC component of the periodic signal as a measurement result.

  FIG. 5 shows a processing flow of the calibration unit 34 according to the present embodiment. FIG. 6 shows an example of a waveform of a signal including a rising edge output from the driver 58 of the acquisition unit 18 according to the present embodiment and a waveform of a signal including a falling edge output from the driver 58. 7 shows the waveform of a signal including a rising edge input to the H-side comparator 62 of the supply unit 16 and the waveform of the signal output from the H-side comparator 62 according to the present embodiment, and the L-side comparator of the supply unit 16. An example of a waveform of a signal including a falling edge input to 64 and a waveform of a signal output from the H-side flip-flop 66 are shown.

The calibration unit 34 executes the processing from step S11 to step S13. First, in step S11, the calibration unit 34 measures an output time difference that is a time difference between an output time of the supply unit 16 when outputting a rising edge and an output time of the supply unit 16 when outputting a falling edge. . More specifically, the output time difference is, as shown in FIG. 6, a rising edge of a signal actually output from the supply unit 16 when a signal having a waveform rising at a predetermined timing is output. The time difference between the time (t ₁ ) and the time (t ₂ ) of the falling edge of the signal actually output from the supply unit 16 when a signal having a waveform falling at the same timing is output. Here, the same timing means, for example, that the delay time from the reference time in the test cycle is the same.

Subsequently, in step S12, the calibration unit 34 calculates an acquisition time difference that is a time difference between the acquisition time of the acquisition unit 18 when acquiring the rising edge and the acquisition time of the acquisition unit 18 when acquiring the falling edge. . More specifically, as shown in FIG. 7, the acquisition time difference is a time (t ₃ ) at which the value acquired by the acquisition unit 18 changes when a signal having a waveform rising at a predetermined timing is input. And the time difference from the time (t ₄ ) when the value acquired by the acquisition unit 18 changes when a signal having a waveform falling at the same timing is input.

  Subsequently, in step S <b> 13, the calibration unit 34 adjusts the acquisition unit 18 based on the acquisition time difference so that the acquisition time when the rising edge is acquired matches the acquisition time when the falling edge is acquired. As an example, the calibration unit 34 calculates the delay amount of the H-side minute delay element 72 that delays the H logic strobe signal and the delay amount of the L-side minute delay element 74 that delays the L logic strobe signal shown in FIG. By adjusting, the acquisition time when acquiring the rising edge and the acquisition time when acquiring the falling edge are matched.

  FIG. 8 shows a detailed processing flow of the calibration unit 34 in step S11 of FIG. FIG. 9 shows the connection state of the first relay 24 and the second relay 26 in step S21 of FIG. FIG. 10 shows an example of an ideal periodic signal waveform to be output in step S24 of FIG. FIG. 11 shows an example of the waveform of the actual periodic signal output in step S24 of FIG. FIG. 12 shows an example of a table in which a plurality of differential voltages and corresponding output time differences are registered in advance.

  In step S11, the calibration unit 34 executes processing from step S21 to step S25. First, in step S21, the calibration unit 34 places the first relay 24 and the second relay 26 in a connected state as shown in FIG. Accordingly, the calibration unit 34 can cause the measurement unit 22 to measure the voltage of the signal output from the supply unit 16.

  Subsequently, in step S <b> 22, the calibration unit 34 causes the supply unit 16 to output an H logic signal and causes the measurement unit 22 to measure the H logic voltage output from the supply unit 16. Subsequently, in step S23, the calibration unit 34 causes the supply unit 16 to output an L logic signal, and causes the measurement unit 22 to measure the L logic voltage output from the supply unit 16.

  Subsequently, in step S24, the calibration unit 34 causes the supply unit 16 to output a predetermined periodic signal, and causes the measurement unit 22 to output a periodic signal voltage that is a DC component of the periodic signal output from the supply unit 16. Let me measure. More specifically, the calibration unit 34 causes the measurement unit 22 to measure the periodic signal voltage by outputting a periodic signal that alternately repeats the H logic and the L logic with a predetermined frequency and duty ratio. As an example, the calibration unit 34 outputs a periodic signal having a duty ratio of 50%.

  Subsequently, in step S25, the first calculation unit 38 of the calibration unit 34 outputs the H logic voltage measured by the measurement unit 22 when the supply unit 16 outputs an H logic signal, and the supply unit 16 outputs the L logic. Based on the L logic voltage measured by the measurement unit 22 when the signal is output and the periodic signal voltage measured by the measurement unit 22 when the predetermined periodic signal is output from the supply unit 16, Calculate the output time difference.

  Here, for example, when the supply unit 16 outputs an ideal periodic signal having the same rise time and fall time as shown in FIG. 10, for example, the periodic signal voltage measured by the measurement unit 22 is The voltage is determined by the amplitude of the signal and the duty ratio of the periodic signal. That is, when the supply unit 16 outputs an ideal periodic signal, the periodic signal voltage measured by the measuring unit 22 is a voltage having a potential obtained by dividing the amplitude of the periodic signal by the duty ratio of the periodic signal. For example, if the supply unit 16 outputs a periodic signal with a duty ratio of 50%, the periodic signal voltage measured by the measuring unit 22 is the midpoint of the amplitude of the periodic signal, that is, the H logic voltage and the L logic voltage. And an intermediate voltage. As described above, the periodic signal voltage measured by the measurement unit 22 when the supply unit 16 outputs an ideal periodic signal is referred to herein as a reference voltage.

  However, the periodic signal actually output by the supply unit 16 has a rise time and a fall time that are different from each other as shown in FIG. When the rise time and the fall time are different, the periodic signal voltage measured by the measurement unit 22 deviates from the reference voltage. In this case, the difference voltage between the reference voltage and the periodic signal voltage increases or decreases as the output time difference increases, for example.

  Therefore, in step S25, the first calculator 38 calculates a reference voltage from the H logic voltage, the L logic voltage, and the duty ratio of the periodic signal. For example, when outputting a periodic signal with a duty ratio of 50%, the first calculation unit 38 calculates a midpoint voltage between the H logic voltage and the L logic voltage as a reference voltage. Subsequently, the first calculator 38 calculates a differential voltage between the periodic signal voltage measured in step S24 and the reference voltage.

  Then, the first calculation unit 38 calculates an output time difference from the calculated difference voltage. In this case, as an example, the first calculation unit 38 refers to a table in which each of the plurality of difference voltages and the corresponding output time difference are registered in advance as illustrated in FIG. 12, and calculates the output time difference from the difference voltage. . In the table, for example, the relationship between the difference voltage obtained as a result of measuring the sample supply unit 16 and the output time difference is registered. Thereby, the 1st calculation part 38 can calculate an output time difference correctly from a difference voltage.

  Further, as an example, the first calculating unit 38 calculates an output time difference from the difference voltage with reference to a predetermined straight line connecting a preset differential voltage between two points and a corresponding output time difference. Also good. Thereby, the 1st calculation part 38 can calculate an output time difference from a difference voltage, without using a table etc.

  The calibration unit 34 performs the processing from step S21 to step S25 as described above, so that the output time of the supply unit 16 when outputting the rising edge and the output of the supply unit 16 when outputting the falling edge are output. An output time difference that is a time difference from time can be measured.

  FIG. 13 shows a detailed processing flow of the calibration unit 34 in step S12 of FIG. FIG. 14 shows the connection state of the first relay 24 and the second relay 26 in step S31 of FIG.

  In step S12, the calibration unit 34 executes processing from step S31 to step S34. First, in step S31, the calibration unit 34 causes the first relay 24 and the second relay 26 to be disconnected as shown in FIG. As a result, the calibration unit 34 can give the signal output from the supply unit 16 to the acquisition unit 18 without outputting the signal to the outside.

  Subsequently, in step S <b> 32, the calibration unit 34 outputs a signal that rises at a predetermined timing from the supply unit 16 and gives the signal to the acquisition unit 18 to measure the timing of the rising edge of the signal input to the acquisition unit 18. . Subsequently, in step S <b> 33, the calibration unit 34 outputs a signal that falls at the same timing as the signal rises in step S <b> 32 from the supply unit 16 to the acquisition unit 18 and inputs the signal to the acquisition unit 18. The timing of the falling edge of the signal is measured.

  Subsequently, in step S34, the second calculation unit 40 of the calibration unit 34 calculates the time difference between the acquisition time of the acquisition unit 18 when acquiring the rising edge and the acquisition time of the acquisition unit 18 when acquiring the falling edge. A certain acquisition time difference is calculated. In this case, the second calculation unit 40 causes the supply unit 16 measured in step S32 to output a signal rising at a predetermined timing to obtain the rising edge timing acquired by the acquisition unit 18, and the supply measured in step S33. The acquisition time difference is calculated based on the falling edge timing acquired by the acquisition unit 18 by causing the unit 16 to output a signal falling at a predetermined timing and the output time difference measured in step S11.

  More specifically, the second calculation unit 40 calculates the time difference between the rising edge timing measured in step S32 and the falling edge timing measured in step S33. Then, the second calculation unit 40 further subtracts the output time difference calculated in step S11 from the time difference between the rising edge timing and the falling edge timing to calculate the acquisition time difference.

  Thereby, as a result of the output time difference being included in the supply unit 16, the second calculation unit 40 has a time difference between the rising edge and the falling edge of the signal input to the acquisition unit 18. The acquisition time difference of the acquisition unit 18 can be calculated with high accuracy.

  FIG. 15 shows an example of adjustment processing by the adjustment unit 42 in step S13 of FIG. Based on the acquisition time difference calculated in step S12, the adjustment unit 42 causes the acquisition unit 18 to match the acquisition time when the acquisition unit 18 acquires the rising edge and the acquisition time when the falling edge is acquired. adjust.

  As an example, the adjustment unit 42 compares the relative time difference between the H logic strobe signal indicating the timing for capturing the H logic value of the response signal and the L logic strobe signal indicating the timing for capturing the L logic value of the response signal. Is shifted by the acquisition time difference calculated in step S12. For example, the adjustment unit 42 adjusts the delay amount of at least one of the H-side micro delay element 72 and the L-side micro delay element 74 shown in FIG. The relative time difference is shifted by the acquisition time difference.

  Thereby, the adjustment unit 42 can match the time difference between the acquisition time when the acquisition unit 18 acquires the rising edge of the response signal and the acquisition time when the falling edge is acquired. As described above, according to the test apparatus 10, even in the case where an adjustment mechanism that matches the timing of the rising edge and the timing of the falling edge of the signal output from the supply unit 16 is not provided, The rising edge acquisition timing and the falling edge acquisition timing can be matched with high accuracy. Thereby, the test apparatus 10 can test the device under test with high accuracy.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

DESCRIPTION OF SYMBOLS 10 Test apparatus, 12 pattern generation part, 14 timing generation part, 16 supply part, 18 acquisition part, 20 determination part, 22 measurement part, 24 1st relay, 26 2nd relay, 28 pins, 30 control apparatus, 32 test control Unit, 34 calibration unit, 36 calibration control unit, 38 first calculation unit, 40 second calculation unit, 42 adjustment unit, 52 rising delay unit, 54 falling delay unit, 56 SR flip-flop, 58 driver, 62 H Side comparator, 64 L side comparator, 66 H side flip flop, 68 L side flip flop, 70 logic comparison unit, 72 H side minute delay element, 74 L side minute delay element, 82 filter unit, 84 AD conversion unit

Claims (9)

A test apparatus for testing a device under test,
A supply for supplying a test signal to the device under test;
A measurement unit for measuring a DC voltage of a signal output from the supply unit;
When outputting the output time and falling edge of the supply unit when outputting a rising edge based on the periodic signal voltage measured by the measurement unit when a predetermined periodic signal is output from the supply unit A first calculation unit that calculates an output time difference that is a time difference from the output time of the supply unit;
A test apparatus comprising: The first calculation unit causes the measurement unit to output an H logic voltage measured by the measurement unit when an H logic signal is output from the supply unit, and an L logic signal output from the supply unit. The test apparatus according to claim 1, wherein the output time difference is calculated based on a measured L logic voltage and the periodic signal voltage. The test according to claim 1 or 2, wherein the first calculation unit calculates the output time difference based on a difference voltage between a reference voltage of a potential obtained by dividing the amplitude of the periodic signal according to a duty ratio and the periodic signal voltage. apparatus. An acquisition unit for acquiring a response signal output from the device under test;
Acquired by the acquisition unit by outputting a signal that rises at a predetermined timing to the supply unit and outputting a rising edge timing acquired by the acquisition unit and a signal falling at a predetermined timing by the supply unit The acquisition time difference is a time difference between the acquisition time of the acquisition unit when acquiring the rising edge and the acquisition time of the acquisition unit when acquiring the falling edge based on the timing of the falling edge and the output time difference A second calculation unit for calculating
The test apparatus according to claim 1, further comprising: The test apparatus according to claim 4, further comprising: an adjustment unit that adjusts the acquisition unit based on the acquisition time difference so that the acquisition time when acquiring the rising edge and the acquisition time when acquiring the falling edge are matched. . The test apparatus according to claim 3, wherein the first calculation unit calculates the output time difference from the difference voltage with reference to a table in which the output time difference corresponding to each of the plurality of difference voltages is registered in advance. The test apparatus according to claim 3, wherein the first calculation unit calculates the output time difference from the difference voltage with reference to a straight line connecting a representative difference voltage between the two points and a corresponding output time difference. The measuring unit is
A filter unit for low-pass filtering the signal output from the supply unit;
An AD converter that AD converts the signal filtered by the filter;
The test apparatus according to claim 1, comprising: An adjustment method in a test apparatus for testing a device under test,
The test apparatus comprises:
A supply for supplying a test signal to the device under test;
An acquisition unit for acquiring a response signal output from the device under test;
A measurement unit for measuring a DC voltage of a signal output from the supply unit;
With
When outputting the output time and falling edge of the supply unit when outputting a rising edge based on the periodic signal voltage measured by the measurement unit when a predetermined periodic signal is output from the supply unit Calculating an output time difference which is a time difference from the output time of the supply unit of
Acquired by the acquisition unit by outputting a signal that rises at a predetermined timing to the supply unit and outputting a rising edge timing acquired by the acquisition unit and a signal falling at a predetermined timing by the supply unit The acquisition time difference is a time difference between the acquisition time of the acquisition unit when acquiring the rising edge and the acquisition time of the acquisition unit when acquiring the falling edge based on the timing of the falling edge and the output time difference To calculate
An adjustment method for adjusting the acquisition unit based on the acquisition time difference so that the acquisition time for acquiring a rising edge and the acquisition time for acquiring a falling edge are matched.

Images