JP2003179204A - Power module with cooling mechanism and method of cooling the same - Google Patents

Power module with cooling mechanism and method of cooling the same

Info

Publication number
JP2003179204A
JP2003179204A JP2001379231A JP2001379231A JP2003179204A JP 2003179204 A JP2003179204 A JP 2003179204A JP 2001379231 A JP2001379231 A JP 2001379231A JP 2001379231 A JP2001379231 A JP 2001379231A JP 2003179204 A JP2003179204 A JP 2003179204A
Authority
JP
Japan
Prior art keywords
thermoelectric
power
power semiconductor
semiconductor elements
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001379231A
Other languages
Japanese (ja)
Other versions
JP4085236B2 (en
Inventor
Akira Sasaki
亮 佐々木
Saemitsu Hayashi
賛恵光 林
Yuji Ishida
雄二 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yaskawa Electric Corp
Original Assignee
Yaskawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaskawa Electric Corp filed Critical Yaskawa Electric Corp
Priority to JP2001379231A priority Critical patent/JP4085236B2/en
Publication of JP2003179204A publication Critical patent/JP2003179204A/en
Application granted granted Critical
Publication of JP4085236B2 publication Critical patent/JP4085236B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power module which restrains a temperature distribution generated by heat generated by a power element, which cools the power element uniformly, which does not break down the power element and which is of high reliability. <P>SOLUTION: In the power module which is composed of a plurality of power elements 1, a heat dissipating base 6, an output terminal 5 and a control terminal 4, thermoelectric modules 7 in which thermoelectric semiconductor elements 7a for thermoelectric conversion are arranged on an insulating substrate so as to be divided into a plurality of regions are attached to positions coming into close contact with, or adjacent to, rear surfaces of the power elements 1, the plurality of regions are arranged individually at the respective power elements 1, and the mounting number of the elements and/or the arrangement interval of the elements are changed in the respective regions. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、サーボアンプやイ
ンバータに用いられると共に、パワー変換回路を構成す
るパワーモジュールの冷却構造と冷却方法に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cooling structure and a cooling method for a power module used in a servo amplifier or an inverter and constituting a power conversion circuit.

【0002】[0002]

【従来の技術】従来のパワーモジュールにおいては、パ
ワー半導体素子を絶縁回路基板に実装し、パワー半導体
素子と出力端子および制御端子との接続をアルミワイヤ
と絶縁回路基板のパターン配線で結線したものを放熱ベ
ース上に実装していた。図13に従来装置を示す。1は
パワー半導体素子で、2は絶縁回路基板で、3はアルミ
ワイヤで、4は制御端子、5は出力端子、6は放熱ベー
スである。以上の構成において、パワー半導体素子1と
制御端子4と出力端子5を絶縁回路基板2にはんだ付け
実装し、パワー半導体素子1と制御端子4および出力端
子5とをアルミワイヤ3で電気的に接続したものを放熱
ベース6にはんだ実装していた。上記のようなパワーモ
ジュールの構成において、制御端子6に外部装置から制
御信号を送りパワー半導体素子1をスイッチングさせて
インバータ動作を行い、出力端子5から負荷装置を運転
することができるようになっている。また、インバータ
動作したときにパワー半導体素子1に生じる熱は一旦絶
縁回路基板2に伝熱し、放熱ベースから外部へ放熱する
ようになっている。
2. Description of the Related Art In a conventional power module, a power semiconductor element is mounted on an insulating circuit board, and the power semiconductor element and output terminals and control terminals are connected by aluminum wires and pattern wiring on the insulating circuit board. It was mounted on the heat dissipation base. FIG. 13 shows a conventional device. 1 is a power semiconductor element, 2 is an insulating circuit board, 3 is an aluminum wire, 4 is a control terminal, 5 is an output terminal, and 6 is a heat dissipation base. In the above configuration, the power semiconductor element 1, the control terminal 4, and the output terminal 5 are mounted on the insulated circuit board 2 by soldering, and the power semiconductor element 1, the control terminal 4 and the output terminal 5 are electrically connected by the aluminum wire 3. This was solder-mounted on the heat dissipation base 6. In the configuration of the power module as described above, it becomes possible to operate the load device from the output terminal 5 by sending a control signal from the external device to the control terminal 6 to switch the power semiconductor element 1 to perform an inverter operation. There is. Further, the heat generated in the power semiconductor element 1 when the inverter operates is once transferred to the insulating circuit board 2 and radiated from the heat radiation base to the outside.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上記従
来のパワーモジュールにおいては、インバータ動作時に
生じる複数のパワー半導体素子の熱を、一旦絶縁回路基
板に伝熱し放熱ベースから外部へ放熱するようになって
いる。このため、インバータ動作した時に通電している
パワー半導体素子が切り替わりパワーモジュール内での
発熱位置が変わる場合には、パワーモジュール内の温度
分布が時間とともに変化するため、場所によって放熱が
十分でなくなり、パワー半導体素子が熱破壊するという
問題があった。また、複数のパワー半導体素子に同じ大
きさの電流を流した場合、パワーモジュールの中央部に
位置するパワー半導体素子の温度上昇はパワーモジュー
ルの端に位置するパワー半導体素子の温度上昇より相対
的に高くなり、中央部のパワー半導体素子が優先的に熱
破壊する問題があった。したがって本発明の目的は、複
数のパワー半導体素子の発熱によって生じる温度分布を
抑制し、パワー半導体素子を均一に冷却することでパワ
ー素子を破壊させない、信頼性の高いパワーモジュール
の冷却構造と冷却方法を提供することである。
However, in the above-mentioned conventional power module, the heat of the plurality of power semiconductor elements generated during the operation of the inverter is once transferred to the insulating circuit board and radiated to the outside from the heat dissipation base. There is. Therefore, when the power semiconductor element that is energized when the inverter operates and the heat generation position in the power module changes, the temperature distribution in the power module changes over time, so heat radiation becomes insufficient depending on the location. There is a problem that the power semiconductor element is thermally destroyed. Further, when the same amount of current is applied to a plurality of power semiconductor elements, the temperature rise of the power semiconductor element located at the center of the power module is relatively higher than the temperature rise of the power semiconductor element located at the end of the power module. There has been a problem that the power semiconductor element in the central portion becomes higher in temperature and is preferentially thermally destroyed. Therefore, an object of the present invention is to suppress the temperature distribution generated by heat generation of a plurality of power semiconductor elements and to uniformly cool the power semiconductor elements so that the power elements are not destroyed, and a highly reliable power module cooling structure and cooling method. Is to provide.

【0004】[0004]

【課題を解決するための手段】上記課題を解決するた
め、請求項1記載の冷却機構付きパワーモジュールの発
明は、複数のパワー半導体素子と放熱ベースと出力端子
と制御端子を備えたパワーモジュールにおいて、熱電変
換する熱電半導体素子に絶縁基板を設けた熱電モジュー
ルを前記パワー半導体素子の下面に密着若しくは近接し
た位置に、前記パワー半導体素子毎に配置したことを特
徴とする。請求項2記載の発明は、請求項1記載のパワ
ーモジュールにおいて、前記熱電半導体素子の素子搭載
数が異なった熱電モジュールを前記パワー半導体素子に
個別に配置したことを特徴とする。以上の構成により、
複数のパワー半導体素子を個別に冷却することができる
ため、複数のパワー半導体素子の発熱によって生じる温
度分布を抑制することが出来、パワー半導体素子の熱破
壊を防止することができる。
In order to solve the above problems, the invention of a power module with a cooling mechanism according to claim 1 is a power module having a plurality of power semiconductor elements, a heat dissipation base, an output terminal and a control terminal. A thermoelectric module in which an insulating substrate is provided on a thermoelectric semiconductor element for thermoelectric conversion is arranged for each power semiconductor element at a position close to or close to the lower surface of the power semiconductor element. According to a second aspect of the present invention, in the power module according to the first aspect, thermoelectric modules having different numbers of mounted thermoelectric semiconductor elements are individually arranged in the power semiconductor elements. With the above configuration,
Since the plurality of power semiconductor elements can be individually cooled, the temperature distribution caused by the heat generation of the plurality of power semiconductor elements can be suppressed, and the thermal destruction of the power semiconductor elements can be prevented.

【0005】また、請求項3記載の冷却機構付きパワー
モジュールの発明は、複数のパワー半導体素子と放熱ベ
ースと出力端子と制御端子からなるパワーモジュールに
おいて、熱電変換する熱電半導体素子を絶縁基板上に複
数の領域に分けて配置した熱電モジュールを前記パワー
半導体素子の下面に密着若しくは近接した位置に取り付
けたことを特徴とする。請求項4記載の発明は、請求項
3記載のパワーモジュールにおいて、前記熱電半導体素
子を配置した複数の領域が前記パワー半導体素子毎に個
別に配置されたことを特徴とする。以上の構成により、
パワー半導体素子の発熱にあわせて熱電モジュールの領
域毎に通電し冷却できるため、パワー半導体素子の温度
上昇を個別にあるいは領域毎に制御することができる。
請求項5記載の発明は、請求項3又は4記載のパワーモ
ジュールにおいて、前記熱電半導体素子を配置した複数
の領域毎に素子の搭載数および/又は素子の配置間隔を
変えたことを特徴とする。このように、領域毎の熱電半
導体素子の搭載数と素子間隔を変えて配置しているた
め、複数の領域を同じ条件で制御しても、領域毎に冷却
能力を変えることができる。請求項6記載のパワーモジ
ュールの冷却方法の発明は、請求項1又は2記載のパワ
ーモジュールの冷却において、前記パワー半導体の複数
個の熱電モジュールを個別に導通して冷却することを特
徴とする。請求項7記載の発明は、請求項3〜5のいず
れか1項記載のパワーモジュールの冷却において、前記
熱電半導体素子を配置した複数の領域間を配線により結
合し、結合した領域毎に個別に通電して冷却することを
特徴とする。請求項8記載の発明は、請求項4記載のパ
ワーモジュールの冷却において、前記熱電半導体素子を
配置した複数の領域毎に通電し、前記パワー半導体素子
を個別に冷却することを特徴とする。以上の構成によ
り、複数のパワー半導体素子を個別にあるいは領域毎に
冷却することができるため、複数のパワー半導体素子の
発熱によって生じる温度分布を抑制することができ、パ
ワー半導体素子の熱破壊を防止することができる。
According to the invention of a power module with a cooling mechanism as defined in claim 3, in a power module comprising a plurality of power semiconductor elements, a heat radiation base, an output terminal and a control terminal, a thermoelectric semiconductor element for thermoelectric conversion is placed on an insulating substrate. The thermoelectric module divided into a plurality of regions is attached to the lower surface of the power semiconductor element in a close contact or close position. According to a fourth aspect of the invention, in the power module according to the third aspect, a plurality of regions in which the thermoelectric semiconductor elements are arranged are individually arranged for each of the power semiconductor elements. With the above configuration,
Since it is possible to energize and cool each region of the thermoelectric module in accordance with the heat generation of the power semiconductor element, the temperature rise of the power semiconductor element can be controlled individually or in each region.
According to a fifth aspect of the present invention, in the power module according to the third or fourth aspect, the number of mounted elements and / or the arrangement interval of the elements are changed for each of a plurality of regions in which the thermoelectric semiconductor elements are arranged. . In this way, since the number of thermoelectric semiconductor elements to be mounted and the element spacing are changed for each region, the cooling capacity can be changed for each region even if a plurality of regions are controlled under the same conditions. According to a sixth aspect of the present invention, there is provided a power module cooling method according to the first or second aspect, wherein the plurality of thermoelectric modules of the power semiconductor are individually conducted and cooled. According to a seventh aspect of the invention, in cooling the power module according to any one of the third to fifth aspects, a plurality of regions in which the thermoelectric semiconductor elements are arranged are connected by wiring, and each of the combined regions is individually connected. It is characterized by energizing and cooling. The invention according to claim 8 is characterized in that, in the cooling of the power module according to claim 4, electricity is supplied to each of a plurality of regions in which the thermoelectric semiconductor elements are arranged to individually cool the power semiconductor elements. With the above configuration, the plurality of power semiconductor elements can be cooled individually or in each region, so that the temperature distribution generated by the heat generation of the plurality of power semiconductor elements can be suppressed and the thermal destruction of the power semiconductor elements can be prevented. can do.

【0006】[0006]

【発明の実施の形態】本発明の第1の実施の形態につい
て図1と図2に基づいて説明する。図1は、本発明の第
1実施の形態を示すパワーモジュールの側断面図であ
る。図において、7は熱電モジュールであり、熱電半導
体素子7a、絶縁基板7b、絶縁基板7c、端子7dか
らなる。熱電モジュール7は、N型およびP型の熱電半
導体素子7aを順番に並べて絶縁基板7b、絶縁基板7
cで挟み込んでいる。熱電半導体素子7a側となる絶縁
基板7bの下面、および絶縁基板7cの上面には熱電半
導体素子7aが各々直列に接続されるように回路配線が
施してあり、熱電半導体素子7aと絶縁基板7b、絶縁
基板7cは半田等によって固着されている。端子7d
は、一方の端部が絶縁基板7c上の熱電半導体素子7a
が接続された回路配線の始点と終点に接続されている。
絶縁基板7bの上面には、パワー半導体素子1と出力端
子5を介して電源と負荷が接続されるように回路配線8
が施してあり、パワー半導体素子1および制御端子4と
出力端子5が固着されている。絶縁基板7cは、半田等
によって放熱板1に固着されている。
BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a side sectional view of a power module showing a first embodiment of the present invention. In the figure, 7 is a thermoelectric module, which comprises a thermoelectric semiconductor element 7a, an insulating substrate 7b, an insulating substrate 7c, and a terminal 7d. In the thermoelectric module 7, the N-type and P-type thermoelectric semiconductor elements 7a are arranged in order, and the insulating substrate 7b and the insulating substrate 7 are arranged.
It is sandwiched by c. Circuit wiring is provided on the lower surface of the insulating substrate 7b on the thermoelectric semiconductor element 7a side and the upper surface of the insulating substrate 7c so that the thermoelectric semiconductor elements 7a are connected in series, and the thermoelectric semiconductor element 7a and the insulating substrate 7b are connected. The insulating substrate 7c is fixed by solder or the like. Terminal 7d
Has one end on the thermoelectric semiconductor element 7a on the insulating substrate 7c.
Are connected to the start and end points of the connected circuit wiring.
Circuit wiring 8 is formed on the upper surface of the insulating substrate 7b so that a power source and a load are connected via the power semiconductor element 1 and the output terminal 5.
The power semiconductor element 1, the control terminal 4 and the output terminal 5 are fixed to each other. The insulating substrate 7c is fixed to the heat dissipation plate 1 by soldering or the like.

【0007】次にこのような熱電モジュール7を放熱ベ
ース上に6個搭載したパワーモジュールの冷却を図2を
使って説明する。図は厚さ4mmの銅製放熱ベース6の
上に6個の熱電モジュール7に各々IGBTパワー半導
体素子1を各1個づつ搭載したものをはんだ付けにより
実装し、インバータ回路を構成した。6個のパワー半導
体素子はそれぞれU相上アームのパワー半導体素子1U
1、U相下アームのパワー半導体素子1U2、V相上ア
ームのパワー半導体素子1V1、V相下アームのパワー
半導体素子1V2、W相上アームのパワー半導体素子1
W1、W相下アームのパワー半導体素子1W2としてい
る。これらのパワー半導体素子1に取り付ける熱電モジ
ュール7はそれぞれ、U相上アームの熱電モジュール7
U1、U相下アームの熱電モジュール7U2、V相上ア
ームの熱電モジュール7V1、V相下アームの熱電モジ
ュール7V2、W相上アームの熱電モジュール7W1、
W相下アームの熱電モジュール7W2としている。この
ような構成のインバータ回路ではパワー半導体素子の通
電を次のように行った。16.7Hzの周波数で運転す
る場合には0.01秒毎に同時にONとなるパワー半導
体素子は、まず、1U1・1V2・1W1の状態から
1U1・1V2・1W2、1U1・1V1・1W
2、1U2・1V1・1W2、1U2・1V1・1
W1、1U2・1V2・1W1の状態に順次切り替わ
る。このため〜それぞれの状態で、通電する熱電モ
ジュールは0.01秒ごとに7U1・7V2・7W1
の状態から7U1・7V2・7W2、7U1・7V
1・7W2、7U2・7V1・7W2、7U2・7
V1・7W1、7U2・7V2・7W1とした。この
ようにパワー半導体素子1のスイッチングに合わせて、
熱電モジュール7の通電を行い、冷却できた。この結
果、パワー半導体素子1の温度上昇を低く抑えることが
でき、しかも各素子の温度を均一化することができた。
このため、素子配置より影響を受けるパワー半導体素子
1の熱破壊による寿命のばらつきを少なくすることがで
きた。なお、6個の熱電モジュール7を同時に通電する
こともできるし、6個の熱電モジュール7を個別に電流
値を変えて通電して冷却することもできる。この実施の
形態によれば、複数のパワー半導体素子と放熱ベースと
出力端子と制御端子からなるパワーモジュールにおい
て、前記パワー半導体素子の下面に密着若しくは近接し
た位置に、熱電変換する熱電半導体素子に絶縁基板を設
けた熱電モジュールを前記パワー半導体素子に個別に配
置し、熱電モジュールを半導体モジュールの通電による
温度上昇に併せて個別に導通させて冷却するため、パワ
ーモジュールの複数のパワー半導体素子の発熱によって
生じる温度分布を抑制し、パワー半導体素子を均一に冷
却することでパワー素子を破壊させない、信頼性の高い
パワーモジュールを提供することができる。
Next, cooling of a power module having six such thermoelectric modules 7 mounted on a heat dissipation base will be described with reference to FIG. In the figure, six thermoelectric modules 7 each having one IGBT power semiconductor element 1 mounted on a copper heat dissipation base 6 having a thickness of 4 mm are mounted by soldering to form an inverter circuit. Each of the six power semiconductor devices is a power semiconductor device 1U of the U-phase upper arm.
1. Power semiconductor element 1U2 of U-phase lower arm, power semiconductor element 1V1 of V-phase upper arm, power semiconductor element 1V2 of V-phase lower arm, power semiconductor element 1 of W-phase upper arm
The power semiconductor element 1W2 of the W1 and W phase lower arms is used. The thermoelectric modules 7 attached to these power semiconductor elements 1 are the thermoelectric modules 7 of the U-phase upper arm, respectively.
U1, U-phase lower arm thermoelectric module 7U2, V-phase upper arm thermoelectric module 7V1, V-phase lower arm thermoelectric module 7V2, W-phase upper arm thermoelectric module 7W1,
The thermoelectric module 7W2 of the W-phase lower arm is used. In the inverter circuit having such a configuration, the power semiconductor element was energized as follows. When operating at a frequency of 16.7 Hz, the power semiconductor elements that are turned on at the same time every 0.01 seconds are as follows: 1U1, 1V2, 1W1, 1U1, 1V2, 1W2, 1U1, 1V1, 1W
2, 1U2.1V1 1W2, 1U2.1V1.1
The state is sequentially switched to W1, 1U2, 1V2, 1W1. For this reason, in each state, the thermoelectric module that is energized has 7U1, 7V2, 7W1 every 0.01 seconds.
From the state of 7U1.7V2 / 7W2, 7U1.7V
1.7W2, 7U2, 7V1, 7W2, 7U2.7
It was set to V1 · 7W1 and 7U2 · 7V2 · 7W1. In this way, according to the switching of the power semiconductor device 1,
The thermoelectric module 7 was energized and cooled. As a result, the temperature rise of the power semiconductor element 1 can be suppressed to a low level, and the temperature of each element can be made uniform.
For this reason, it is possible to reduce variations in life due to thermal destruction of the power semiconductor element 1 which is affected by the element arrangement. The six thermoelectric modules 7 can be energized at the same time, or the six thermoelectric modules 7 can be energized and cooled by individually changing the current values. According to this embodiment, in a power module including a plurality of power semiconductor elements, a heat radiation base, an output terminal, and a control terminal, a thermoelectric semiconductor element for thermoelectric conversion is insulated at a position close to or close to the lower surface of the power semiconductor element. A thermoelectric module provided with a substrate is individually arranged on the power semiconductor element, and the thermoelectric module is individually conducted and cooled in accordance with a temperature rise due to energization of the semiconductor module, so that the power semiconductor elements of the power module generate heat. It is possible to provide a highly reliable power module in which the power element is not destroyed by suppressing the generated temperature distribution and cooling the power semiconductor element uniformly.

【0008】本発明の第2の実施の形態について図3に
基づいて説明する。図において、7xと7yは熱電モジ
ュールであり、熱電半導体素子7a、絶縁基板7b、絶
縁基板7c、端子7dからなる。熱電モジュール7x
は、N型およびP型の熱電半導体素子7aを順番に並べ
て絶縁基板7b、絶縁基板7cで挟み込んでいる。熱電
半導体素子7a側となる絶縁基板7bの下面、および絶
縁基板7cの上面には熱電半導体素子7aが8個直列に
したものを8列で合計64個接続されるように回路配線
が施してあり、熱電半導体素子7aと絶縁基板7b、絶
縁基板7cは半田等によって固着されている。端子7d
は、一方の端部が絶縁基板7c上の熱電半導体素子7a
が接続された回路配線の始点と終点に接続されている。
一方、熱電モジュール7yは、N型およびP型の熱電半
導体素子7aを順番に並べて絶縁基板7b、絶縁基板7
cで挟み込んでいる。熱電半導体素子7a側となる絶縁
基板7bの下面、および絶縁基板7cの上面には熱電半
導体素子7aが6個直列にしたものを6列で合計36個
接続されるように回路配線が施してあり、熱電半導体素
子7aと絶縁基板7b、絶縁基板7cは半田等によって
固着されている。端子7dは、一方の端部が絶縁基板7
c上の熱電半導体素子7aが接続された回路配線の始点
と終点に接続されている。図のパワーモジュールには熱
電半導体素子7aの搭載数が異なる熱電モジュール7x
を1個と熱電モジュール7yを2個放熱ベース6にはん
だ等により実装している。
A second embodiment of the present invention will be described with reference to FIG. In the figure, 7x and 7y are thermoelectric modules, which are composed of a thermoelectric semiconductor element 7a, an insulating substrate 7b, an insulating substrate 7c, and a terminal 7d. Thermoelectric module 7x
In, the N-type and P-type thermoelectric semiconductor elements 7a are arranged in order and sandwiched by the insulating substrate 7b and the insulating substrate 7c. Circuit wiring is provided on the lower surface of the insulating substrate 7b on the thermoelectric semiconductor element 7a side and the upper surface of the insulating substrate 7c so that a total of 64 thermoelectric semiconductor elements 7a connected in series are connected in 8 rows. The thermoelectric semiconductor element 7a, the insulating substrate 7b, and the insulating substrate 7c are fixed by soldering or the like. Terminal 7d
Has one end on the thermoelectric semiconductor element 7a on the insulating substrate 7c.
Are connected to the start and end points of the connected circuit wiring.
On the other hand, in the thermoelectric module 7y, the N-type and P-type thermoelectric semiconductor elements 7a are arranged in order and the insulating substrate 7b and the insulating substrate 7 are arranged.
It is sandwiched by c. Circuit wiring is provided on the lower surface of the insulating substrate 7b on the thermoelectric semiconductor element 7a side and the upper surface of the insulating substrate 7c so that a total of 36 thermoelectric semiconductor elements 7a connected in series are connected in 6 rows. The thermoelectric semiconductor element 7a, the insulating substrate 7b, and the insulating substrate 7c are fixed by soldering or the like. One end of the terminal 7d is the insulating substrate 7
The thermoelectric semiconductor element 7a on c is connected to the start point and the end point of the connected circuit wiring. In the power module shown in the figure, the thermoelectric module 7x in which the number of thermoelectric semiconductor elements 7a mounted is different
1 and two thermoelectric modules 7y are mounted on the heat dissipation base 6 by soldering or the like.

【0009】次にこの熱電モジュール7xを1個と熱電
モジュール7yを2個を混載したパワーモジュールの冷
却方法を説明する。図の両端のパワー半導体素子1が同
時にONしたときは、中央のパワー半導体素子1はOF
Fする動作をし、両端のパワー半導体素子1が同時にO
FFしたときは、中央のパワー半導体素子1はONする
ものとする。従来のパワー半導体素子1と制御端子4と
出力端子5を絶縁回路基板2にはんだ付け実装し、パワ
ー半導体素子1と制御端子4および出力端子5とをアル
ミワイヤ3で電気的に接続したものを放熱ベース6には
んだ実装しているパワーモジュールの場合には、両端の
パワー半導体素子1と中央のパワー半導体素子1のスイ
ッチングの繰り返しによる発熱により、放熱ベース6の
中央部が両端部より温度が高くなり、その結果中央のパ
ワー半導体素子1のON時の温度が、両端のパワー半導
体素子1の温度より高くなり、中央のパワー半導体素子
が優先的に熱破壊してしまう。本発明では中央のパワー
半導体素子1は熱電半導体素子7aを64個搭載した熱
電モジュール7xに取り付けており、両端のパワー半導
体素子1には熱電半導体素子7aを36個搭載した熱電
モジュール7yに取り付けている。熱電モジュール7x
と熱電モジュール7yに同じ電流を常時流した状態で、
パワー半導体のスイッチングを行うと、中央のパワー半
導体素子1に取り付けた熱電モジュール7xは両端のパ
ワー半導体素子1に取り付けた熱電モジュール7yより
熱電半導体素子が多く搭載してあるため、熱電モジュー
ル7xに取り付けられているパワー半導体素子1の温度
は両端部に位置するパワー半導体素子1の温度と同じ温
度になるように冷却することができた。なお、中央部に
位置する熱電モジュール7xに流す電流値を両端に位置
する熱電モジュール7yに流す電流値より大きな電流を
流してもよく、この場合中央部のパワー半導体素子1の
温度をさらに下げることもできる。また、熱電モジュー
ル7xと熱電モジュール7yに流す電流値を個別に変え
てもよい。
Next, a method of cooling a power module in which one thermoelectric module 7x and two thermoelectric modules 7y are mounted together will be described. When the power semiconductor elements 1 at both ends of the figure are simultaneously turned on,
The power semiconductor elements 1 at both ends are simultaneously turned on
When FF is performed, the power semiconductor element 1 in the center is turned on. The conventional power semiconductor device 1, the control terminal 4, and the output terminal 5 are mounted on the insulated circuit board 2 by soldering, and the power semiconductor device 1, the control terminal 4, and the output terminal 5 are electrically connected by the aluminum wire 3. In the case of the power module solder-mounted on the heat dissipation base 6, the temperature of the center part of the heat dissipation base 6 is higher than that of both ends due to heat generation due to repeated switching of the power semiconductor elements 1 at both ends and the power semiconductor element 1 at the center. As a result, the temperature of the central power semiconductor element 1 at the time of ON becomes higher than the temperature of the power semiconductor elements 1 at both ends, and the central power semiconductor element is preferentially thermally destroyed. In the present invention, the power semiconductor element 1 at the center is attached to the thermoelectric module 7x having 64 thermoelectric semiconductor elements 7a mounted, and the power semiconductor element 1 at both ends is attached to the thermoelectric module 7y having 36 thermoelectric semiconductor elements 7a mounted. There is. Thermoelectric module 7x
And the thermoelectric module 7y with the same current constantly flowing,
When the power semiconductors are switched, the thermoelectric module 7x attached to the central power semiconductor element 1 has more thermoelectric semiconductor elements than the thermoelectric modules 7y attached to the power semiconductor elements 1 at both ends. Therefore, the thermoelectric module 7x is attached to the thermoelectric module 7x. It was possible to cool the power semiconductor element 1 so that the temperature of the power semiconductor element 1 was the same as that of the power semiconductor elements 1 located at both ends. It should be noted that a current value flowing through the thermoelectric module 7x located in the central portion may be larger than a current value flowing through the thermoelectric modules 7y located at both ends. In this case, the temperature of the power semiconductor element 1 in the central portion should be further lowered. You can also Moreover, you may change the electric current value sent to the thermoelectric module 7x and the thermoelectric module 7y individually.

【0010】この実施の形態によれば、請求項1記載の
パワーモジュールの熱電モジュールにおいて、熱電半導
体素子の素子搭載数が異なった熱電モジュールを前記パ
ワー半導体素子に個別に配置したことにより、パワーモ
ジュールの複数のパワー半導体素子の発熱によって生じ
る温度分布を抑制し、パワー半導体素子を均一に冷却す
ることでパワー素子を破壊させない、信頼性の高いパワ
ーモジュールを提供することができる。
According to this embodiment, in the thermoelectric module of the power module according to claim 1, by disposing thermoelectric modules having different numbers of mounted thermoelectric semiconductor elements individually in the power semiconductor element, the power module It is possible to provide a highly reliable power module which suppresses the temperature distribution caused by the heat generation of the plurality of power semiconductor elements and uniformly cools the power semiconductor elements without damaging the power elements.

【0011】本発明の第3の実施の形態について図4と
図5に基づいて説明する。図4は、本発明の第3の実施
の形態を示すパワーモジュールの側断面図である。図4
において、7は熱電モジュールであり、熱電半導体素子
7a、絶縁基板7b、絶縁基板7c、端子7dからな
る。熱電モジュール7は、N型およびP型の熱電半導体
素子7aを順番に並べて絶縁基板7b、絶縁基板7cで
挟み込んでいる。熱電半導体素子7a側となる絶縁基板
7bの下面、および絶縁基板7cの上面には熱電半導体
素子7aが各々直列に接続されるように回路配線が施し
てあり、熱電半導体素子7aと絶縁基板7b、絶縁基板
7cは半田等によって固着されている。端子7dは、一
方の端部が絶縁基板7c上の熱電半導体素子7aが接続
された回路配線の始点と終点に接続されている。絶縁基
板7bの上面には、パワー半導体素子1と出力端子5を
介して電源と負荷が接続されるように回路配線8が施し
てあり、パワー半導体素子1および制御端子4と出力端
子5が固着されている。絶縁基板7cは、半田等によっ
て放熱板1に固着されている。
A third embodiment of the present invention will be described with reference to FIGS. 4 and 5. FIG. 4 is a side sectional view of a power module showing a third embodiment of the present invention. Figure 4
In the figure, 7 is a thermoelectric module, which comprises a thermoelectric semiconductor element 7a, an insulating substrate 7b, an insulating substrate 7c, and a terminal 7d. In the thermoelectric module 7, N-type and P-type thermoelectric semiconductor elements 7a are arranged in order and sandwiched by an insulating substrate 7b and an insulating substrate 7c. Circuit wiring is provided on the lower surface of the insulating substrate 7b on the thermoelectric semiconductor element 7a side and the upper surface of the insulating substrate 7c so that the thermoelectric semiconductor elements 7a are connected in series, and the thermoelectric semiconductor element 7a and the insulating substrate 7b are connected. The insulating substrate 7c is fixed by solder or the like. One end of the terminal 7d is connected to the start point and the end point of the circuit wiring to which the thermoelectric semiconductor element 7a on the insulating substrate 7c is connected. Circuit wiring 8 is provided on the upper surface of the insulating substrate 7b so that a power source and a load are connected via the power semiconductor element 1 and the output terminal 5, and the power semiconductor element 1, the control terminal 4 and the output terminal 5 are fixed. Has been done. The insulating substrate 7c is fixed to the heat dissipation plate 1 by soldering or the like.

【0012】次に、熱電半導体素子7aの素子配置を領
域毎に分けた熱電モジュール7を図5を使って説明す
る。図5はパワー半導体素子1を6個搭載した場合の熱
電モジュール7内を6つの領域にわけて熱電半導体素子
を配置したものである。この熱電モジュール7には熱電
半導体素子7aの大きさと配置間隔を同じ大きさにとり
8行9列の合計72個の素子を配置した領域7xと同様
に6行5列の合計30個の素子を配置した領域7yの二
種類を作成した。7yを配線し2つを直列に結合したを
熱電モジュール7の両端に配置し、中央には7xを2つ
直列に結合したものを配置した。この熱電モジュール7
では、パワー半導体素子1のスイッチングに同期させ
て、それぞれ結合した7x、7yの領域に端子7dに個
別に通電して冷却の制御を行った。この結果、7xと7
yの領域にあるパワー半導体素子1の温度上昇を個別に
低く抑えることができ、しかも各素子の温度を均一化す
ることができた。このため、素子配置より影響を受ける
パワー半導体素子1の熱破壊による寿命のばらつきを少
なくすることができた。また、7xと7yの領域の通電
値を変えて冷却することもできる。さらに図6に示すよ
うに、7xと7yのすべての領域間を配線により結合
し、2つの端子7dで冷却を制御することもできる。こ
の場合、冷却能力は7xと7yの素子の搭載数に比例し
て高くなるため、熱電モジュール7ではモジュールの中
央部のパワー半導体素子の温度が高くなることを考慮し
て中央の領域に7xを配置した。この実施の形態によれ
ば、複数のパワー半導体素子と放熱ベースと出力端子と
制御端子からなるパワーモジュールにおいて、前記パワ
ー半導体素子の下面に密着若しくは近接した位置に、熱
電変換する熱電半導体素子を絶縁基板上に複数の領域に
分けて配置した熱電モジュールを取り付けたことを特徴
とするパワーモジュールの冷却構造であり、請求項1記
載のパワーモジュールの熱電モジュールにおいて、前記
熱電半導体素子を配置した複数の領域が前記パワー半導
体素子に個別に配置したことを特徴とするパワーモジュ
ールの冷却構造である。また、前記熱電半導体素子を配
置した複数の領域間を配線により結合し、結合した領域
毎に個別に冷却するため、パワーモジュールの複数のパ
ワー半導体素子の発熱によって生じる温度分布を抑制
し、パワー半導体素子を均一に冷却することでパワー素
子を破壊させない、信頼性の高いパワーモジュールを提
供することができる。
Next, the thermoelectric module 7 in which the element arrangement of the thermoelectric semiconductor element 7a is divided into regions will be described with reference to FIG. FIG. 5 shows that the thermoelectric semiconductor elements are arranged by dividing the inside of the thermoelectric module 7 when six power semiconductor elements 1 are mounted into six regions. In this thermoelectric module 7, the thermoelectric semiconductor elements 7a are arranged to have the same size and arrangement interval, and a total of 30 elements of 6 rows and 5 columns are arranged in the same manner as the region 7x in which 72 elements of 8 rows and 9 columns are arranged. Two types of regions 7y were prepared. 7y was wired and two of them were connected in series were arranged at both ends of the thermoelectric module 7, and two 7x were connected in series at the center. This thermoelectric module 7
Then, in synchronization with the switching of the power semiconductor element 1, the terminals 7d are individually energized in the coupled 7x and 7y regions to control the cooling. As a result, 7x and 7
The temperature rise of the power semiconductor element 1 in the y region can be individually suppressed low, and the temperature of each element can be made uniform. For this reason, it is possible to reduce variations in life due to thermal destruction of the power semiconductor element 1 which is affected by the element arrangement. It is also possible to change the energization value in the 7x and 7y regions for cooling. Further, as shown in FIG. 6, all the regions 7x and 7y can be connected by wiring to control the cooling by the two terminals 7d. In this case, the cooling capacity increases in proportion to the number of mounted 7x and 7y elements, so in the thermoelectric module 7, the temperature of the power semiconductor element in the central part of the module becomes high, so that 7x is set in the central region. I placed it. According to this embodiment, in a power module including a plurality of power semiconductor elements, a heat radiation base, an output terminal, and a control terminal, a thermoelectric semiconductor element for thermoelectric conversion is insulated at a position close to or close to the lower surface of the power semiconductor element. It is a cooling structure for a power module, characterized in that a thermoelectric module arranged in a plurality of regions is mounted on a substrate, wherein the thermoelectric module of the power module according to claim 1 has a plurality of thermoelectric semiconductor elements arranged therein. A cooling structure of a power module, wherein regions are individually arranged in the power semiconductor element. In addition, since the plurality of regions in which the thermoelectric semiconductor elements are arranged are coupled by wiring and each coupled region is individually cooled, the temperature distribution generated by the heat generation of the plurality of power semiconductor elements of the power module is suppressed, and the power semiconductor It is possible to provide a highly reliable power module that does not damage the power element by uniformly cooling the element.

【0013】本発明の第4の実施の形態について図7と
図8に基づいて説明する。図7と図8において、パワー
半導体素子1を6個搭載した場合の熱電モジュール7内
を6つの領域にわけて熱電半導体素子を配置したもので
ある。この熱電モジュール7には熱電半導体素子7aの
大きさと配置間隔を同じ大きさにとり8行9列の合計7
2個の素子を配置した領域7xと6行5列の合計30個
の素子を熱電半導体素子7aの2倍の間隔を空け配置し
た領域7mの二種類を作成した。7mを直列に2つ結合
したものを熱電モジュール7の両端にそれぞれ配置し、
中央には7xを直列に2つ結合したものを配置した。こ
の熱電モジュール7では、パワー半導体素子1のスイッ
チングに同期させて、それぞれ7x、7mの領域の熱電
モジュールに端子7dに領域毎に個別に通電して冷却の
制御を行った。この結果、パワー半導体素子1の温度上
昇を領域毎に低く抑えることができ、しかも各素子の温
度を均一化することができた。このため、素子配置より
影響を受けるパワー半導体素子1の熱破壊による寿命の
ばらつきを少なくすることができた。また、7xと7m
の領域の通電値を変えて冷却制御することもできる。
A fourth embodiment of the present invention will be described with reference to FIGS. 7 and 8. In FIG. 7 and FIG. 8, the thermoelectric semiconductor element is arranged by dividing the inside of the thermoelectric module 7 when six power semiconductor elements 1 are mounted into six regions. In this thermoelectric module 7, the size of the thermoelectric semiconductor elements 7a and the arrangement interval are set to the same size, and a total of 7 rows and 9 columns.
Two types were prepared: a region 7x in which two elements are arranged and a region 7m in which a total of 30 elements in 6 rows and 5 columns are arranged with a gap twice as large as that of the thermoelectric semiconductor element 7a. The two 7m connected in series are arranged at both ends of the thermoelectric module 7,
In the center, two 7x are connected in series. In this thermoelectric module 7, in synchronization with the switching of the power semiconductor element 1, the terminals 7d were individually energized to the thermoelectric modules in the areas 7x and 7m, respectively, to control the cooling. As a result, the temperature rise of the power semiconductor element 1 can be suppressed low in each region, and the temperature of each element can be made uniform. For this reason, it is possible to reduce variations in life due to thermal destruction of the power semiconductor element 1 which is affected by the element arrangement. Also, 7x and 7m
It is also possible to control the cooling by changing the energization value in the area.

【0014】本発明の第5の実施の形態について図9と
図10に基づいて説明する。図9と図10において、パ
ワー半導体素子1を6個搭載した場合の熱電モジュール
7内を6つの領域にわけて熱電半導体素子を配置したも
のである。この熱電モジュール7には熱電半導体素子7
aの大きさと配置間隔を同じ大きさにとり8行9列の合
計72個の素子を配置した領域7xと6行5列の合計3
0個の素子を中心の12個の熱電半導体素子7aを素子
の大きさと配置間隔を同じにした配列とし、周囲の18
個を熱電半導体素子7aの2倍の間隔を空けた領域7n
の二種類を作成した。7nを2つ直列に結合したものを
熱電モジュール7の両端にそれぞれ配置し、中央には7
xを2つ直列に結合したものを配置した。この熱電モジ
ュール7では、パワー半導体素子1のスイッチングに同
期させて、それぞれ7x、7nの領域の熱電モジュール
に端子7dに個別に通電して冷却の制御を行った。この
結果、パワー半導体素子1の温度上昇を領域毎に低く抑
えることができ、しかも各素子の温度を均一化すること
ができた。このため、素子配置より影響を受けるパワー
半導体素子1の熱破壊による寿命のばらつきを少なくす
ることができた。また、7xと7nの領域の通電値を変
えて冷却することもできる。この実施の形態によれば、
複数のパワー半導体素子と放熱ベースと出力端子と制御
端子からなるパワーモジュールにおいて、前記パワー半
導体素子の下面に密着若しくは近接した位置に、熱電変
換する熱電半導体素子を絶縁基板上に複数の領域に分け
て配置した熱電モジュールを取り付けたことを特徴とす
るパワーモジュールの冷却構造であり、前記熱電半導体
素子を配置した複数の領域毎に素子の搭載数と素子の配
置間隔を変えたことを特徴とするパワーモジュールの冷
却構造である。また、前記熱電半導体素子を配置した複
数の領域間を配線により結合し、結合した領域毎に個別
に冷却するため、パワーモジュールの複数のパワー半導
体素子の発熱によって生じる温度分布を抑制し、パワー
半導体素子を均一に冷却することでパワー素子を破壊さ
せない、信頼性の高いパワーモジュールを提供すること
ができる。
A fifth embodiment of the present invention will be described with reference to FIGS. 9 and 10. In FIG. 9 and FIG. 10, the thermoelectric semiconductor elements are arranged by dividing the inside of the thermoelectric module 7 when six power semiconductor elements 1 are mounted into six regions. The thermoelectric module 7 includes a thermoelectric semiconductor element 7
An area 7x in which 72 elements are arranged in 8 rows and 9 columns and a total of 3 rows in 6 rows and 5 columns are arranged with the same size of a and the arrangement interval.
Twelve thermoelectric semiconductor elements 7a having 0 elements at the center are arrayed with the same element size and arrangement interval, and the surrounding 18
A region 7n in which the distance between the thermoelectric semiconductor device 7a and the thermoelectric semiconductor device 7a is twice.
I created two types. Two 7n connected in series are arranged at both ends of the thermoelectric module 7, and 7n in the center.
A combination of two x's connected in series was arranged. In this thermoelectric module 7, in synchronization with the switching of the power semiconductor element 1, the thermoelectric modules in the areas 7x and 7n were individually energized to the terminals 7d to control the cooling. As a result, the temperature rise of the power semiconductor element 1 can be suppressed low in each region, and the temperature of each element can be made uniform. For this reason, it is possible to reduce variations in life due to thermal destruction of the power semiconductor element 1 which is affected by the element arrangement. Further, it is also possible to change the energization values in the 7x and 7n regions for cooling. According to this embodiment,
In a power module including a plurality of power semiconductor elements, a heat dissipation base, an output terminal and a control terminal, a thermoelectric semiconductor element for thermoelectric conversion is divided into a plurality of regions on an insulating substrate at a position in close contact with or close to the lower surface of the power semiconductor element. Is a cooling structure of a power module, characterized in that the thermoelectric modules arranged in a plurality are arranged, and the number of mounted elements and the arrangement interval of the elements are changed for each of a plurality of regions in which the thermoelectric semiconductor elements are arranged. It is a cooling structure of the power module. In addition, since the plurality of regions in which the thermoelectric semiconductor elements are arranged are coupled by wiring and each coupled region is individually cooled, the temperature distribution generated by the heat generation of the plurality of power semiconductor elements of the power module is suppressed, and the power semiconductor It is possible to provide a highly reliable power module that does not damage the power element by uniformly cooling the element.

【0015】本発明の第6の実施の形態について図11
と図12に基づいて説明する。図11と図12におい
て、パワー半導体素子1を6個搭載した場合の熱電モジ
ュール7内を6つの領域にわけて熱電半導体素子を配置
したものである。この熱電モジュール7には熱電半導体
素子7aの大きさと配置間隔を同じ大きさにとり8行8
列の合計64個の素子を配置した領域7oと6行6列の
合計36個の熱電半導体素子7aの大きさと配置間隔を
同じ大きさにとり配置した領域7pの二種類を作成し
た。熱電モジュール7の両端には7pを4つ配置しそれ
ぞれに端子7dを設けた。また中央には7oを2つ配置
しそれぞれに端子7dを設けた。この熱電モジュール7
では、パワー半導体素子1のスイッチングに同期させ
て、それぞれ7pの4領域と、7oの2領域の端子7d
に個別に通電して冷却の制御を行った。この結果、パワ
ー半導体素子1の温度上昇を6つの素子と領域すべてで
低く抑えることができ、しかも各素子の温度を均一化す
ることができた。このため、素子配置より影響を受ける
パワー半導体素子1の熱破壊による寿命のばらつきを少
なくすることができた。また、7pと7oの領域の通電
値を変えて冷却することもできる。この実施の形態によ
れば、複数のパワー半導体素子と放熱ベースと出力端子
と制御端子からなるパワーモジュールにおいて、前記パ
ワー半導体素子の下面に密着若しくは近接した位置に、
熱電変換する熱電半導体素子を絶縁基板上に複数の領域
に分けて配置した熱電モジュールを取り付けたことを特
徴とするパワーモジュールの冷却構造であり、請求項1
記載のパワーモジュールの熱電モジュールにおいて、前
記熱電半導体素子を配置した複数の領域が前記パワー半
導体素子に個別に配置したことを特徴とするパワーモジ
ュールの冷却構造である。また、前記熱電半導体素子を
配置した複数の領域毎に通電し、前記パワー半導体素子
を個別に冷却するため、パワーモジュールの複数のパワ
ー半導体素子の発熱によって生じる温度分布を抑制し、
パワー半導体素子を均一に冷却することでパワー素子を
破壊させない、信頼性の高いパワーモジュールを提供す
ることができる。
FIG. 11 shows the sixth embodiment of the present invention.
Will be described with reference to FIG. 11 and 12, the thermoelectric semiconductor element is arranged by dividing the inside of the thermoelectric module 7 when six power semiconductor elements 1 are mounted into six regions. In this thermoelectric module 7, the thermoelectric semiconductor elements 7a are arranged in the same size and arrangement interval as 8 rows and 8 rows.
Two types of regions 7o were prepared in which a region 7o having a total of 64 elements arranged in a column and a total of 36 thermoelectric semiconductor devices 7a having a total of 6 rows and 6 columns were arranged with the same size and arrangement interval. Four 7p were arranged at both ends of the thermoelectric module 7 and terminals 7d were provided on each of them. Further, two 7o are arranged in the center and a terminal 7d is provided for each. This thermoelectric module 7
Then, in synchronization with the switching of the power semiconductor element 1, the terminals 7d of 4 regions of 7p and 2 regions of 7o are respectively formed.
Was individually energized to control cooling. As a result, the temperature rise of the power semiconductor element 1 can be suppressed low in all six elements and regions, and the temperature of each element can be made uniform. For this reason, it is possible to reduce variations in life due to thermal destruction of the power semiconductor element 1 which is affected by the element arrangement. It is also possible to change the energization value in the areas 7p and 7o for cooling. According to this embodiment, in a power module including a plurality of power semiconductor elements, a heat dissipation base, an output terminal, and a control terminal, at a position close to or close to the lower surface of the power semiconductor element,
2. A cooling structure for a power module, comprising: a thermoelectric module having a thermoelectric semiconductor element for thermoelectric conversion divided into a plurality of regions on an insulating substrate.
The thermoelectric module of the power module described above is a cooling structure for a power module, wherein a plurality of regions in which the thermoelectric semiconductor elements are arranged are individually arranged in the power semiconductor element. Further, the plurality of regions in which the thermoelectric semiconductor elements are arranged are energized to individually cool the power semiconductor elements, so that the temperature distribution caused by the heat generation of the plurality of power semiconductor elements of the power module is suppressed,
It is possible to provide a highly reliable power module that does not destroy the power element by uniformly cooling the power semiconductor element.

【0016】[0016]

【発明の効果】以上述べたように、本発明は複数のパワ
ー半導体素子と放熱ベースと出力端子と制御端子からな
るパワーモジュールにおいて、前記パワー半導体素子の
下面に密着若しくは近接した位置に、熱電変換する熱電
半導体素子に絶縁基板を設けた熱電モジュールを前記パ
ワー半導体素子に個別に配置し、熱電半導体素子の素子
搭載数が異なった熱電モジュールを前記パワー半導体素
子に個別に配置し、さらに熱電半導体素子を絶縁基板上
に複数の領域に分けて配置し、前記複数の領域が前記パ
ワー半導体素子毎に個別に配置され、そして熱電半導体
素子を配置した複数の領域毎に素子の搭載数および/又
は素子の配置間隔を変えたことにより、複数のパワー半
導体素子の発熱によって生じる温度分布を抑制し、パワ
ー半導体素子を均一に冷却することでパワー素子を破壊
させない、信頼性の高いパワーモジュールとすることが
できる。また、発熱してないパワー半導体素子に通電す
る必要がないため、消費電力を抑えることができる。
As described above, according to the present invention, in a power module comprising a plurality of power semiconductor elements, a heat dissipation base, an output terminal and a control terminal, thermoelectric conversion is performed at a position close to or close to the lower surface of the power semiconductor element. A thermoelectric module having an insulating substrate provided on the thermoelectric semiconductor element is individually arranged on the power semiconductor element, and thermoelectric modules having different numbers of mounted thermoelectric semiconductor elements are individually arranged on the power semiconductor element. Are arranged in a plurality of regions on an insulating substrate, the plurality of regions are individually arranged for each of the power semiconductor elements, and the number of mounted elements and / or elements for each of the plurality of areas where thermoelectric semiconductor elements are arranged. By changing the arrangement interval of the power semiconductor elements, the temperature distribution caused by the heat generation of the plurality of power semiconductor elements is suppressed, and the power semiconductor elements are evenly distributed. Not destroy the power element by cooling to be a highly reliable power module. Further, since it is not necessary to energize the power semiconductor element that does not generate heat, it is possible to suppress power consumption.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施の形態を示すパワーモジュ
ールの側断面図である。
FIG. 1 is a side sectional view of a power module showing a first embodiment of the present invention.

【図2】図1のパワーモジュールの斜視図である。FIG. 2 is a perspective view of the power module shown in FIG.

【図3】本発明の第2の実施の形態のパワーモジュール
を示す側断面図である。
FIG. 3 is a side sectional view showing a power module according to a second embodiment of the present invention.

【図4】本発明の第3の実施の形態のパワーモジュール
を示す側断面図である。
FIG. 4 is a side sectional view showing a power module according to a third embodiment of the present invention.

【図5】本発明の第3の実施の形態の熱電半導体素子の
配線図である。
FIG. 5 is a wiring diagram of a thermoelectric semiconductor element according to a third embodiment of the present invention.

【図6】本発明の第3の実施の形態の熱電半導体素子の
配線図である。
FIG. 6 is a wiring diagram of a thermoelectric semiconductor element according to a third embodiment of the present invention.

【図7】本発明の第4の実施の形態のパワーモジュール
を示す側断面図である。
FIG. 7 is a side sectional view showing a power module according to a fourth embodiment of the present invention.

【図8】本発明の第4の実施の形態の熱電半導体素子の
配線図である。
FIG. 8 is a wiring diagram of a thermoelectric semiconductor element according to a fourth embodiment of the present invention.

【図9】本発明の第5の実施の形態のパワーモジュール
を示す側断面図である。
FIG. 9 is a side sectional view showing a power module according to a fifth embodiment of the present invention.

【図10】本発明の第5の実施の形態の熱電半導体素子
の配線図である。
FIG. 10 is a wiring diagram of a thermoelectric semiconductor element according to a fifth embodiment of the present invention.

【図11】本発明の第6の実施の形態のパワーモジュー
ルを示す側断面図である。
FIG. 11 is a side sectional view showing a power module according to a sixth embodiment of the present invention.

【図12】本発明の第6の実施の形態の熱電半導体素子
の配線図である。
FIG. 12 is a wiring diagram of a thermoelectric semiconductor element according to a sixth embodiment of the present invention.

【図13】従来の実施装置を示す側断面図である。FIG. 13 is a side sectional view showing a conventional apparatus.

【符号の説明】[Explanation of symbols]

1:パワー半導体素子 1U1 U相上アームのパワー半導体素子 1U2 U相下アームのパワー半導体素子 1V1 V相上アームのパワー半導体素子 1V2 V相下アームのパワー半導体素子 1W1 W相上アームのパワー半導体素子 1W2 W相下アームのパワー半導体素子 2:絶縁回路基板 3:アルミワイヤ 4:制御端子 5:出力端子 6:放熱ベース 7:熱電モジュール 7a 熱電半導体素子 7b 絶縁基板 7c 絶縁基板 7d 端子 7m 熱電素子の領域 7n 熱電素子の領域 7o 熱電素子の領域 7p 熱電素子の領域 7x 熱電素子の領域 7y 熱電素子の領域 7U1 U相上アームの熱電モジュール 7U2 U相下アームの熱電モジュール 7V1 V相上アームの熱電モジュール 7V2 V相下アームの熱電モジュール 7W1 W相上アームの熱電モジュール 7W2 W相下アームの熱電モジュール 1: Power semiconductor element 1U1 U-phase upper arm power semiconductor device 1U2 U phase lower arm power semiconductor device 1V1 V phase upper arm power semiconductor device 1V2 V phase lower arm power semiconductor device 1W1 W phase upper arm power semiconductor device 1W2 W phase lower arm power semiconductor device 2: Insulated circuit board 3: Aluminum wire 4: Control terminal 5: Output terminal 6: Heat dissipation base 7: Thermoelectric module 7a Thermoelectric semiconductor element 7b insulating substrate 7c insulating substrate 7d terminal Area of 7m thermoelectric element 7n Thermoelectric element area 7o Area of thermoelectric element Area of 7p thermoelectric element Area of 7x thermoelectric elements 7y Thermoelectric element area 7U1 U-phase upper arm thermoelectric module 7U2 U-phase lower arm thermoelectric module 7V1 V-phase upper arm thermoelectric module 7V2 V phase lower arm thermoelectric module 7W1 W phase upper arm thermoelectric module 7W2 W phase lower arm thermoelectric module

───────────────────────────────────────────────────── フロントページの続き (72)発明者 石田 雄二 福岡県北九州市八幡西区黒崎城石2番1号 株式会社安川電機内 Fターム(参考) 5F036 AA01 BA33    ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yuji Ishida             2-1, Kurosaki Shiroishi, Hachiman Nishi-ku, Kitakyushu City, Fukuoka Prefecture               Yasukawa Electric Co., Ltd. F-term (reference) 5F036 AA01 BA33

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 複数のパワー半導体素子と放熱ベースと
出力端子と制御端子を備えたパワーモジュールにおい
て、熱電変換する熱電半導体素子に絶縁基板を設けた熱
電モジュールを前記パワー半導体素子の下面に密着若し
くは近接した位置に、前記パワー半導体素子毎に配置し
たことを特徴とする冷却機構付きパワーモジュール。
1. A power module having a plurality of power semiconductor elements, a heat radiation base, an output terminal and a control terminal, wherein a thermoelectric module in which an insulating substrate is provided on a thermoelectric semiconductor element for thermoelectric conversion is adhered to a lower surface of the power semiconductor element or A power module with a cooling mechanism, characterized in that the power semiconductor elements are arranged in close proximity to each other.
【請求項2】 請求項1記載のパワーモジュールにおい
て、前記熱電半導体素子の素子搭載数が異なった熱電モ
ジュールを前記パワー半導体素子に個別に配置したこと
を特徴とする冷却機構付きパワーモジュール。
2. The power module with a cooling mechanism according to claim 1, wherein thermoelectric modules having different numbers of mounted thermoelectric semiconductor elements are individually arranged in the power semiconductor elements.
【請求項3】 複数のパワー半導体素子と放熱ベースと
出力端子と制御端子からなるパワーモジュールにおい
て、熱電変換する熱電半導体素子を絶縁基板上に複数の
領域に分けて配置した熱電モジュールを前記パワー半導
体素子の下面に密着若しくは近接した位置に取り付けた
ことを特徴とする冷却機構付きパワーモジュール。
3. A power module comprising a plurality of power semiconductor elements, a heat dissipation base, an output terminal and a control terminal, wherein the thermoelectric module in which thermoelectric semiconductor elements for thermoelectric conversion are arranged in a plurality of regions on an insulating substrate. A power module with a cooling mechanism, characterized in that the power module is attached to the lower surface of the element or in a position close to the element.
【請求項4】 請求項3記載のパワーモジュールにおい
て、前記熱電半導体素子を配置した複数の領域が前記パ
ワー半導体素子毎に個別に配置されたことを特徴とする
冷却機構付きパワーモジュール。
4. The power module with a cooling mechanism according to claim 3, wherein a plurality of regions in which the thermoelectric semiconductor elements are arranged are individually arranged for each of the power semiconductor elements.
【請求項5】 請求項3又は4記載のパワーモジュール
において、前記熱電半導体素子を配置した複数の領域毎
に素子の搭載数および/又は素子の配置間隔を変えたこ
とを特徴とする冷却機構付きパワーモジュール。
5. The power module according to claim 3, wherein the number of mounted elements and / or the arrangement intervals of the elements are changed for each of a plurality of regions in which the thermoelectric semiconductor elements are arranged. Power module.
【請求項6】 請求項1又は2記載のパワーモジュール
の冷却において、前記パワー半導体の複数個の熱電モジ
ュールを個別に導通して冷却することを特徴とするパワ
ーモジュールの冷却方法。
6. The cooling method for a power module according to claim 1, wherein the plurality of thermoelectric modules of the power semiconductor are individually conducted and cooled.
【請求項7】 請求項3〜5のいずれか1項記載のパワ
ーモジュールの冷却において、前記熱電半導体素子を配
置した複数の領域間を配線により結合し、結合した領域
毎に個別に通電して冷却することを特徴とするパワーモ
ジュールの冷却方法。
7. The cooling of the power module according to claim 3, wherein a plurality of regions in which the thermoelectric semiconductor elements are arranged are connected by wiring, and each of the connected regions is individually energized. A method for cooling a power module, which comprises cooling.
【請求項8】 請求項4記載のパワーモジュールの冷却
において、前記熱電半導体素子を配置した複数の領域毎
に通電し、前記パワー半導体素子を個別に冷却すること
を特徴とするパワーモジュールの冷却方法。
8. The cooling method for a power module according to claim 4, wherein the plurality of regions in which the thermoelectric semiconductor elements are arranged are energized to individually cool the power semiconductor elements. .
JP2001379231A 2001-12-12 2001-12-12 Power module with cooling mechanism and cooling method thereof Expired - Fee Related JP4085236B2 (en)

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US9949414B2 (en) 2016-02-18 2018-04-17 Lsis Co., Ltd. Cooling system for two-dimensional array power converters
CN109314172A (en) * 2016-03-22 2019-02-05 金瑟姆股份有限公司 Distributed heat electric material with non-homogeneous heat transfer characteristic
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