JP2003179065A - Method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the technology to safely eliminate hydrogen in the exhaust gas to be exhausted from the chemical vapor deposition apparatus in the chemical vapor deposition process of semiconductor wafers using hydrogen. <P>SOLUTION: This method of manufacturing a semiconductor integrated circuit device comprises the steps of forming a gate electrode of MOSFET by patterning a conductive film after deposition of the conductive film including at least a metal film on a gate oxide film in the thickness of 5 nm or less formed on the main surface of a semiconductor substrate, improving a profile of the end of side wall of the gate electrode by supplying the hydrogen gas including the vapor generated from hydrogen and oxygen through the effect of catalyst and in the low concentration which enables control of reproducibility in formation of oxide film and uniformity of thickness of the oxide film to the main surface or the proximity thereof of the semiconductor substrate heated up to the predetermined temperature and then selectively oxidizing the main surface of the semiconductor substrate, and removing hydrogen included in the exhaust gas after the oxidation process through reaction with oxygen using the catalyst. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a vapor phase process of a semiconductor wafer using hydrogen gas.

[0002]

In the semiconductor manufacturing process, MOSFETs are used.
(Metal Oxide Semiconductor Field Effect Transisto
The hydrogen annealing treatment for supplying hydrogen to the polycrystalline silicon film or the Si (silicon) substrate forming the gate electrode of r) is performed. To perform hydrogen annealing, hydrogen gas is introduced into a batch-type or single-wafer hydrogen annealing furnace that accommodates semiconductor wafers, and the semiconductor wafers are heat-treated in a hydrogen atmosphere at about 400 ° C. When this hydrogen annealing is performed, S
Since the trap level resulting from the dangling bond (i.e., dangling bond) of i is terminated by hydrogen,
The characteristics of the FET are improved.

Conventionally, the hydrogen gas discharged from the hydrogen annealing furnace is removed by a combustion method. This is a system in which air is introduced into the exhaust system of a hydrogen annealing device and hydrogen is burned by a spark ignition system to be converted into water. In a relatively small-scale hydrogen annealing furnace, the exhausted hydrogen may be diluted with a large amount of nitrogen gas or air and released into the atmosphere.

On the other hand, in the process of forming a MOSFET on a Si substrate, the Si substrate is wet-oxidized to form a gate oxide film on its surface. At that time as well, hydrogen is burned in an oxygen atmosphere. A combustion method is used in which water is generated and the water is supplied to the surface of a semiconductor wafer together with oxygen.

As a method for producing a water / oxygen mixed gas used for wet oxidation of a Si substrate, a catalyst method is known in addition to the above combustion method. For example, in Japanese Unexamined Patent Publication No. 5-1522282, the inner surface of the hydrogen gas introducing pipe is Ni (nickel) or N.
Disclosed is a thermal oxidation device formed of an i-containing material and provided with means for heating a hydrogen gas introduction pipe. This thermal oxidizer uses N in a hydrogen gas introduction pipe heated to 300 ° C or higher.
Hydrogen is brought into contact with i (or a Ni-containing material) to generate hydrogen active species, and the hydrogen active species is reacted with oxygen (or a gas containing oxygen) to generate water.

Further, in the process of forming the gate electrode on the gate oxide film formed by the wet oxidation method as described above, the gate electrode material deposited on the gate oxide film is patterned by dry etching and then used as an etching mask. The used photoresist is removed by ashing (ashing), and an etching solution such as hydrofluoric acid is used to remove dry etching residues and ashing residues remaining on the substrate surface.

When the above wet etching is performed, the gate oxide film in the region other than the lower portion of the gate electrode is removed, and at the same time, the gate oxide film at the side wall end portion of the gate electrode is isotropically etched to cause an undercut. As a result, the breakdown voltage of the gate electrode is lowered as it is. Therefore, in order to improve the profile of the undercut gate electrode sidewall end portion, so-called light oxidation treatment is performed in which the substrate is again thermally oxidized to form an oxide film.

However, if the above-mentioned light oxidation treatment is applied to the gate electrode having a polymetal structure containing a refractory metal such as W (tungsten) or Mo (molybdenum) which is easily oxidized in a high-temperature oxygen atmosphere, the refractory metal is applied. The film is oxidized to increase its resistance value, or a part thereof is peeled off from the substrate. Therefore, in the gate processing process using polymetal, it is necessary to take measures to prevent the refractory metal film from being oxidized during the light oxidation process.

Japanese Unexamined Patent Publication No. 59-132136 discloses Si.
After forming a gate electrode having a polymetal structure including a W film or a Mo film on a substrate and performing light oxidation in a mixed atmosphere of water vapor and hydrogen, only Si is selected without oxidizing the W (Mo) film. The technique of selective oxidation is disclosed.

This utilizes the fact that the steam / hydrogen partial pressure ratio at which the redox reaction is in equilibrium differs between W (Mo) and Si, and this partial pressure ratio is oxidized by steam to W (Mo). Is rapidly reduced by the coexisting hydrogen, but Si is selectively oxidized by setting it in a range such that it remains oxidized. A mixed atmosphere of water vapor and hydrogen is generated by a bubbling method in which hydrogen gas is supplied into pure water contained in a container, and the steam / hydrogen partial pressure ratio is controlled by changing the temperature of pure water.

In the light oxidation process described in the above publication, since the Si substrate is oxidized by using the steam / hydrogen mixed gas, hydrogen gas is contained in the exhaust gas discharged from the oxidation furnace. Therefore, also in this case, some measure for removing the hydrogen gas in the exhaust gas is required.

[0012] As an exhaust gas removing method other than the above used in the semiconductor manufacturing process, there is disclosed in Japanese Unexamined Patent Publication No. 8-83772.
The one described in Japanese Patent Publication is known. This is a CVD
(Chemical Vapor Deposition) A device that oxidizes and decomposes tetraethoxysilane by introducing exhaust gas containing tetraethoxysilane discharged from a device to an adsorption tower and bringing it into contact with a metal oxide catalyst (or an adsorbent carrying it) Is. NiO, Cu as the metal oxide catalyst
O, Mn ₂ O ₃ , Fe ₂ O ₃ or the like is used.

[0013]

In the above-described hydrogen annealing process for semiconductor wafers, in order to remove the hydrogen gas discharged from the hydrogen annealing furnace by the combustion method, air is sufficiently flowed in the exhaust system before ignition. There is a need. Therefore, when the amount of hydrogen gas becomes small, such as when switching between hydrogen gas and purge gas, the flame is likely to extinguish, and unburned hydrogen may be discharged as it is to the outside. However, since the hydrogen annealing treatment is performed at a high temperature of about 400 ° C., there is a danger of explosion if unburned hydrogen is contained in the high-temperature exhaust gas. Further, the method of removing hydrogen gas by the combustion method has a problem that the scale of the apparatus for removing harm increases.

On the other hand, in the detoxification method of diluting the hydrogen gas discharged from the hydrogen annealing furnace with a large amount of nitrogen gas or air and discharging it into the atmosphere, it is necessary to reduce the hydrogen gas concentration to about several percent as a safety measure. Since a large amount of diluting gas is used, there is a problem that the scale of the detoxification device becomes large as in the case of the combustion system, and it is not suitable for detoxifying a large amount of hydrogen gas.

An object of the present invention is to provide a technique for safely removing hydrogen in exhaust gas discharged from a gas phase processing apparatus in a gas phase processing process for a semiconductor wafer using a processing gas containing hydrogen. Especially.

Another object of the present invention is to provide a technique for efficiently detoxifying hydrogen in exhaust gas discharged from a gas phase processing apparatus in a process of gas phase processing a semiconductor wafer using a processing gas containing hydrogen. To provide.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0018]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a conductive film containing at least a metal film is deposited on a gate oxide film having a film thickness of 5 nm or less formed on a main surface of a semiconductor substrate, and then the conductive film is formed. And a low-concentration water vapor that is generated from hydrogen and oxygen by a catalytic action and that can control the reproducibility of oxide film formation and the uniformity of oxide film thickness. Is supplied to or near the main surface of the semiconductor substrate heated to a predetermined temperature, and the main surface of the semiconductor substrate is selectively oxidized to change the profile of the side wall end portion of the gate electrode. It includes a step of improving and a step of reacting hydrogen contained in exhaust gas after oxidation treatment with oxygen by a catalyst to remove harm.

The method of manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of forming a single layer or a plurality of layers of wiring on the main surface of a semiconductor substrate and then depositing a passivation film on the uppermost wiring. In the middle of the step of depositing the film or before and after the step of depositing, a step of terminating the dangling bonds of Si with hydrogen by heat-treating the semiconductor substrate in a gas atmosphere containing hydrogen, and the exhaust gas after the heat-treatment. And a step of reacting the contained hydrogen with oxygen by a catalyst to remove harm.

The outline of the invention of the present application other than the above is as follows. (1) A method of manufacturing a semiconductor integrated circuit device according to the present invention comprises a step of vapor-treating a semiconductor wafer using a treatment gas containing hydrogen, and hydrogen contained in the exhaust gas after the vapor-phase treatment to oxygen by a catalyst. And reacting to remove harm. (2) In the method for manufacturing a semiconductor integrated circuit device of the present invention, the hydrogen abatement part for abatement of hydrogen contained in the exhaust gas is provided in an exhaust system of a vapor phase treatment part for vapor phase treating the semiconductor wafer. There is. (3) In the method for manufacturing a semiconductor integrated circuit device of the present invention, the hydrogen abatement part is provided for each exhaust system of the vapor phase processing part. (4) In the method for manufacturing a semiconductor integrated circuit device of the present invention, the hydrogen abatement part is provided in a ratio of one in the exhaust system of the plurality of gas phase processing parts. (5) In the method for manufacturing a semiconductor integrated circuit device of the present invention, the treatment for removing the hydrogen contained in the exhaust gas is performed by a single-wafer treatment or a batch treatment. (6) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, a conductive film containing at least a metal film is deposited on a gate oxide film formed on a main surface of a semiconductor substrate, and then the conductive film is patterned to form a MOSFET. A step of forming a gate electrode, and supplying hydrogen gas containing water vapor generated from hydrogen and oxygen by a catalytic action to the main surface of the semiconductor substrate heated to a predetermined temperature or the vicinity thereof, and the main surface of the semiconductor substrate Selectively improving the profile of the end portion of the side wall of the gate electrode by selective oxidation, and reacting hydrogen contained in the exhaust gas after the oxidation treatment with oxygen by a catalyst to remove harm. . (7) In the method for manufacturing a semiconductor integrated circuit device of the present invention, the steam / hydrogen partial pressure ratio of the hydrogen gas containing steam is set within a range in which the metal film is reduced and the main surface of the semiconductor substrate is oxidized. To do. (8) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the conductive film contains at least a Ti film, and hydrogen gas containing water vapor at a low concentration such that deterioration of the gate electrode due to oxidation of the Ti film is minimized. Is used to selectively oxidize the main surface of the semiconductor substrate. (9) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the conductive film includes at least a W film, and hydrogen gas containing a low concentration of water vapor is used so that the oxidation rate and the oxide film thickness can be controlled. The main surface of the semiconductor substrate is selectively oxidized. (10) In the method for manufacturing a semiconductor integrated circuit device of the present invention, the conductive film forming the gate electrode is a polycrystalline silicon film, a metal nitride film deposited on the polycrystalline silicon film, and the metal nitride film. And a metal film deposited on top of the. (11) In the method for manufacturing a semiconductor integrated circuit device of the present invention, the metal nitride film is made of WN or TiN, and the metal film is made of W, Mo or Ti.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is an equivalent circuit diagram of the DRAM of this embodiment. As shown in the figure, the memory array (MARY) of this DRAM has a plurality of word lines WL (WLn-1, WLn, WLn + 1 ...) Arranged in a matrix and a plurality of bit lines BL at their intersections. And a plurality of arranged memory cells (MC). One memory cell for storing 1-bit information is one information storage capacitive element C and one memory cell selection M connected in series with it.
One of the source and the drain of the memory cell selection MISFET Qs is electrically connected to the information storage capacitive element C, and the other is a bit line B.
It is electrically connected to L. One end of the word line WL is connected to the word driver WD, and the bit line BL is
One end thereof is connected to the sense amplifier SA.

A method of manufacturing the DRAM of this embodiment will be described below with reference to FIGS. 2 to 8 and 14 to 27 are cross-sectional views of the semiconductor substrate showing each part of the memory array (MARY) and the peripheral circuit (for example, the sense amplifier SA), and FIGS. 9 and 10 show the light oxidation process. FIG. 11 is a schematic view of a single-wafer oxidation furnace used, FIG. 11 is a schematic view of a catalytic steam / hydrogen mixed gas generation device and a hydrogen gas detoxification device connected to a chamber of the oxidation furnace, and FIG. 12 is steam / hydrogen. FIG. 13 is a graph showing the temperature dependence of the equilibrium vapor pressure ratio of the redox reaction using a mixed gas, FIG. 13 is a diagram showing the sequence of the light oxidation process, and FIG. 28 is a batch type vertical hydrogen annealing furnace and a catalyst connected thereto. FIG. 29 is a schematic diagram of a hydrogen gas abatement system of the type, and FIG. 29 is a diagram showing a sequence of a hydrogen annealing process. It should be noted that in the following description, the numerical values indicating the thickness of the thin film and the like are merely examples and are not intended to limit the present invention.

First, as shown in FIG. 2, the specific resistance is 10Ω.
A semiconductor substrate 1 made of single crystal silicon having a thickness of about cm is heat-treated to form a thin silicon oxide film 2 having a thickness of about 10 nm on its main surface.
(Pad oxide film) is formed, and then a silicon nitride film 3 having a film thickness of about 100 nm is formed on the silicon oxide film 2 by CVD (C
After the deposition by the chemical vapor deposition method, the silicon nitride film 3 in the element isolation region is removed by etching using the photoresist film as a mask. The silicon oxide film 2 is formed for the purpose of relieving stress applied to the substrate when sintering (baking) the silicon oxide film embedded in the element isolation trench in a later step. Since the silicon nitride film 3 has a property of being hard to be oxidized, it is used as a mask for preventing the oxidation of the substrate surface below it (active region).

Next, as shown in FIG. 3, the silicon oxide film 2 and the semiconductor substrate 1 are dry-etched by using the silicon nitride film 3 as a mask, and the semiconductor substrate 1 in the element isolation region has a depth of 300 to 400 nm. A groove 4a of a certain degree is formed.

Next, as shown in FIG. 4, in order to remove the damaged layer formed on the inner wall of the groove 4a by the etching,
After heat-treating the semiconductor substrate 1 to form a silicon oxide film 5 with a film thickness of about 10 nm on the inner wall of the groove 4a, a silicon oxide film 6 is deposited on the semiconductor substrate 1 by the CVD method, and then the film quality of the silicon oxide film 6 is changed. For improvement, the semiconductor substrate 1 is heat-treated to densify the silicon oxide film 6. After that, the silicon oxide film 6 is polished by the chemical mechanical polishing (CMP) method using the silicon nitride film 3 as a stopper and left inside the groove 4a to form the element isolation groove 4.

Next, after the silicon nitride film 3 remaining on the semiconductor substrate 1 is removed by wet etching using hot phosphoric acid, as shown in FIG. The p-type well 7 is formed by ion-implanting B (boron) in the region where the array) and a part of the peripheral circuit (n-channel type MISFETQn) are formed, and another part of the peripheral circuit (p-channel type MISFETQp) is formed. P (phosphorus) is ion-implanted in the region to be formed to form the n-type well 8.

Next, as shown in FIG. 6, the silicon oxide film 2 on each surface of the p-type well 7 and the n-type well 8 is subjected to HF.
After removing with a (hydrofluoric acid) -based cleaning liquid, the semiconductor substrate 1 is wet-oxidized to form the p-type well 7 and the n-type well 8.
A clean gate oxide film 9 having a film thickness of about 5 nm is formed on each surface of the.

Although not particularly limited, after the gate oxide film 9 is formed, the semiconductor substrate 1 is heat-treated in an NO (nitrogen oxide) or N ₂ O (nitrous oxide) atmosphere to form the gate oxide film 9 Oxynitriding treatment for segregating nitrogen may be performed on the interface with the semiconductor substrate 1. When the gate oxide film 9 is thinned to about 5 nm, the strain generated at the interface between the two becomes apparent due to the difference in thermal expansion coefficient from the semiconductor substrate 1,
Induces the generation of hot carriers. Nitrogen segregated at the interface with the semiconductor substrate 1 alleviates this strain, so the above oxynitriding treatment can improve the reliability of the ultrathin gate oxide film 9.

Next, as shown in FIG. 7, the gate oxide film 9 is formed.
On top of the gate electrode 14 with a gate length of about 0.25 μm
A (word line WL) and gate electrodes 14B and 14C are formed. The gate electrode 14A (word line WL) and the gate electrodes 14B and 14C are, for example, n such as P (phosphorus).
A polycrystalline silicon film 10 having a film thickness of about 70 nm doped with type impurities is deposited on the semiconductor substrate 1 by a CVD method, and then a WN film 11 having a film thickness of about 30 nm and a film thickness of 100 nm are formed on the polycrystalline silicon film 10.
And a W film 12 having a thickness of about 150 nm are deposited on the W film 12 by a sputtering method.
After deposition by the VD method, these films are formed by patterning these films using a photoresist as a mask.

When a part of the gate electrode 14A (word line WL) is made of a low resistance metal (W), its sheet resistance can be reduced to about 2Ω / □, so that the word line delay should be reduced. You can Further, since the word line delay can be reduced without lining the gate electrode 14 (word line WL) with Al wiring or the like, the number of wiring layers formed above the memory cell can be reduced by one layer.

After that, the photoresist is removed by ashing (ashing), and an etching solution such as hydrofluoric acid is used to remove the dry etching residue and the ashing residue left on the surface of the semiconductor substrate 1. When this wet etching is performed, as shown in FIG.
(The word line WL) (and the gate electrodes 14B and 14C not shown in the figure) are removed at the same time as the gate oxide film 9 in a region other than the lower part, and at the same time, the gate oxide film 9 below the gate sidewall is isotropically etched. As a result, an undercut occurs, which causes a problem such as a decrease in withstand voltage of the gate oxide film 9 as it is. Therefore, in order to regenerate the scraped gate oxide film 9, reoxidation (light oxidation) treatment is performed by the following method.

FIG. 9 (a) is a schematic plan view showing an example of a concrete structure of a single-wafer oxidation furnace used for light oxidation treatment,
FIG. 9B is a sectional view taken along the line BB ′ of FIG.

The single-wafer oxidation furnace 100 is provided with a chamber 101 composed of a multi-wall quartz tube, and a heater 102 for heating the semiconductor wafer 1A is provided at the upper and lower parts thereof.
a and 102b are installed. Inside the chamber 101, there is housed a disc-shaped heat equalizing ring 103 that evenly disperses the heat supplied from the heaters 102a and 102b over the entire surface of the semiconductor wafer 1A, and the semiconductor wafer 1A is held horizontally above it. A susceptor 104 is placed. The soaking ring 103 is made of a heat resistant material such as quartz or SiC (silicon carbide),
01 is supported by a support arm 105 extending from the wall surface. The susceptor 10 is provided near the soaking ring 103.
A thermocouple 106 for measuring the temperature of the semiconductor wafer 1A held by the No. 4 is installed. The semiconductor wafer 1A may be heated by a heater 107a, 102b or a lamp 107 as shown in FIG.

One end of a gas introduction pipe 108 for introducing the steam / hydrogen mixed gas and the purge gas into the chamber 101 is connected to a part of the wall surface of the chamber 101. To the other end of the gas introduction pipe 108, a catalyst-type gas generator described later is connected. Gas introduction pipe 108
A partition 110 having a large number of through holes 109 is provided in the vicinity of, and the gas introduced into the chamber 101 passes through the through holes 109 of the partition 110 and spreads evenly into the chamber 101. One end of an exhaust pipe 111 for exhausting the gas introduced into the chamber 101 is connected to the other part of the wall surface of the chamber 101, and the other end of the exhaust pipe 111 is formed of a catalyst system described later. Gas abatement device is connected.

FIG. 11 shows a catalytic steam / hydrogen mixed gas generator 14 connected to the single-wafer oxidation furnace 100.
2 is a schematic diagram showing 0 and a hydrogen gas abatement device 150. FIG.

The steam / hydrogen mixed gas generator 140 is
Heat and corrosion resistant alloys (for example, trade name "Hastello (Hastello
y) ”, such as a Ni alloy), and a coil 141 made of a catalytic metal such as Pt (platinum), Ni (nickel), or Pd (palladium) and a reactor 141a. Coil 142
And a heater 143 for heating.

In the reactor 141a of the gas generator 140, hydrogen gas, oxygen gas, and purge gas composed of an inert gas such as nitrogen or Ar (argon) are respectively supplied from the gas storage tanks 144a, 144b, 144c to the pipe 1
Introduced through 45. Gas storage tank 144a, 144
b, 144c and the pipe 145, mass flow controllers 146a, 146b, 146 for adjusting the gas amount.
c and open / close valves 147a, 147a for opening and closing the gas flow path
7b and 147c are installed, and the amount and composition ratio of the gas introduced into the reactor 141a are precisely controlled by these.

The hydrogen gas and oxygen gas introduced into the reactor 141a come into contact with the coil 142 heated to about 350 to 450 ° C. to be excited, and hydrogen radicals are generated from hydrogen molecules (H ₂ → 2H). *), Oxygen radicals are generated from oxygen molecules (O ₂ → 2O ^* ). Since these two types of radicals are chemically extremely active, they rapidly react to generate water (steam) (2H ^* + O ^* → H ₂ O). Therefore, a hydrogen / oxygen mixed gas containing hydrogen in excess of the molar ratio (hydrogen: oxygen = 2: 1) produced by water is supplied to the reactor 141.
By introducing into a, a steam / hydrogen mixed gas can be generated. The generated steam / hydrogen mixed gas is introduced into the chamber 101 of the oxidation furnace 100 through the gas introduction pipe 108.

The catalytic gas generator 14 as described above
Since 0 can control the amounts of hydrogen and oxygen involved in the generation of water and their ratio with high accuracy, the water vapor concentration in the water vapor / hydrogen mixed gas introduced into the chamber 101 can be reduced from an extremely low concentration on the order of ppm to a few. Wide range up to high concentration of about 10%,
And it can be controlled with high accuracy. In addition, the reactor 14
Since water is instantly generated when the process gas is introduced into 1a, a steam / hydrogen mixed gas having a desired steam concentration can be obtained in real time. Further, as a result, contamination of foreign matter can be suppressed to a minimum, so that a clean water vapor / hydrogen mixed gas can be introduced into the chamber 101. In addition,
The catalyst metal in the reactor 141a is not limited to the above-mentioned metals as long as it can convert hydrogen and oxygen into radicals. Further, the catalytic metal may be processed into a coil shape for use, or may be processed into, for example, a hollow tube or a fine fiber filter and the process gas may be passed through the inside thereof.

FIG. 12 is a graph showing the temperature dependence of the equilibrium vapor pressure ratio (PH ₂ O / PH ₂ ) of the redox reaction using a steam / hydrogen mixed gas, and the curves (a) to (e) in the graph are shown. )
Are W, Mo, Ta (tantalum), Si and Ti, respectively.
Shows the equilibrium vapor pressure ratio of.

As shown, chamber 1 of oxidation furnace 100
By setting the water vapor / hydrogen partial pressure ratio of the water vapor / hydrogen mixed gas introduced into 01 within the range of the region between the curve (a) and the curve (d), the gate electrode 14A (word line WL) and the gate It is possible to selectively oxidize only Si without oxidizing the W film 12 that constitutes a part of the electrodes 14B and 14C and the WN film 11 that is a barrier layer. Further, as shown in the figure, metal (W, Mo, Ta, T
In both i) and Si, the oxidation rate becomes slower as the water vapor concentration in the water vapor / hydrogen mixed gas becomes lower. Therefore,
By lowering the water vapor concentration in the water vapor / hydrogen mixed gas, it becomes easy to control the oxidation rate of Si and the oxide film thickness.

Similarly, when a part of the gate electrode is composed of a Mo film, by setting the water vapor / hydrogen partial pressure ratio within the range between the curve (b) and the curve (d). , Si can be selectively oxidized without oxidizing the Mo film. Further, when a part of the gate electrode is made of a Ta film, the steam / hydrogen partial pressure ratio is changed to the curve (c).
By setting it within the range of the region sandwiched by the curve (d) and Si, it is possible to selectively oxidize only Si without oxidizing the Ta film.

On the other hand, as shown in the figure, since Ti has a higher oxidation rate than Si in the steam / hydrogen mixed gas atmosphere,
Part of the gate electrode is composed of a Ti film, or the barrier layer is made of T
In the case of being composed of an iN film, Si alone cannot be selectively oxidized without oxidizing the Ti film or the TiN film. However, also in this case, by setting the water vapor in the water vapor / hydrogen mixed gas to an extremely low concentration, Ti
Since the oxidation rate and the oxide film thickness of the film, TiN film and Si can be easily controlled, the oxidation of the Ti film and the TiN film can be minimized and the deterioration of the characteristics of the gate electrode is not a problem in practical use. Can be suppressed. Specifically, it is desirable to set the upper limit of the water vapor concentration to about 1% or less, and since a certain amount of water vapor is required to improve the profile of the end portion of the gate electrode side wall, the lower limit is 10%.
It is desirable to set it to about ppm to 100 ppm.

The water vapor / hydrogen mixed gas introduced into the chamber 101 of the oxidation furnace 100 is passed through the exhaust pipe 111 after the light oxidation treatment of the semiconductor wafer 1A is completed.
It is introduced into the reactor 141b of the hydrogen gas abatement system 150 shown in FIG. At this time, the gas storage tank 1 is connected through the pipe 151.
Oxygen gas is supplied into the exhaust pipe 111 from 44a and is introduced into the reactor 141b together with the steam / hydrogen mixed gas. A mass flow controller 146d that adjusts the amount of oxygen gas and an opening / closing valve 147d that opens and closes the flow path of oxygen gas are installed between the gas storage tank 144a and the pipe 151. The quantity is precisely controlled by these. In addition, in the middle of the exhaust pipe 111, the oxygen gas flows into the chamber 101 of the oxidation furnace 100.
A check valve 152 is provided to prevent back flow into the.

Reactor 141b of hydrogen gas abatement system 150
Is similar to the reactor 141a of the gas generator 140,
A coil 142 made of a heat resistant and corrosion resistant alloy, and made of a catalytic metal such as Pt, Ni, or Pd, and a heater 143 for heating the coil 142 are housed inside. The water vapor / hydrogen mixed gas and oxygen gas introduced into the reactor 141b are excited by being contacted with the coil 142 heated to about 350 to 450 ° C., and are generated from hydrogen radicals generated from hydrogen molecules and oxygen molecules. It rapidly reacts with oxygen radicals to produce water (steam).

Therefore, when the steam / hydrogen mixed gas discharged from the oxidation furnace 100 is introduced into the reactor 141b, at least 1/2 or more (molar ratio) oxygen of the amount of hydrogen in this mixed gas is simultaneously introduced. As a result, hydrogen gas can be completely oxidized and converted into water. This oxygen gas is added to the reactor 1 prior to the introduction of the steam / hydrogen mixed gas.
It may be introduced into 41b, or the pipe 151
It is also possible to constantly keep flowing into the reactor 141b through the exhaust pipe 111. The water (steam) generated in the reactor 141b is discharged to the outside through the exhaust pipe 153 together with the excess oxygen gas. In the middle of the exhaust pipe 153, a hydrogen gas sensor 154 for confirming whether or not the hydrogen gas is completely converted to water, and a cooler 155 for liquefying the discharged high temperature steam are provided. There is.

Next, an example of the light oxidation process sequence using the oxidation furnace 100 will be described with reference to FIG.

First, the chamber 101 of the oxidation furnace 100 is opened, and the semiconductor wafer 1A is loaded on the susceptor 104 while introducing a purge gas (nitrogen) into the chamber 101. After that, the chamber 101 is closed, and the purge gas is continuously introduced to sufficiently exchange the gas in the chamber 101. The susceptor 104 is previously heated by the heaters 102a and 102b so that the semiconductor wafer 1A can be heated quickly. The heating temperature of the semiconductor wafer 1A is 800 to 90.
The range is 0 ° C., for example, 850 ° C. Wafer temperature is 80
At 0 ° C or lower, the quality of the silicon oxide film deteriorates. On the other hand,
If the temperature is 900 ° C. or higher, the surface of the wafer tends to be rough.

Next, hydrogen is introduced into the chamber 101 and nitrogen is discharged. If nitrogen remains in the chamber 101, an undesired nitriding reaction may occur, so it is desirable to completely discharge nitrogen.

Next, the reactor 141 of the gas generator 140
Oxygen and excess hydrogen are introduced into the chamber, and the water produced from the oxygen and hydrogen by the catalytic action is introduced into the chamber 1 together with the excess hydrogen.
01, and the surface of the semiconductor wafer 1A is oxidized for a predetermined time. As a result, the gate oxide film 9 that has been thinned by the wet etching is re-oxidized, and the profile of the side walls of the undercut gate electrode 14A (word line WL) and the gate electrodes 14B and 14C is improved. .

When the above-mentioned light oxidation is carried out for a long time, the oxide film thickness near the end of the gate electrode becomes thicker than necessary, an offset occurs at the end of the gate electrode, and the threshold voltage (Vth) of the MOSFET is designed. It deviates from the value. There is also a problem that the effective channel length becomes shorter than the processed value of the gate electrode. In particular, in a fine MOSFET having a gate length of about 0.25 μm, the allowance of the gate processing dimension from the design value is severely limited in terms of device design. This is because the threshold voltage sharply decreases due to the short channel effect even if the amount of thinning is slightly increased. In the case of a gate electrode having a gate length of about 0.25 μm, the side wall edge of the polycrystalline silicon film forming a part thereof is oxidized by about 0.1 μm (about 0.2 μm at both ends) in the light oxidation process. It is considered to be the limit at which the threshold voltage does not decrease sharply. Therefore, it is desirable that the upper limit of the oxide film thickness grown by light oxidation is about 50% of the gate oxide film thickness.

Next, after introducing a purge gas (nitrogen) into the chamber 101 and discharging the unnecessary steam / hydrogen mixed gas through the exhaust pipe 111, the chamber 101 is opened and the purge gas is introduced into the chamber 101. The semiconductor wafer 1A is unloaded from the susceptor 104.

On the other hand, the water vapor / hydrogen mixed gas discharged from the chamber 101, together with the oxygen gas supplied through the pipe 151, the reactor 141b of the hydrogen gas abatement device 150.
And hydrogen gas and oxygen gas in the mixed gas are converted into water (steam) by a catalytic action. This water vapor is
The excess oxygen gas is forcedly exhausted through the exhaust pipe 153 and liquefied by the cooler 155. After that, the oxygen gas is exhausted to the outside through the exhaust duct, and the water is drained through the drain.

Instead of using hydrogen gas to oxidize hydrogen gas, dry air may be used to oxidize hydrogen gas. In this case, in consideration of the oxygen content in the air (about 21%), dry air containing oxygen at least ½ of the amount of hydrogen in the steam / hydrogen mixed gas (molar ratio) is introduced into the reactor 141b. By doing so, hydrogen gas can be completely converted into water.

Next, the DRAM process after the light oxidation process will be described. First, as shown in FIG. 14, p-type impurity into the n-type well 8, for example, B (boron) on both sides of the n-type well 8 ion implantation to the gate electrode 14C p ^-
The type semiconductor region 16 is formed. In addition, in the p-type well 7, n
Type impurities such as P (phosphorus) are ion-implanted to form n ⁻ type semiconductor regions 17 in the p type wells 7 on both sides of the gate electrode 14B, and the p type wells 7 on both sides of the gate electrode 14A.
Then, the n-type semiconductor region 18 is formed.

Next, as shown in FIG. 15, the semiconductor substrate 1
After depositing a silicon nitride film 19 on the upper surface by the CVD method, FIG.
6, the memory array is provided with a photoresist film 20.
Then, the silicon nitride film 19 of the peripheral circuit is anisotropically etched to form sidewall spacers 19a on the sidewalls of the gate electrodes 14B and 14C. This etching is performed by the silicon oxide film 6 embedded in the element isolation trench 4 and the silicon nitride film 19 on the gate electrodes 14B and 14C.
In order to minimize the amount of shavings, the amount of over-etching is kept to a necessary minimum, and an etching gas that allows a large selection ratio with respect to the silicon oxide film 6 is used.

Next, as shown in FIG. 17, p of the peripheral circuit is
An n type impurity such as As (arsenic) is ion-implanted into the well 7 to form an n ⁺ type semiconductor region 21 (source, drain) of the n channel MISFET Qn, and a p type impurity such as B ( Boron) is ion-implanted to form the p ⁺ type semiconductor region 22 (source, drain) of the p-channel type MISFET Qp.

Next, as shown in FIG. 18, the semiconductor substrate 1
A silicon oxide film 23 is deposited on the upper surface of the n-type semiconductor region 18 of the memory cell selection MISFET Qs by dry etching using a photoresist film 24 as a mask, after depositing a silicon oxide film 23 by a chemical mechanical polishing method. The silicon oxide film 23 above the (source, drain) is removed. This etching is performed under the condition that the etching rate of the silicon oxide film 23 with respect to the silicon nitride films 13 and 19 is increased so that the silicon nitride film 19 on the n-type semiconductor region 18 is not removed.

Then, as shown in FIG. 19, the silicon nitride film 19 and the gate oxide on the n-type semiconductor region 18 (source, drain) of the memory cell selection MISFET Qs are dry-etched by dry etching using the photoresist film 24 as a mask. By removing the film 9, the contact hole 2 is formed on one of the source and the drain (n-type semiconductor region 18).
5 is formed, and the contact hole 26 is formed on the other (n-type semiconductor region 18). This etching keeps the amount of over-etching to a necessary minimum in order to minimize the amount of abrasion of the semiconductor substrate 1.
An etching gas that allows a large selection ratio with respect to (silicon) is used. Further, this etching is performed under the condition that the silicon nitride film 19 is anisotropically etched so that the silicon nitride film 19 remains on the side wall of the gate electrode 14A (word line WL). In this way, the contact holes 25 and 26 are formed in self alignment with the gate electrode 14A (word line WL). The contact holes 25 and 26 are connected to the gate electrode 14A (word line WL).
In order to form the gate electrode 14A in a self-aligned manner, the silicon nitride film 19 is anisotropically etched in advance.
A side wall spacer may be formed on the side wall of the (word line WL).

Next, as shown in FIG. 20, after the plug 27 is buried in the contact holes 25 and 26, the silicon oxide film 2 is formed on the silicon oxide film 23 by the CVD method.
8 is deposited, and then the silicon oxide film 28 on the contact hole 25 is removed by dry etching using the photoresist film 29 as a mask. Contact hole 25,
To embed the plug 27 in the inside of 26, a polycrystalline silicon film doped with P (phosphorus) is deposited on the silicon oxide film 23 by the CVD method, and then the polycrystalline silicon film is polished by the chemical mechanical polishing method. Then, the polycrystalline silicon film on the silicon oxide film 23 is removed. A part of P (phosphorus) in the polycrystalline silicon film diffuses from the bottoms of the contact holes 25 and 26 to the n-type semiconductor region 18 (source, drain) in a high temperature process to be performed later, and lowers the n-type semiconductor region 18. To resist.

Next, as shown in FIG. 21, the peripheral circuit type silicon oxide films 28 and 23 and the gate oxide film 9 are removed by dry etching using the photoresist film 30 as a mask, whereby the n-channel type MISFETQn is formed. Of the p-channel MISF by forming contact holes 31 and 32 on the source and drain (n ⁺ type semiconductor region 21) of
Source and drain of ETQp (p ⁺ type semiconductor region 22)
Contact holes 33 and 34 are formed in the upper part of the. This etching is performed under the condition that the etching rate of the silicon oxide film with respect to the silicon nitride film 13 and the sidewall spacer 19a is increased, the contact holes 31 and 32 are formed in self-alignment with the gate electrode 14B, and the contact hole 33 is formed. , 34 to the gate electrode 14C
Self-aligned with.

Next, as shown in FIG. 22, the bit line BL and the first layer wiring 3 of the peripheral circuit are formed on the silicon oxide film 28.
5 and 36 are formed. For the bit line BL and the first layer wirings 35 and 36, for example, a TiN film and a W film are deposited on the silicon oxide film 28 by the sputtering method, and then a silicon oxide film 37 is deposited on the W film by the CVD method. After that, these films are sequentially patterned and formed by etching using the photoresist film as a mask.

Next, as shown in FIG. 23, the bit line BL
And a silicon oxide film 38 is deposited on the first layer wirings 35 and 36 by the CVD method, and the silicon oxide films 38 and 28 above the contact holes 26 are removed by dry etching using a photoresist film as a mask to form through holes. After forming the plug 39, the plug 40 is placed inside the through hole 39.
Embed. The plug 40 is, for example, a silicon oxide film 38.
After depositing a W film on top of the
The film is formed by polishing the film by a chemical mechanical polishing method and leaving it inside the through hole 39.

Next, as shown in FIG. 24, an information storage capacitive element C having a laminated structure of a lower electrode 41, a capacitive insulating film 42 and an upper electrode 43 is formed on the through hole 39. , MISFETQ for memory cell selection
A memory cell of a DRAM including s and an information storage capacitive element C connected in series to this is substantially completed. The lower electrode 41 of the information storage capacitor C is formed, for example, by depositing a W film on the silicon oxide film 38 by a CVD method or a sputtering method and patterning the W film by dry etching using a photoresist film as a mask. To do. The capacitive insulating film 42 and the upper electrode 43 are formed on the lower electrode 41 by CV.
A tantalum oxide film is deposited by the D method or the sputtering method, a TiN film is deposited on the tantalum oxide film by the sputtering method, and then these films are sequentially patterned by etching using the photoresist film as a mask.

Then, as shown in FIG. 25, a silicon oxide film 44 is deposited on the information storage capacitive element C by a CVD method, and then dry etching is performed using a photoresist film as a mask to perform the information storage capacitive element C. After the through holes 45 and 46 are formed in the upper part of the above and the first layer wiring 35 of the peripheral circuit, the plug 47 is embedded in the through holes 45 and 46. For the plug 47, for example, a W film is deposited on the silicon oxide film 44 by a sputtering method, and then the W film is polished by a chemical mechanical polishing method to form through holes 45, 46.
It is formed by leaving it inside. Next, a TiN film, an Al (aluminum) film, and a TiN film are sequentially deposited on the silicon oxide film 44 by a sputtering method, and then these films are patterned by dry etching using a photoresist film as a mask. 2-layer wiring 48-
51 is formed.

Next, as shown in FIG. 26, the second layer wiring 4
8 to 51, a silicon oxide film 52 is deposited by the CVD method, and then a through hole 53 is formed above the second layer wiring 51 by dry etching using a photoresist film as a mask. The plug 54 is embedded. The plug 54 is formed, for example, by depositing a W film on the silicon oxide film 53 by a sputtering method, and then polishing the W film by a chemical mechanical polishing method and leaving it inside the through hole 53. Next, a TiN film, an Al film, and a TiN film are formed on the silicon oxide film 52 by a sputtering method.
After sequentially depositing the films, the third layer wiring 55 is formed by patterning these films by dry etching using the photoresist film as a mask.

Next, as shown in FIG. 27, the third layer wiring 5
A passivation film 56 is deposited on the upper part of 5. The passivation film 56 is composed of, for example, a silicon oxide film and a silicon nitride film deposited by the CVD method.

Next, the gate electrode 14A (word line WL)
28. In order to supply hydrogen to the polycrystalline silicon film and the Si (silicon) substrate forming part of the gate electrodes 14B and 14C, the batch type vertical hydrogen annealing furnace 16 shown in FIG.
0 is used to perform a hydrogen annealing process.

This hydrogen annealing furnace 160 is equipped with a cylindrical chamber 161 made of a quartz tube, and heaters 162a, 1a for heating the semiconductor wafer 1A are provided on the outer periphery thereof.
62b is installed. The wafer boat 163 having a plurality of semiconductor wafers 1A mounted therein is a boat elevator 16
It is accommodated in the chamber 161 by raising 4.

Inside the chamber 161, a gas introducing pipe 16 is provided.
A predetermined amount of hydrogen gas is introduced through 5. This hydrogen gas is introduced into the hydrogen gas detoxification device 150 through the exhaust pipe 166 after the hydrogen annealing treatment of the semiconductor wafer 1A is completed. At this time, the gas storage tank 1 is connected through the pipe 167.
Oxygen gas is introduced into the hydrogen gas abatement device 150 from 44a. A mass flow controller 146e for adjusting the amount of oxygen gas is provided between the gas storage tank 144a and the pipe 167.
And an opening / closing valve 147e for opening and closing the flow path of oxygen gas are installed, and the amount of oxygen gas introduced into the hydrogen gas abatement device 150 is precisely controlled by these. Further, in the middle of the exhaust pipe 166, the oxygen gas is supplied to the hydrogen annealing furnace 16
Check valve 15 for preventing back flow into chamber 161 of 0
Two are provided.

The hydrogen gas abatement system 150 is equipped with the same reactor (141b) as that shown in FIG. That is, the reactor of the hydrogen gas abatement device 150 is made of a heat-resistant and corrosion-resistant alloy, and Pt, Ni, or Pd is contained in the reactor.
A coil made of a catalytic metal such as, and a heater for heating the coil are housed. The hydrogen gas and oxygen gas introduced into the reactor are contacted with a coil heated to about 350 to 450 ° C. to be excited, and the hydrogen radicals generated from hydrogen molecules and the oxygen radicals generated from oxygen molecules are promptly discharged. Reacts to produce water (steam).

Therefore, when the hydrogen gas discharged from the hydrogen annealing furnace 160 is introduced into the reactor of the hydrogen gas abatement system 150, at least 1/2 or more (molar ratio) of oxygen is introduced at the same time. As a result, hydrogen gas can be completely oxidized and converted into water. This oxygen gas may be introduced into the reactor prior to the introduction of hydrogen gas, or may be kept flowing through the pipe 167 into the reactor at all times. Water (steam) generated in the reactor
Is discharged to the outside through the exhaust pipe 153 together with the excess oxygen gas. In the middle of the exhaust pipe 153, a hydrogen gas sensor 154 for confirming whether or not the hydrogen gas is completely converted to water, and a cooler 155 for liquefying the discharged high temperature steam are provided. There is.

Next, an example of a hydrogen annealing process sequence using the hydrogen annealing furnace 160 will be described with reference to FIG.

First, after the wafer boat 163 loaded with a plurality of semiconductor wafers 1A is housed in the chamber 161 of the hydrogen annealing furnace 160, a purge gas (nitrogen gas) is introduced into the chamber 161 through the gas introduction pipe 165. The gas is sufficiently exchanged and the heaters 162a, 16a
The semiconductor wafer 1A is heated to about 400 ° C. using 2b. Next, through the gas introduction pipe 165, the chamber 161
Hydrogen gas is introduced into the inside, and the semiconductor wafer 1A is heat-treated for about 30 minutes to terminate Si dangling bonds with hydrogen.

Next, after introducing a purge gas into the chamber 161, and discharging unnecessary hydrogen gas through the exhaust pipe 166, the wafer boat 163 is set in the hydrogen annealing furnace 160.
And unloading the semiconductor wafer 1A.

On the other hand, through the exhaust pipe 166, the chamber 16
The hydrogen gas discharged from No. 1 is sent to the reactor of the hydrogen gas abatement device 150 together with the oxygen gas supplied through the pipe 167, and the oxygen gas and the hydrogen gas are converted into water (steam) by the catalytic action. This water vapor is forcedly exhausted to the outside through the exhaust pipe 153 together with the excess oxygen gas, and liquefied by the cooler 155. After that, the oxygen gas is exhausted to the outside through the exhaust duct, and the water is drained through the drain.

Instead of using hydrogen gas to oxidize hydrogen gas, dry air can be used to oxidize hydrogen gas. In this case, in consideration of the oxygen content in the air (about 21%), the dry gas containing oxygen at least ½ or more of the hydrogen amount (molar ratio) is introduced into the reactor to completely remove the hydrogen gas. Can be converted to water.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

The light oxidation treatment of the gate oxide film described above is carried out by using the batch type vertical oxidation furnace 170 as shown in FIG.
It is also possible to attach 40 and the hydrogen gas abatement device 150. FIG. 31 shows an example of a sequence of a light oxidation treatment process using the batch type vertical oxidation furnace 170.

Further, the hydrogen gas abatement device 150 is installed in the exhaust system of an oxidation furnace for performing light oxidation using a steam / hydrogen mixed gas generated by a so-called bubbling method, in which hydrogen gas is supplied into pure water contained in a container. It is also possible to remove the hydrogen in the exhaust gas by attaching the.

In the above embodiment, the removal of hydrogen gas exhausted in the light oxidation process of MOSFET and the removal of hydrogen gas exhausted in hydrogen annealing after the formation of the passivation film have been described. For example, hydrogen annealing for forming a defect-free layer on the surface of a Si wafer manufactured by CZ (Czochralski) method, hydrogen annealing after forming an epitaxial layer on the surface of the Si wafer, The present invention can be applied to the detoxification of hydrogen gas discharged in various hydrogen anneals performed in a semiconductor manufacturing process, such as hydrogen anneal performed in the middle of a process for measuring electrical characteristics.

It is also possible to concentrate the exhaust systems of a plurality of oxidation furnaces and hydrogen annealing furnaces at one location and install a hydrogen gas detoxification device in the middle thereof to improve the hydrogen gas detoxification efficiency. On the other hand, as in the above-described embodiment, one hydrogen gas abatement device is attached to the exhaust system of one oxidation furnace, or one hydrogen gas abatement device is attached to the exhaust system of one hydrogen annealing furnace. When it is attached, the route from the oxidation furnace or the hydrogen annealing furnace to the hydrogen gas abatement device is shortened, so that the safety is further improved.

[0085]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

According to the hydrogen abatement method of one aspect of the present invention, the hydrogen in the exhaust gas discharged from the gas phase treatment apparatus can be completely converted into water. As described above, there is no risk of unburned hydrogen being discharged to the outside, and hydrogen in exhaust gas can be safely removed.

According to another aspect of the present invention, which is a method of removing hydrogen, a method of removing hydrogen gas discharged from the gas phase treatment apparatus by diluting it with a large amount of nitrogen gas or air and discharging it into the atmosphere. Since the abatement device can be downsized as compared with the combustion system, the manufacturing cost of the device can be reduced.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a DRAM which is an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM according to an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM according to an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a DRAM according to an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM according to an embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a DRAM according to an embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM according to an embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a DRAM according to an embodiment of the present invention.

9A is a schematic plan view of a single-wafer oxidation furnace used for light oxidation treatment, and FIG. 9B is a sectional view taken along line BB ′ of FIG. 9A.

10A is a schematic plan view of a single-wafer oxidation furnace used for light oxidation treatment, and FIG. 10B is a sectional view taken along line BB ′ of FIG.

FIG. 11 is a schematic diagram of a catalytic steam / hydrogen mixed gas generation device and a hydrogen gas detoxification device connected to a single-wafer oxidation furnace.

FIG. 12 is a graph showing the temperature dependence of the equilibrium vapor pressure ratio of a redox reaction using a steam / hydrogen mixed gas.

FIG. 13 is a diagram showing a sequence of a light oxidation process using a single-wafer oxidation furnace.

FIG. 14 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a DRAM which is an embodiment of the present invention.

FIG. 15 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a DRAM according to an embodiment of the present invention.

FIG. 16 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a DRAM according to an embodiment of the present invention.

FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM which is the embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM according to an embodiment of the present invention.

FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM which is the embodiment of the present invention;

FIG. 20 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM which is the embodiment of the present invention;

FIG. 21 is a main-portion cross-sectional view of the semiconductor substrate, which shows the method of manufacturing the DRAM according to the embodiment of the present invention.

FIG. 22 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM according to an embodiment of the present invention.

FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM which is the embodiment of the present invention;

FIG. 24 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM which is the embodiment of the present invention;

FIG. 25 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM which is the embodiment of the present invention;

FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the DRAM which is the embodiment of the present invention;

FIG. 27 is a main-portion cross-sectional view of the semiconductor substrate, which shows the manufacturing method of the DRAM which is the embodiment of the present invention.

FIG. 28 is a schematic view of a batch type vertical hydrogen annealing furnace and a catalyst type hydrogen gas detoxification apparatus connected thereto.

FIG. 29 is a diagram showing a sequence of a hydrogen annealing process using a batch type vertical hydrogen annealing furnace.

FIG. 30 is a schematic view of a batch type vertical oxidation furnace used for light oxidation treatment.

FIG. 31 is a diagram showing a sequence of a light oxidation process using a batch type vertical oxidation furnace.

[Explanation of symbols]

1 semiconductor substrate 1A semiconductor wafer 2 silicon oxide film (pad oxide film) 3 silicon nitride film 4 element isolation groove 4a groove 5 silicon oxide film 6 silicon oxide film 7 p-type well 8 n-type well 9 gate oxide film 10 polycrystalline silicon film 11 WN Film 12 W Film 13 Silicon Nitride Films 14A to 14C Gate Electrode 16 p ⁻ Type Semiconductor Region 17 n ⁻ Type Semiconductor Region 18 n Type Semiconductor Region 19 Silicon Nitride Film 19a Sidewall Spacer 20 Photoresist Film 21 p ⁺ Type Semiconductor Region 22 n ⁺ type semiconductor region 23 silicon oxide film 24 photoresist film 25 contact hole 26 contact hole 27 plug 28 silicon oxide film 29 photoresist film 30 photoresist films 31 to 34 contact holes 35, 36 first layer wiring 37 silicon oxide film 38 Silicon oxide film 39 Through -Hole 40 Plug 41 Lower electrode 42 Capacitance insulating film 43 Upper electrode 44 Silicon oxide film 45, 46 Through hole 47 Plug 48 to 51 Second layer wiring 52 Silicon oxide film 53 Through hole 54 Plug 55 Third layer wiring 56 100 passivation films Leaf-type oxidation furnace 101 Chambers 102a, 102b Heater 103 Soaking ring 104 Susceptor 105 Support arm 106 Thermocouple 107 Lamp 108 Gas introduction pipe 109 Through hole 110 Partition wall 111 Exhaust pipe 140 Steam / hydrogen mixed gas generator 141a Reactor 141b Reactor 142 coil 143 heaters 144a to 144c gas storage tank 145 pipes 146a to 146e mass flow controllers 147a to 147e open / close valve 150 hydrogen gas abatement device 151 pipe 152 check valve 153 exhaust pipe 154 hydrogen SENSOR 155 Cooler 160 Batch type vertical hydrogen annealing furnace 161 Chambers 162a, 162b Heater 163 Wafer boat 164 Boat elevator 165 Gas introduction pipe 166 Exhaust pipe 167 Pipe 170 Batch type vertical oxidation furnace BL bit line C Information storage capacity element MARY Memory array Qn n-channel type MOSFET Qp p-channel type MOSFET Qs MISFET for memory cell selection SA sense amplifier WD word driver WL word line

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/8234 H01L 27/10 621B 5F083 21/8242 671Z 5F140 27/088 29/78 301G 27/108 27 / 10 681F 29/78 27/08 102C (72) Toshiaki Nagahama Toshiaki Nagahama 3-3, Fujibashi, Ome-shi, Tokyo 2 Hitachi Hitachi Tokyo Electronics Co., Ltd. (72) Inventor Nobuyoshi Natsuaki 2326 Imai, Ome, Tokyo Hitachi, Ltd. In-house (72) Inventor Yasuhiko Nakatsuka 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center F-term (reference) 4M104 BB01 EE20 5F032 AA35 AA44 BA02 CA03 CA17 DA02 DA23 DA24 DA33 DA43 DA74 5F033 HH08 HH33 JJ19 KK01 PP15 5F045 AA20 BB20 DP01 DP19 DQ05 EG07 5F048 AB01 AC01 AC10 BA01 BB06 BB09 BB11 BB13 BC06 BC19 BC20 BE03 BF01 BF02 BF04 BF07 BF12 BG01 BG13 DA19 DA27 5F083 AD01 AD42 AD48 AD49 JA06 JA36 JA39 JA40 KA01 KA05 MA03 MA06 MA16 MA17 MA20 MA01 NA05 PR05 PR12 PR18 PR43 PR52 PR44 PR44 PR33 PR40 PR42 PR33 PR40 PR42 PR44 PR33 PR40 PR42 PR33 PR40 PR33 PR40 PR42 PR33 PR40 PR42 PR33 PR40 PR42 PR33 PR40 PR43 PR44 PR44 PR33 PR40 PR42 PR33 PR40 PR42 PR33 PR40 PR42 PR33 PR40 PR43 PR44 PR44 PR44 PR44 PR33 PR40 PR42 PR33 PR40 PR43 PR44 PR44 PR33 PR40 PR43 PR40 PR43 PR40 PR43 PR40 PR43 PR40 PR43 PR40 ZA06 5F140 AB03 AB09 AC32 BA01 BD09 BD18 BE03 BE07 BE17 BF03 BF11 BF17 BF20 BF21 BF27 BG08 BG14 BG28 BG30 BG41 BG44 BG45 BG50 BG52 BG53 BH15 BJ27 BK02 BK13 BK30 CA02 CA06 CA08 CE07

Claims (2)

[Claims] 1. A film thickness formed on the main surface of a semiconductor substrate is 5
After depositing a conductive film containing at least a metal film on the gate oxide film of not more than nm, the conductive film is patterned to form a MOS.
Hydrogen gas containing low-concentration water vapor that is generated from hydrogen and oxygen by a catalytic action and that can control the reproducibility of oxide film formation and the uniformity of oxide film thickness Is supplied to the main surface of the semiconductor substrate heated to a predetermined temperature or its vicinity, and the main surface of the semiconductor substrate is selectively oxidized to improve the profile of the side wall end portion of the gate electrode. And a step of causing hydrogen contained in the exhaust gas after the oxidation treatment to react with oxygen by a catalyst to remove harm, and a method for manufacturing a semiconductor integrated circuit device. 2. A step of depositing a passivation film on the uppermost wiring after forming a single-layer or multiple-layer wiring on the main surface of the semiconductor substrate, and during or during the step of depositing the passivation film. Before and after the step, a step of terminating the dangling bonds of Si with hydrogen by heat-treating the semiconductor substrate in a gas atmosphere containing hydrogen, and reacting hydrogen contained in the exhaust gas after the heat treatment with oxygen by a catalyst. A method of manufacturing a semiconductor integrated circuit device, the method comprising: