JP2003179033A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JP2003179033A JP2003179033A JP2001377137A JP2001377137A JP2003179033A JP 2003179033 A JP2003179033 A JP 2003179033A JP 2001377137 A JP2001377137 A JP 2001377137A JP 2001377137 A JP2001377137 A JP 2001377137A JP 2003179033 A JP2003179033 A JP 2003179033A
- Authority
- JP
- Japan
- Prior art keywords
- film
- cmp
- manufacturing
- semiconductor device
- convex portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- ing And Chemical Polishing (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置の製造
方法に関し、更に言えば、半導体基板上に形成された凸
部をＣＭＰ（ケミカル・メカニカル・ポリッシング）法
により研磨して平坦化処理を施す技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more specifically, a convex portion formed on a semiconductor substrate is polished by a CMP (Chemical Mechanical Polishing) method to be planarized. Regarding technology.
【０００２】[0002]
【従来の技術】従来の半導体装置の製造方法について図
面を参照しながら説明する。尚、以下の説明では、半導
体基板上に形成された配線を被覆するように層間絶縁膜
を形成した際に、当該配線（下地段差部）の直上の層間
絶縁膜の凸部を、ＣＭＰ法を用いて平坦化処理する形態
について説明する。2. Description of the Related Art A conventional method of manufacturing a semiconductor device will be described with reference to the drawings. In the following description, when the interlayer insulating film is formed so as to cover the wiring formed on the semiconductor substrate, the convex portion of the interlayer insulating film immediately above the wiring (underlying stepped portion) is subjected to the CMP method. A mode of performing the flattening process using the above will be described.
【０００３】図７において、例えば、半導体基板２１上
に形成された層間絶縁膜２２上に配線２３が形成され、
当該配線２３を被覆するように層間絶縁膜２４が形成さ
れている。このとき、配線２３の直上に形成された層間
絶縁膜２４には、その配線２３の膜厚分により凸部２５
が形成されている。In FIG. 7, for example, a wiring 23 is formed on an interlayer insulating film 22 formed on a semiconductor substrate 21,
An interlayer insulating film 24 is formed so as to cover the wiring 23. At this time, the convex portion 25 is formed on the interlayer insulating film 24 formed immediately above the wiring 23 due to the film thickness of the wiring 23.
Are formed.
【０００４】そして、前記層間絶縁膜２４上にフォトレ
ジスト膜２６を形成し、当該フォトレジスト膜２６を現
像・露光処理して、前記凸部２５上に開口部２７を形成
する。Then, a photoresist film 26 is formed on the interlayer insulating film 24, and the photoresist film 26 is developed and exposed to form an opening 27 on the convex portion 25.
【０００５】続いて、図８において、前記フォトレジス
ト膜２６をマスクにして前記層間絶縁膜２４を異方性エ
ッチング処理することで、当該凸部２５に凹部２８を形
成する。Subsequently, in FIG. 8, the interlayer insulating film 24 is anisotropically etched using the photoresist film 26 as a mask to form a concave portion 28 in the convex portion 25.
【０００６】更に、図９において、前記フォトレジスト
膜２６を除去した後に、前記層間絶縁膜２４をＣＭＰ法
により研磨して平坦化処理を施している。Further, in FIG. 9, after removing the photoresist film 26, the interlayer insulating film 24 is polished by a CMP method to be planarized.
【０００７】[0007]
【発明が解決しようとする課題】このように従来の方法
では、ＣＭＰ工程の高均一性を達成するために、突出し
たパターン部（凸部２５）に反転マスクを用いてエッチ
ング処理して凸部２５を削り取ることで、ＣＭＰ工程の
均一性を向上させている。As described above, in the conventional method, in order to achieve high uniformity in the CMP process, the protruding pattern portions (convex portions 25) are subjected to etching treatment using an inversion mask to form convex portions. By scraping off 25, the uniformity of the CMP process is improved.
【０００８】しかし、上述した異方性エッチング工程で
は、そのエッチングバラツキが比較的大きく、そのＣＭ
Ｐバラツキが最大でレンジ５０ｎｍもあり、制御性が低
かった。However, in the above-mentioned anisotropic etching process, the etching variation is relatively large, and the CM
The maximum P variation was in the range of 50 nm, and the controllability was low.
【０００９】また、パターン部において、その疎密な領
域で、削れ量にバラツキが出ていた。即ち、比較的疎な
領域（オープンスペース部）での削れ量が大きくなると
いう問題があった（図９に示す膜厚バラツキ（Ａ＞Ｂ）
を参照）。Further, in the sparse and dense areas of the pattern portion, the amount of abrasion varies. That is, there is a problem that the amount of abrasion in the relatively sparse region (open space part) becomes large (film thickness variation (A> B) shown in FIG. 9).
See).
【００１０】[0010]
【課題を解決するための手段】そこで、上記課題に鑑み
本発明の半導体装置の製造方法は、半導体基板上に形成
された凸部をＣＭＰ法により研磨して平坦化処理を施す
ものにおいて、前記ＣＭＰ工程の前工程として、前記凸
部上に開口部を有するフォトレジスト膜をマスクにして
当該凸部をケミカルドライエッチング処理して、当該凸
部を含むその周辺部を、予め平坦化する工程を有するこ
とを特徴とするものである。In view of the above problems, the method of manufacturing a semiconductor device according to the present invention is directed to a method of polishing a convex portion formed on a semiconductor substrate by a CMP method to perform a planarization process. As a pre-step of the CMP step, a step of performing chemical dry etching on the convex portion with a photoresist film having an opening on the convex portion as a mask to flatten the peripheral portion including the convex portion in advance. It is characterized by having.
【００１１】[0011]
【発明の実施の形態】以下、本発明の半導体装置の製造
方法について図面を参照しながら説明する。尚、以下の
説明では、半導体基板上に形成された配線を被覆するよ
うに層間絶縁膜を形成した際に、当該配線（下地段差
部）の直上の層間絶縁膜の凸部を、ＣＭＰ法を用いて平
坦化処理する形態について説明する。DETAILED DESCRIPTION OF THE INVENTION A method of manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings. In the following description, when the interlayer insulating film is formed so as to cover the wiring formed on the semiconductor substrate, the convex portion of the interlayer insulating film immediately above the wiring (underlying stepped portion) is subjected to the CMP method. A mode of performing the flattening process using the above will be described.
【００１２】図１において、例えば、半導体基板１上に
形成された層間絶縁膜２上に配線３が形成され、当該配
線３を被覆するようにＳｉＯ2膜やＳｉＮ膜から成る層
間絶縁膜４が形成されている。このとき、配線３の直上
に形成された層間絶縁膜４には、前記配線３の膜厚分に
より凸部５が形成されている。In FIG. 1, for example, a wiring 3 is formed on an interlayer insulating film 2 formed on a semiconductor substrate 1, and an interlayer insulating film 4 made of a SiO 2 film or a SiN film is formed so as to cover the wiring 3. Has been formed. At this time, the convex portion 5 is formed on the interlayer insulating film 4 formed right above the wiring 3 by the film thickness of the wiring 3.
【００１３】そして、前記層間絶縁膜４上にフォトレジ
スト膜６を形成し、当該フォトレジスト膜６を現像・露
光処理して、前記凸部５上に開口部７を形成する。Then, a photoresist film 6 is formed on the interlayer insulating film 4, and the photoresist film 6 is developed and exposed to form an opening 7 on the convex portion 5.
【００１４】続いて、図２において、前記フォトレジス
ト膜６をマスクにして前記層間絶縁膜４をケミカルドラ
イエッチング（等方性エッチング）処理することで、当
該凸部５をエッチングし、前記配線３の上部を露出させ
る。このとき、フォトレジスト膜６として、従来のマス
クと同じ寸法の開口部を有するマスクを用いても、本実
施形態では、前記層間絶縁膜４を等方性エッチングして
いるため、前記配線３の周辺部に形成されていた層間絶
縁膜４も削れて、従来に比して平坦化されている。Subsequently, in FIG. 2, the interlayer insulating film 4 is subjected to chemical dry etching (isotropic etching) by using the photoresist film 6 as a mask to etch the convex portion 5 and the wiring 3 Expose the top of the. At this time, even if a mask having an opening having the same size as that of a conventional mask is used as the photoresist film 6, in the present embodiment, the interlayer insulating film 4 is isotropically etched. The interlayer insulating film 4 formed in the peripheral portion is also scraped and is flattened as compared with the conventional one.
【００１５】尚、本エッチング工程では、例えば、Ｓｉ
Ｏ2膜から成る層間絶縁膜４の場合には、ＣＦ4＋Ｏ2ガ
スを用い、ＳｉＮ膜から成る層間絶縁膜４の場合には、
ＣＦ 4＋Ｏ2＋Ｎ2ガスを用いている。In this etching step, for example, Si
O2In the case of the interlayer insulating film 4 made of a film, CFFour+ O2Moth
In the case of the interlayer insulating film 4 made of SiN film,
CF Four+ O2+ N2It uses gas.
【００１６】更に、図３において、前記フォトレジスト
膜６を除去した後に、前記層間絶縁膜４をＣＭＰ法によ
り、前記層間絶縁膜４と配線３の頭部を研磨して平坦化
処理を施す。このとき、ＣＭＰ工程の前工程で、層間絶
縁膜４の凸部を等方性エッチングすることで、予め、そ
の凸部５を削っている（凸部５を削ると共に、その周辺
部の層間絶縁膜４も削れて、従来方法に比してほぼ平ら
な状態としている）ため、ＣＭＰ工程による研磨工程に
より更に平坦化される。Further, in FIG. 3, after removing the photoresist film 6, the interlayer insulating film 4 is planarized by polishing the heads of the interlayer insulating film 4 and the wiring 3 by CMP. At this time, in the previous step of the CMP step, the convex portion of the interlayer insulating film 4 is isotropically etched to remove the convex portion 5 in advance (the convex portion 5 is removed and the interlayer insulating film around the peripheral portion is removed). Since the film 4 is also scraped and is in a substantially flat state as compared with the conventional method), it is further flattened by the polishing process by the CMP process.
【００１７】また、本発明では、凸部５を削る際に等方
性エッチング方法を採用したことで、凸部形成要因であ
る、下地段差部（配線３）とも十分な選択比を確保する
ことが可能になる。即ち、異方性エッチングは、基本的
にイオンスパッタ効果でエッチングしているのに対し、
ケミカルエッチングは化学反応でエッチングしているた
め、選択比が高くなる。そのため、従来のように配線の
頭部を露出させないように異方性エッチングする必要が
無くなる。従って、配線３上には層間絶縁膜４が存在し
ないため、ＣＭＰ工程による平坦化作業性が向上する。Further, in the present invention, the isotropic etching method is adopted when the convex portion 5 is shaved, so that a sufficient selection ratio is secured also for the underlying stepped portion (wiring 3) which is a factor for forming the convex portion. Will be possible. That is, while anisotropic etching basically etches by the ion sputtering effect,
Since the chemical etching is performed by a chemical reaction, the selection ratio is high. Therefore, it is not necessary to perform anisotropic etching so that the head of the wiring is not exposed as in the conventional case. Therefore, since the interlayer insulating film 4 does not exist on the wiring 3, the planarization workability in the CMP process is improved.
【００１８】従来では、ＣＭＰ工程の高均一性を達成す
るために、凸部１５に反転マスクを用いて異方性エッチ
ング処理して凸部１５を削り取ることで、ＣＭＰ工程の
均一性を向上させていたが、この場合のＣＭＰバラツキ
は比較的大きく、その制御性に問題があったが、本実施
形態ではＣＭＰバラツキレンジをおよそ１５ｎｍ程度に
まで低減することができた。そのため、パターン部にお
いて、その疎密な領域においても、削れ量のバラツキ発
生を低減できた。即ち、図３に示すように、本発明の膜
厚バラツキ（Ｃ−Ｄ）（図３参照）は、従来の膜厚バラ
ツキ（Ａ−Ｂ）よりも小さい（図６参照）。Conventionally, in order to achieve high uniformity in the CMP process, the convex part 15 is removed by anisotropic etching using an inversion mask to improve the uniformity of the CMP process. However, the CMP variation in this case is comparatively large and there is a problem in its controllability, but in the present embodiment, the CMP variation range could be reduced to about 15 nm. Therefore, it is possible to reduce the occurrence of variation in the scraped amount in the sparse and dense areas of the pattern portion. That is, as shown in FIG. 3, the film thickness variation (C-D) of the present invention (see FIG. 3) is smaller than the conventional film thickness variation (AB) (see FIG. 6).
【００１９】また、本実施形態では、配線３（配線に限
らなくても良い。）を被覆するように形成された層間絶
縁膜４の凸部５を等方性エッチングして、当該凸部５と
その周辺部の層間絶縁膜４を、予め平坦化しているが、
本発明はこれに限定されるものではなく、例えばトレン
チ法やＳＴＩ（シャロー・トレンチ・アイソレーショ
ン）法を用いた素子分離膜の形成方法に本発明を適用し
て、当該素子分離膜の平坦化作業性を向上させるもので
あっても構わない。Further, in this embodiment, the convex portion 5 of the interlayer insulating film 4 formed so as to cover the wiring 3 (not limited to the wiring) is isotropically etched, and the convex portion 5 is formed. And the interlayer insulating film 4 in the peripheral portion of the
The present invention is not limited to this, and for example, the present invention is applied to a method of forming an element isolation film using a trench method or an STI (shallow trench isolation) method to planarize the element isolation film. It may be one that improves workability.
【００２０】以下に、上記ＳＴＩ法を用いた素子分離膜
の形成方法について図面を参照しながら説明する。A method of forming an element isolation film using the STI method will be described below with reference to the drawings.
【００２１】図４において、例えば、半導体基板１１の
所望位置に第１の膜１２（例えば、ＳｉＯ2膜）及び第
２の膜１３（例えば、ＳｉＮ膜）を積層し、当該積層膜
１２，１３をマスクに前記基板１２をエッチングして溝
１４を形成する。In FIG. 4, for example, a first film 12 (for example, a SiO 2 film) and a second film 13 (for example, a SiN film) are laminated at desired positions on the semiconductor substrate 11, and the laminated films 12 and 13 are formed. Using the as a mask, the substrate 12 is etched to form the groove 14.
【００２２】続いて、図５において、前記溝１４を含む
基板１１上にＣＶＤＳｉＯ2膜１５を形成する。このと
き、溝１４が密な領域に形成されたＣＶＤＳｉＯ2膜１
５の膜厚は薄く、疎な（無い）領域に形成されたＣＶＤ
ＳｉＯ2膜１５の膜厚は厚くなり、凸部１６が形成され
る（Ｅ＜Ｆ）。そのため、このままの状態で、ＣＭＰ研
磨を行った場合には、ＣＭＰバラツキが大きくなってし
まう。Subsequently, referring to FIG. 5, a CVDSiO 2 film 15 is formed on the substrate 11 including the groove 14. At this time, the CVD SiO 2 film 1 in which the grooves 14 are formed in the dense region is formed.
5 is thin and CVD formed in a sparse (absent) region
The thickness of the SiO 2 film 15 becomes thicker and the convex portion 16 is formed (E <F). Therefore, when the CMP polishing is performed in this state, the CMP variation becomes large.
【００２３】そこで、本発明を適用して、前記ＣＶＤＳ
ｉＯ2膜１５上にフォトレジスト膜１７を形成し、当該
フォトレジスト膜１７を現像・露光処理して、図６に示
すように前記凸部１６上に開口部１８を形成する。Therefore, by applying the present invention, the CVDS
A photoresist film 17 is formed on the iO 2 film 15, and the photoresist film 17 is developed and exposed to form an opening 18 on the convex portion 16 as shown in FIG.
【００２４】そして、前記フォトレジスト膜１７をマス
クにして前記ＣＶＤＳｉＯ2膜１５をケミカルドライエ
ッチング（等方性エッチング）処理することで、当該凸
部１６をエッチングする。このとき、前記溝１４内を埋
設するように形成されたＣＶＤＳｉＯ2膜１５の上面と
ほぼ同等の位置となるまでエッチングを施すことで、後
工程でのＣＭＰ研磨でのＣＭＰバラツキを抑止でき、平
坦化が図れる。Then, by using the photoresist film 17 as a mask, the CVD SiO 2 film 15 is subjected to chemical dry etching (isotropic etching) to etch the convex portion 16. At this time, etching is performed until the position is almost the same as the upper surface of the CVD SiO 2 film 15 formed so as to fill the inside of the groove 14, so that CMP variation in CMP polishing in a later process can be suppressed and flat Can be realized.
【００２５】尚、前記ＣＶＤＳｉＯ2膜１５の成膜法と
して、エッチングしながら酸化膜を成膜していく、いわ
ゆるＨＤＰ（ハイ・デンシティ・プラズマ）法を用いた
場合には、前記溝１４が存在しない領域（疎な領域）に
は当然のことながら削られた酸化膜が入る溝がないた
め、成膜した膜厚分だけそのまま成膜されるため、より
高段差となる。従って、本発明を適用することで、ＣＭ
Ｐバラツキを抑止でき、平坦化が図れる。When the so-called HDP (high density plasma) method in which an oxide film is formed while etching is used as the method for forming the CVD SiO 2 film 15, the groove 14 exists. Naturally, since there is no groove in which the scraped oxide film enters in the non-use area (sparse area), the film is formed as it is by the thickness of the formed film, resulting in a higher step. Therefore, by applying the present invention, CM
P variation can be suppressed and flattening can be achieved.
【００２６】[0026]
【発明の効果】本発明によれば、ＣＭＰ工程の前工程に
おいて、半導体基板上に形成された凸部をケミカルドラ
イエッチング処理することで、当該凸部を含むその周辺
部を、予め平坦化しているため、その後のＣＭＰ工程に
おける平坦化作業性が向上する。According to the present invention, in the pre-process of the CMP process, the convex portion formed on the semiconductor substrate is subjected to chemical dry etching to flatten the peripheral portion including the convex portion in advance. Therefore, the planarization workability in the subsequent CMP process is improved.
【００２７】また、凸部形成要因である、下地段差部と
も十分に選択比が確保可能となり、ＣＭＰ工程での作業
性が向上する。Further, it is possible to secure a sufficient selection ratio with the underlying step portion, which is a factor for forming the convex portion, and the workability in the CMP process is improved.
【図１】本発明の第１の実施形態の半導体装置の製造方
法を示す断面図である。FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第１の実施形態の半導体装置の製造方
法を示す断面図である。FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor device of the first embodiment of the present invention.
【図３】本発明の第１の実施形態の半導体装置の製造方
法を示す断面図である。FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device of the first embodiment of the present invention.
【図４】本発明の第２の実施形態の半導体装置の製造方
法を示す断面図である。FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device of the second embodiment of the present invention.
【図５】本発明の第２の実施形態の半導体装置の製造方
法を示す断面図である。FIG. 5 is a cross-sectional view showing the method of manufacturing the semiconductor device of the second embodiment of the present invention.
【図６】本発明の第２の実施形態の半導体装置の製造方
法を示す断面図である。FIG. 6 is a cross-sectional view showing the method of manufacturing the semiconductor device of the second embodiment of the present invention.
【図７】従来の半導体装置の製造方法を示す断面図であ
る。FIG. 7 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device.
【図８】従来の半導体装置の製造方法を示す断面図であ
る。FIG. 8 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
【図９】従来の半導体装置の製造方法を示す断面図であ
る。FIG. 9 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 21/304 ６２２ Ｈ０１Ｌ 21/302 Ｌ 21/3205 21/88 Ｋ 21/76 21/76 Ｌ Ｆターム(参考） 4K057 WA04 WC03 WC10 WN01 5F004 AA11 DA04 DA25 DA26 DB03 EA10 EA28 EB03 5F032 AA34 AA44 AA77 DA23 DA26 DA33 DA78 5F033 QQ09 QQ11 QQ18 QQ48 RR04 RR06 SS11 XX01 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 21/304 622 H01L 21/302 L 21/3205 21/88 K 21/76 21/76 LF term ( Reference) 4K057 WA04 WC03 WC10 WN01 5F004 AA11 DA04 DA25 DA26 DB03 EA10 EA28 EB03 5F032 AA34 AA44 AA77 DA23 DA26 DA33 DA78 5F033 QQ09 QQ11 QQ18 QQ48 RR04 RR06 SS11 XX01
Claims (3)
法により研磨して平坦化処理を施す半導体装置の製造方
法において、 前記ＣＭＰ工程の前工程として、前記凸部上に開口部を
有するフォトレジスト膜をマスクにして当該凸部をエッ
チング処理する工程を有することを特徴とする半導体装
置の製造方法。1. A CMP method for forming protrusions formed on a semiconductor substrate.
In the method of manufacturing a semiconductor device which is polished by a method and subjected to a planarization process, a step of etching the convex portion using a photoresist film having an opening on the convex portion as a mask as a pre-step of the CMP step. A method of manufacturing a semiconductor device, comprising:
被覆するように形成された層間絶縁膜をＣＭＰ法により
研磨して平坦化処理を施す半導体装置の製造方法におい
て、 前記ＣＭＰ工程の前工程として、層間絶縁膜の凸部上に
開口部を有するフォトレジスト膜をマスクにして当該凸
部をエッチング処理する工程を有することを特徴とする
半導体装置の製造方法。2. A method of manufacturing a semiconductor device, wherein an interlayer insulating film formed so as to cover an underlying stepped portion formed on a semiconductor substrate is polished by a CMP method to perform a planarization process, wherein the CMP step is performed before the CMP step. A method of manufacturing a semiconductor device, which comprises, as a step, a step of etching the convex portion of the interlayer insulating film using a photoresist film having an opening as a mask.
エッチング工程であることを特徴とする請求項１または
請求項２に記載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the etching step is a chemical dry etching step.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019150541A1 (en) * | 2018-02-02 | 2019-08-08 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
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2001
- 2001-12-11 JP JP2001377137A patent/JP2003179033A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019150541A1 (en) * | 2018-02-02 | 2019-08-08 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
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