JP2003178020A - Bus control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus control device capable of effectively using the cycle of an internal bus without hindrance to operation. <P>SOLUTION: A CPU inside access determining part 61 in a bus control part 51 recognizes a DMA transfer system when starting DMA on the basis of a preset value of a transfer system register 13, and makes determination for allowing a CPU inside access request for requiring access to the internal bus by a CPU in external bus access of DMA operation executed in order of the external bus access and internal bus access when DMA transfer is a normal transfer system, and prohibiting the CPU inside access request even in the external bus access when the DMA transfer is a burst transfer system. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control device which is signal-connected to a CPU, an internal bus, and an external bus and is capable of executing DMA transfer.

[0002]

2. Description of the Related Art A bus controller is signal-connected to a CPU, an internal bus, and an external bus, and executes an internal bus access or makes an external bus access request to an external bus interface in response to a DMA request.
Perform the transfer.

(Construction of Prior Art) FIG. 11 is a block diagram showing the construction of a bus controller according to the prior art. As shown in the figure, the bus control device 5 includes a register group 2, a bus control unit 50, and a DMA request detection unit 60, and uses a system clock CLK as an operation clock.

The register group 2 has a transfer source address register 10, a transfer destination address register 11, a DMA transfer counter 12, a transfer method register 13, and a DMA request selection register 14.

The transfer source address register 10 stores the DMA transfer source address, the transfer destination address register 11 stores the DMA transfer destination address, and the DMA transfer counter 12 stores the number of data to be transferred by DMA. , 13 store transfer method information for selecting a DMA transfer method (burst transfer or normal transfer), and a DMA request selection register 14 stores selection information for selecting a request signal for activating DMA. That is,
The register group 2 is an information storage unit that stores DMA transfer information.

The normal transfer system is a system for transferring data in units of one unit, and the burst transfer system is a system for collectively transferring a plurality of units of data.

The bus control unit 50 arbitrates access requests and DMA requests from a CPU (not shown) to execute bus access, and the DMA request detection unit 60 follows the set value (selection information) of the DMA request selection register 14. DM from outside
Detect A request.

The bus control unit 50 controls access to the CPU, the outside and the inside by sending and receiving the CPU / I / F signal group 7, the internal bus access signal group 8 and the external bus access signal group 9.

The CPU / I / F signal group 7 is I / F with the CPU.
/ F (interface) signal group, the CPU access request signal CREQ is a signal for the CPU to request the bus access, and the CPU access response signal CACK is a signal indicating that the CPU has accepted the bus access. Yes, the CPU access completion signal CDC is a signal indicating that the received access is completed, the CPU address signal CADDDR (CADDDR [31: 0]) is a signal indicating the address of the access destination, and the CPU read / write control signal. CRW is a control signal for instructing whether the access is a read access or a write access, and the CPU
Write data signal CWDATA (CWDATA [31:
0]) is a signal for transferring data for write access, and is a CPU read data signal CRDATA (CRD
ATA [31: 0]) is a signal for transferring data for read access.

The internal bus access signal group 8 is a group of signals for accessing the bus inside the chip in which the bus controller 5 is built, and the internal address signal IADDR (IAD
DDR [31: 0]) is a signal indicating an internal address, the internal read / write control signal IRW is a signal indicating whether the access is a read access or a write access, and the internal write data signal IWDATA ( I
WDATA [31: 0]) is a signal for transferring data for write access, and is an internal read data signal IRD.
ATA (IRDATA [31: 0]) is a signal for transferring data for read access, an internal access completion signal IDC is a signal indicating that bus access is completed, and an internal access request signal IREQ from the inside. This is a signal indicating an access request.

The external bus access signal group 9 is a signal group for requesting an external bus interface (not shown) for bus access outside the chip, and the external address signal EADDR (EADDR [31: 0]) is external. To the external read / write control signal E.
RW is a control signal that indicates whether the access is a read access or a write access, and the external write data signal EWDATA (EWDATA [31: 0]) is a signal that transfers data for write access. Read data signal ERDATA (ERDATA [31:
0]) is a signal for transferring data for read access, an external access completion signal EDC is a signal indicating that bus access is completed, and an external access request signal EREQ is a signal indicating an access request from the outside. Yes,
The external access burst request signal EBURST is a signal for requesting burst access to the external bus interface.

The DMA request detection unit 60 uses a DM from the outside.
The DMA request signal DMAREQ for accepting the A request is received, and the selected DMA request is transmitted to the bus control unit 50 based on the selection information stored in the DMA request selection register 14.

(Operation of Prior Art) The operation of the bus controller according to the prior art will be described below.

(1) DMA setting DMA setting is performed by the CPU from the register group 2 (transfer source address register 10, transfer destination address register 11, DMA transfer counter 12, transfer method register 13, DMA request selection) inside the bus controller. This is done by writing a value to register 14).

FIG. 12 is a timing diagram showing a register write operation within the bus controller. Here, the transfer source address register 10, the transfer destination address register 11, D
MA transfer counter 12, transfer method register 13, and D
The address of the MA request selection register 14 is 0, respectively.
x00700000, 0x00700004, 0x00
700008, 0x0070000c, and 0x007
It is assumed to be assigned to 00010.

The CPU access request signal CREQ is "H".
In this cycle, if the access can be accepted, the bus control unit 50 sets the CPU access response signal CACK to “H”.
To If the value of the CPU address signal CADDDR at this time is the value assigned to the internal register of the bus controller 5 and the CPU read / write control signal CRW is "L" (indicating a write access), the next system CPU write data signal CW at the rising edge of clock CLK
Write the DATA value to the corresponding register.

Since this access is completed in one cycle of the system clock CLK, the bus control unit 50
The CPU access completion signal CDC is set to "H" in the same cycle as the access response signal CACK.

In the example shown in FIG. 12, the CPU is used in the cycle T2.
0x007000 specified by the address signal CADDDR
Source address register 10 addressed by 00
Data D1 is written to the cycle T3
0x00 specified by CPU address signal CADDDR
The data D2 is written to the transfer destination address register 11 addressed in 700004, and the data D3 is written to the DMA transfer counter 12 addressed by 0x00700008 specified by the CPU address signal CADDDR in cycle T5. Is being done.

Each bit of the DMA request selection register 14 corresponds to 32 signals included in the DMA request signal 130, and the bit corresponding to the signal for starting the DMA is set to "1".

(2) Access from CPU to Internal Bus FIG. 13 is a timing chart showing an internal bus access operation from the CPU. Here, the address is 0x0000
0000 to 0x005fffff to the external bus, 0x0
It is assumed that 0600000 to 0x006fffff is assigned to the internal bus.

In cycle T2, the CPU sets the CPU access request signal CREQ to "H" to request access.
At the same time, the address 0x0 is added to the CPU address signal CADDDR.
It outputs 0600000. At this time, CPU read /
Since the write control signal CRW is "H", it is a read designation.

In cycle T3, the bus control unit 50 accepts the access and sets the CPU access response signal CACK to "H". At the same time, the internal access request signal IREQ is set to "H", and the address 0x00600000 designated by the CPU address signal CADDDR is set to the internal address signal IADDR.
To output the address.

From the cycle T4, the CPU continuously outputs C
The PU access request signal CREQ is set to "H" and the next access request is output. At the same time CPU address signal CAD
The internal address 0x0060004 is output to DR. At this time, the CPU read / write control signal CRW is "L".
Therefore, the light is designated.

Internal access completion signal ID in cycle T5
C becomes "H", the bus control unit 50 outputs the data D1 of the internal read data signal IRDATA as the CPU read data signal CRDATA, and sets the CPU access completion signal CDC to "H". That is, the internal read access requested by the CPU in cycle T2 is completed in cycle T5.

In cycle T6, the bus control unit 50 sets the CPU access response signal CACK to "H" and accepts the write access requested by the CPU in cycle T4. At the same time, the internal access request signal IREQ is set to "H", and CP
The value 0x0060004 of the U address signal CADDDR is used as the internal address signal IADDR, and the data D2 of the CPU write data signal CWDATA is used as the internal write data signal IW.
Output to DATA respectively. As a result, the data D2 is written to the internal address 0x0060004.

Then, in cycle T7, the internal access completion signal IDC is asserted, and the bus controller 50 sets the CPU access completion signal CDC to "H". That is, CP
The internal write access requested by U in cycle T4 is completed in cycle T7.

(3) Activation of DMA The DMA is activated by the rising edge of the signal selected from the signals included in the DMA request signal DMAREQ based on the selection information stored in the DMA request selection register 14. The DMA request detection unit 60 uses the DMA request signal DM
When the rising edge of the signal (bit) selected based on the selection information in AREQ [31: 0] is detected, a DMA activation request signal dma_req instructing DMA activation is transmitted to the bus control unit 50.

(4) DMA execution The DMA request detection unit 60 detects a DMA request and issues an "H" DMA start request signal dma_re for instructing DMA start.
When q is given to the bus control unit 50, the bus control unit 50 sends DM
Execute A transfer.

(Example of Normal DMA Transfer) FIG. 14 is a timing chart showing a normal DMA transfer operation according to the prior art. Here, the setting value of the transfer source address register 10 is 0x00400000 (external bus), the setting value of the transfer destination address register 11 is 0x00600000 (internal bus), the value of the DMA transfer counter 12 is 0x2, and the value of the transfer method register 13 is 0x0. It is assumed that it is set to (Normal transfer).

In cycle T2, the DMA start request signal dma
_Req becomes "H" and a DMA request is generated. Since the transfer source address is the external address, the bus control unit 50 sets the external access request signal EREQ to "H" (the external read / write control signal ERW maintains "H") from cycle T3, and starts the external read access. To do.

In the example shown in FIG. 14, the CPU is used in the cycle T4.
Although an internal bus access request irrelevant to the DMA transfer from the device is generated, the bus control unit 50 does not accept this request because the DMA transfer has already started.

At cycle T5, the external address 0x004
The data D1 of 00000 is the external read data signal ERD
It is output as ATA, the external access completion signal EDC becomes "H", and the external read access is completed. At the end of this cycle T5, the bus control unit 50 fetches the data D1 of the external read data signal ERDATA into an internal buffer (not shown).

Since the transfer destination address is the internal address, the bus control unit 50 sets the internal access request signal IREQ to "H" and the internal read / write control signal IRW to "L" from the cycle T6 to perform the internal write access. Start.

The internal write data signal IWDATA includes
The data D1 stored in the buffer inside the bus control unit 50 is output. As a result, the internal address 0x0060
The data D1 is written in 0000. Then, in cycle T7, the internal access completion signal IDC becomes "H",
Internal write access is completed.

Since the value of the DMA transfer counter 12 is 0x2, the bus control unit 50 starts the second external read access at cycle T8. At the same time, the CPU access response signal CACK is set to "H" to accept the CPU access (read access), and the internal bus access from the CPU is started. That is, the second external read access by the DMA transfer and the internal read access by the CPU are executed in parallel.

In the cycle T9, the CPU address signal CA
Internal address 0x00610000 specified by DDR
Data D10 of the CPU is read as the internal read data signal IRDATA, and then the CPU read data signal CRDA
The internal bus access from the CPU is completed by giving it to the CPU as TA.

At cycle T10, external address 0x00
The data D2 of 400004 is the external read data signal ER.
The data is output as DATA, and the second external read access of DMA is completed.

From the cycle T11, the bus control unit 50 becomes 2
Start the internal write access for the second time. Cycle T12
Then, the internal write access for writing the data D2 to the internal address 0x00600004 is completed, and the DMA transfer is completed.

(Burst DMA Transfer Example) FIG. 15 is a timing chart showing a burst DMA transfer operation according to the prior art. Here, the set value of the transfer source address register 10 is 0x00400000, the set value of the transfer destination address register 11 is 0x00600000 (internal bus), the value of the DMA transfer counter 12 is 0x4, and the value of the transfer method register 13 is 0x1 (burst transfer). And

In cycle T2, the DMA start request signal dma
_Req becomes "H" and a DMA request is generated. Since the transfer source address is an external address, the bus control unit 50 sets the external access request signal EREQ to "H" (the external read / write control signal ERW maintains "H") from cycle T3 to start the external read access. To do. At the same time, since the value of the transfer method register 13 is 0x1 (burst transfer), the bus control unit 50 sets the external access burst request signal EBURST to "H".

In cycle T4, an internal bus access request irrelevant to the DMA transfer from the CPU is generated, but since the DMA transfer has already started, the bus control unit 50 does not accept this request.

From cycle T5 to cycle T8, 0x00400000 and 0x00400 are continuously output from the external bus.
004, 0x00400008, and 0x004000
Data D1, D2, D3 of the external address in the order of 0c
And D4 are read. Since the value of the DMA transfer counter 12 is 0x4, the external access request signal ERE is generated in the next cycle T9 after the completion of the fourth external read access.
Q and external access burst request signal EBURST are set to "L".

On the other hand, the write access to the internal bus is 0x00600000, 0x006 from the next cycle T6 when the first read data D1 is read from the external bus.
00004, 0x00600008, and 0x0060
The data D1, D2, D3 and D4 are written in the order of 000c, and the write access is completed in cycle T9.

In cycle T10, the bus control unit 50 is the CPU
The access response signal CACK is set to "H" to accept the CPU access, and the internal bus access from the CPU is started. Internal address 0x0 from CPU in cycle T12
The internal bus access that outputs 06100000 data D10 is completed.

As shown in FIGS. 14 and 15, the internal bus access from the CPU is prohibited at the time when the DMA transfer executed in the order of external bus access and internal bus access is started. This is because if the DMA transfer is a burst transfer method and the completion of internal bus access from the CPU is slow, the data read by the burst access from the external bus is lost.

[0046]

Conventional bus controller 5
The DMA transfer operation by D is performed as described above, and D is executed in the order of external bus access and internal bus access.
Since the internal bus access from the CPU is locked when the MA transfer is started, there is a problem that the cycle of the internal bus cannot be effectively used.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a bus control device which can effectively use the cycle of the internal bus without hindering the DMA transfer operation.

[0048]

[Means for Solving the Problems] Claim 1 according to the present invention
The bus control device described above uses the DMA transfer method to transfer data to 1
A transfer method instructing unit for instructing whether it is a normal transfer method for transferring each unit or a burst transfer method for collectively transferring a plurality of units of data, and a signal connection to each of the CPU, the internal bus, and the external bus, and A bus control unit for performing bus connection control, wherein the bus control unit instructs the normal transfer method by the transfer method instruction unit at the time of executing DMA transfer executed in the order of external bus access and internal bus access. , C requesting access to the internal bus by the CPU during the external bus access
It has a CPU internal access determination unit that permits a PU internal access request.

According to a second aspect of the present invention, in the bus control device according to the first aspect, the CPU internal access determining section unconditionally operates when the transfer method instructing section instructs the normal transfer method. When the CPU internal access request during the external bus access is permitted and the transfer method instruction unit indicates the burst transfer method, the CPU internal access request is unconditionally prohibited during the external bus access.

The invention according to claim 3 is the bus control device according to claim 1, wherein the external bus access remaining for measuring the number of external bus access remaining cycles in the external bus access during the DMA transfer according to an operation clock. The CPU internal access determining unit further includes a cycle number measuring unit, and an internal address table that stores the CPU internal address that is the target of the CPU internal access request and the CPU internal bus execution cycle number in association with each other. When the method instructing section gives an instruction for the normal transfer method, at least the CP of the CPU internal address is referred to by referring to the internal address table based on the CPU internal address.
The U internal bus execution cycle number is acquired, and when the condition that the CPU internal bus execution cycle number is equal to or less than the external bus access remaining cycle number is satisfied, the CPU internal access request during the external bus access is permitted.

According to a fourth aspect of the present invention, in the bus control device according to the third aspect, the CPU internal access determination section is at least the CPU when the transfer method instruction section instructs the burst transfer method. The CPU internal bus execution cycle number of the CPU internal address is acquired by referring to the internal address table based on the internal address, and the C
When the condition that the number of PU internal bus execution cycles is equal to or less than the number of external bus access remaining cycles is satisfied, the external bus access permits the CPU internal access request during access to the first unit data.

The invention according to claim 5 is the bus control device according to claim 3 or 4, wherein the internal address table includes the C internal address in addition to the CPU internal address.
An access mode including a read mode and a write mode of a PU internal access request is stored in association with the number of CPU internal bus execution cycles, and the CPU internal access determination unit is configured to execute the internal operation based on the CPU internal address and the access mode. The number of the CPU internal bus execution cycles of the CPU internal address is acquired by referring to the address table.

The invention of claim 6 is the bus control device according to any one of claims 3 to 5, wherein the external bus is the number of external bus execution cycles of the external bus access. An external access cycle signal indicating that the external bus access remaining cycle number is initialized, and the bus control unit initializes the external bus execution cycle number as the external bus access remaining cycle number at the start of the external bus access. Further includes a section.

According to a seventh aspect of the present invention, in the bus control device according to any one of the third to sixth aspects, the CPU internal bus access remaining cycle number is measured in accordance with the operation clock. A CPU internal bus access remaining cycle count measuring unit is further provided, and the bus control unit is
At the start of the CPU internal bus access, the CPU internal bus execution cycle number of the CPU internal address is acquired by referring to the internal address table based on at least the CPU internal address, and the acquired CPU internal bus execution cycle number is acquired by the CPU. When a CPU internal bus access remaining cycle number initial value setting unit which is initially set as the internal bus access remaining cycle number and a DMA request executed from the external bus access in the order of the internal bus access during execution of the CPU internal access are performed. And a DMA access determination unit that permits external access of the DMA transfer during the CPU internal bus access when the condition that the predetermined external bus access predicted execution cycle number is equal to or less than the CPU internal bus access remaining cycle number is satisfied.

The invention of claim 8 is the bus control device according to claim 7, wherein the predetermined number of predicted external bus access execution cycles includes the shortest number of external bus access execution cycles.

A ninth aspect of the present invention is the bus control device according to any one of the first to eighth aspects, wherein the transfer method instruction unit is the normal transfer method or the burst method. It includes a DMA transfer information storage unit for giving DMA transfer information including transfer method information for instructing transfer to the bus control unit.

[0057]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Preferred Embodiment> FIG. 1 is a block diagram showing a configuration of a bus control device according to a first preferred embodiment of the present invention. As shown in the figure, the bus control device 1
Register group 2, bus control unit 51, and DMA request detection unit 6
0, and uses the system clock CLK as the operating clock.

The bus controller 51 controls access to the CPU, the outside and the inside by sending and receiving the CPU / I / F signal group 7, the internal bus access signal group 8 and the external bus access signal group 9. The CPU / I / F signal group 7,
The internal bus access signal group 8, the external bus access signal group 9, the register group 2, and the DMA request detection unit 60 are the same as those in the conventional configuration shown in FIG.

The bus control unit 51 has a CPU internal access determination unit 61 inside. The CPU internal access determination unit 61 sets the transfer method register 13 setting value (transfer method information).
On the basis of the
When the MA transfer is the normal transfer method, the CPU internal access request for requesting access to the internal bus by the CPU is permitted during the external bus access of the DMA operation executed in the order of external bus access and internal bus access,
If the DMA transfer is a burst transfer, it is determined that the CPU internal access request is prohibited even during the external bus access.

FIG. 2 shows a normal DMA according to the first embodiment.
It is a timing diagram which shows a transfer operation. Here, the setting value of the transfer source address register 10 is 0x00400000.
(External bus), set value of transfer destination address register 11 is 0x00600000 (internal bus), value of DMA transfer counter 12 is 0x2, value of transfer method register 13 is 0x
It is assumed that it is set to 0 (normal transfer).

In cycle T2, the DMA start request signal dma
_Req becomes "H" and a DMA request is generated. Since the transfer source address is the external address, the bus control unit 51 sets the external access request signal EREQ to "H" (the external read / write control signal ERW maintains "H") from the cycle T3 to perform the external bus access. Start external read access.

In the example of FIG. 2, an internal read access request (the CPU access request signal CREQ is "H" and the CPU read / write control signal CRW is "H") unrelated to the DMA transfer from the CPU is generated in the cycle T4. To do.

At this time, the CPU internal access judging section 61
Indicates that the DMA transfer method is normal, DMA transfer has started, but external access is currently being performed.
The PU access response signal CACK is set to "H", and it is determined that the CPU internal access request in the cycle T4 is accepted. As a result, external read access by DMA transfer and internal read access by CPU are executed in parallel.

At cycle T5, external address 0x004
The data D1 of 00000 is the external read data signal ERD
It is output as ATA, the external access completion signal EDC becomes "H", and the external read access is completed. At the end of this cycle T5, the bus control unit 51 fetches the data D1 of the external read data signal ERDATA into an internal buffer (not shown).

In the cycle T6, the CPU address signal C
Internal address specified by ADDR 0x0061000
The data D10 of 0 is the internal read data signal IRDATA.
Read as the CPU read data signal CR
By being given to the CPU as DATA, the CPU
The internal read access by is completed.

Therefore, the bus control unit 51 uses the cycle T
After the external read access by the DMA transfer is completed in 5, the start of the internal write access which is the internal bus access by the DMA transfer is waited until the completion of the internal read access by the CPU during the cycle T6.

Then, from the cycle T7 after the completion of the internal read access by the CPU, the bus control section 51 sets the internal access request signal IREQ to "H" and the internal read / write control signal IRW to "L" to perform the internal DMA transfer. Start write access.

The internal write data signal IWDATA includes
The data D1 stored in the buffer inside the bus control unit 51 is output. As a result, the internal address 0x0060
The data D1 is written in 0000. Then, in cycle T8, the internal access completion signal IDC becomes "H",
Internal write access is completed.

In the example of FIG. 2, another internal bus access request is further issued from the CPU in cycle T7, but since the internal bus access for DMA transfer is already being executed,
The bus control unit 51 does not accept this request.

Since the value of the DMA transfer counter 12 is 0x2, the bus controller 51 starts the second external read access in cycle T9. At the same time, the CPU access response signal CACK is set to "H" to accept the CPU internal access request, and the internal read access from the CPU is started. That is, the second external read access by the DMA transfer and the second internal read access by the CPU are executed in parallel.

In cycle T10, CPU address signal C
Internal address specified by ADDR 0x0062000
The data D20 of 0 is the internal read data signal IRDATA.
CPU read data signal CRD after being read as
By being given to the CPU as ATA, the internal bus access from the CPU is completed.

In cycle T11, the external address 0x00
The data D2 of 400004 is the external read data signal ER.
The data is output as DATA, and the second external read access of DMA is completed.

From the cycle T12, the bus control unit 51 becomes 2
Start the internal write access for the second time. Cycle T13
Then, the internal write access for writing the data D2 to the internal address 0x00600004 is completed, and the DMA transfer is completed.

On the other hand, the set value of the transfer method register 13 is 0.
In the case of x1 (burst transfer), the CPU internal access determination unit 61 prohibits the CPU internal access request for the DMA transfer start number as in the conventional operation shown in FIG.

As described above, in the bus controller of the first embodiment, when the DMA transfer is the normal transfer operation, the external bus access and the internal bus access are executed in this order even during the execution of the DMA transfer operation. Since the internal bus access request from the CPU is permitted when the external bus access operation is being executed, the cycle of the internal bus can be effectively used and the bus control device 1 with a small overhead can be obtained.

<Second Embodiment> FIG. 3 is a block diagram showing a structure of a bus control device according to a second embodiment of the present invention. As shown in the figure, the bus control device 1 is composed of a register group 2, a bus control unit 52, a DMA request detection unit 60, an internal address table 70, and an external access counter 80, and uses a system clock CLK as an operation clock. .

FIG. 4 is an explanatory diagram showing the internal structure of the internal address table 70. As shown in the figure, the reference internal addresses start_addr1 [31: 0] to start.
Mask bit ma corresponding to t_addr4 [31: 0]
sk_bit1 [31: 0] to mask_bit4 [3
1: 0], read access cycle numbers r1 to r4, and write access cycle numbers w1 to w4 are set, respectively.

By using this internal address table 70, it is possible to recognize the correct number of execution cycles of the CPU internal bus access according to the internal address value and the access mode (read, write).

The external access counter 80 is the bus controller 5
The external access count value initial value setting unit 72 of 2 sets a predetermined initial value as the external access count value ext_counter, which is the number of cycles remaining in the external bus access, and sets the external access count value ext_counter to 1 for each cycle of the system clock CLK. Decrement.

The bus control unit 52 controls access to the CPU, the outside and the inside by sending and receiving the CPU / I / F signal group 7, the internal bus access signal group 8 and the external bus access signal group 9. The CPU / I / F signal group 7,
The internal bus access signal group 8, the external bus access signal group 9, the register group 2, and the DMA request detection unit 60 are the same as those in the conventional configuration shown in FIG.

The bus control unit 52 has a CPU internal access determination unit 62 inside. The CPU internal access determination unit 62 determines whether the DMA based on the set value of the transfer method register 13
The DMA transfer method is recognized at startup, and the following operation is executed when the DMA transfer is normal transfer.

After the CPU internal access judging unit 62 recognizes the internal access cycle number ic which is the CPU internal bus execution cycle number by referring to the internal address table 70 based on the access mode (read, write) and the internal address value. , The internal access cycle number ic is compared with the external access count value ext_counter, and the internal access cycle number ic is compared with the external access count value ext_counter.
If it is less than or equal to the counter, it is determined that the CPU internal access request is accepted.

Hereinafter, a method of recognizing the internal access cycle number ic using the internal address table 70 shown in FIG. 4 will be described in detail.

When there is a CPU internal access request, C
A logical product ANDn = {CADDDR [31: 0] & (~ (mask) of the PU address signal CADDDR [31: 0] and the mask bits mask_bitn [31: 0] (n = 1 to 4).
_Bitn [31: 0]))} ("&" is a logical product, "~"
Is the inversion value).

Then, the logical products AND1 to AND4 and the reference start addresses start_addr1 to star.
By comparing with t_addr4, the number of cycles of the access mode corresponding to the matched reference start address is set as the internal access cycle number ic.

For example, AND2 and start_addr
When 2 [31: 0] matches and is in read mode,
The cycle number r2 is the internal access cycle number ic,
It is recognized by the CPU internal access determination unit 62.

FIG. 5 shows a normal DMA according to the second embodiment.
It is a timing diagram which shows a transfer operation. Here, the setting value of the transfer source address register 10 is 0x00400000.
(External bus), set value of transfer destination address register 11 is 0x00600000 (internal bus), value of DMA transfer counter 12 is 0x2, value of transfer method register 13 is 0x
It is assumed that it is set to 0 (normal transfer).

Further, the shortest cycle number of external read access is set to "4" in the bus control unit 52. It is assumed that the internal address table 70 is set so that the number of internal read accesses to the internal address 0x00610000 is “3” and the number of internal read accesses to the internal address 0x00620000 is “2”.

In cycle T2, the DMA start request signal dma
_Req becomes "H" and a DMA request is generated. Since the transfer source address is the external address, the bus control unit 52 sets the external access request signal EREQ to "H" (maintains the external read / write control signal ERW to "H") from cycle T3 to start the external read access. To do.

At this time, the external access count value initial value setting section 72 sets the external access count value ext_counte to "4" which is the shortest cycle number of the external read access.
Initialize as r.

In the example of FIG. 5, an internal read access request (CPU access request signal CREQ is "H", CPU read / write control signal CRW is "H") unrelated to the DMA transfer from the CPU is generated in cycle T3. To do.

At this time, the CPU internal access judging section 62
Recognizes that the internal access cycle number ic becomes “3” by referring to the internal address table 70, and the internal access cycle number ic and the external access count value ext.
Compare with _counter. As a result, the CPU internal access determination unit 62 determines that the internal read access of the CPU is accepted because the two are the same and satisfy the CPU internal access acceptance condition “ic ≦ ext_counter”.

Therefore, the bus control unit 52 sets the CPU access response signal CACK to "H" in the cycle T3 and accepts the internal access by the CPU in the cycle T3. As a result, external read access by DMA transfer and internal read access by CPU are executed in parallel.

Thereafter, in cycle T6, the external address 0
The data D1 of x00400000 is output as the external read data signal ERDATA, the external access completion signal EDC of the DMA transfer becomes "H", and the external read access is completed. At the end of this cycle T6, the bus control unit 52 outputs the data D1 of the external read data signal ERDATA.
To the internal buffer.

On the other hand, in the internal read access by the CPU, in cycle T5, the data D10 of the internal address 0x00610000 designated by the CPU address signal CADDDR is read as the internal read data signal IRDATA, and is further read to the CPU as the CPU read data signal CRDATA. By being granted, the internal read access by the CPU is completed.

Therefore, the bus control unit 52 uses the cycle T
After the external read access by DMA transfer is completed in 6, the internal access request signal IREQ is set to "H" and the internal read / write control signal IRW is set to "L" in the next cycle T7 to start the internal write access.

The internal write data signal IWDATA includes
The data D1 stored in the buffer inside the bus control unit 52 is output. As a result, the internal address 0x0060
The data D1 is written in 0000. Then, in cycle T8, the internal access completion signal IDC becomes "H",
Internal write access is completed.

Since the value of the DMA transfer counter 12 is 0x2, the bus controller 52 starts the second external read access in cycle T9. At the same time, the external access count value initial value setting unit 72 sets “4”, which is the shortest cycle number of external read access, to the external access count value ext.
Initialize again as _counter.

In the example shown in FIG. 5, in cycle T12, the CPU
Another internal bus access request is generated from.

At this time, the CPU internal access judging section 62
Recognizes that the internal access cycle number ic when reading to the internal address 0x00620000 is “2” by referring to the internal address table 70, and determines the internal access cycle number ic and the external access count value ext_counter in the cycle T11. To compare. As a result, the CPU internal access determination unit 62 determines that “ic (=
2)> ext_counter (= 1) ”, and the CPU
Internal access acceptance condition “ic ≦ ext_counter”
Therefore, it is determined that the CPU internal bus access request is not accepted.

At cycle T12, the external address 0x00
The data D2 of 400004 is the external read data signal ER.
The data is output as DATA, and the second external read access of DMA is completed.

From cycle T13, the bus control unit 52 outputs 2
Start the internal write access for the second time. Cycle T14
Then, the internal write access for writing the data D2 to the internal address 0x00600004 is completed, and the DMA transfer is completed.

Then, in cycle T15, the CPU access response signal CACK is set to "H" to accept the CPU access (read access), and the internal bus access from the CPU is started.

In cycle T16, the CPU address signal C
Internal address specified by ADDR 0x0062000
The data D20 of 0 is the internal read data signal IRDATA.
CPU read data signal CRD after being read as
By being given to the CPU as ATA, the internal bus access from the CPU is completed.

Returning to FIG. 3, the CPU internal access judging section 62 judges as follows when the set value of the transfer method register 13 is 0x1 (burst transfer).

When there is a CPU internal access request at the time of external read access of the first data (corresponding to the data D1 in FIG. 15), the CPU internal access determination unit 62 determines the internal access cycle number ic as described above. Based on the result of comparison with the external access count value ext_counter, the CPU internal access determination unit 62 determines whether to accept an internal access request from the CPU.

Further, the CPU internal access judging section 62
When an internal access request is issued from the CPU during the external read access of the second and subsequent data (corresponding to the data D2 to D4 in FIG. 15), the external access count value ext_counter is set to “0” regardless of the external access counter 80. It is determined that the internal access request from the CPU is not accepted unconditionally.

FIG. 6 shows burst DMA according to the second embodiment.
It is a timing diagram which shows a transfer operation. Here, the setting value of the transfer source address register 10 is 0x00400000,
The setting value of the transfer destination address register 11 is 0x00600
000 (internal bus), the value of the DMA transfer counter 12 is 0
x4, the value of the transfer method register 13 is 0x1 (burst transfer).

The shortest cycle number of external read access to the first data in the bus control unit 52 is set to "4". The number of internal read accesses to internal address 0x006100000 is "3", internal address 0x00
It is assumed that the internal address table 70 is set so that the number of internal read accesses to 620000 is “3”.

In cycle T2, the DMA start request signal dma
_Req becomes "H" and a DMA request is generated. Since the transfer source address is an external address, the bus control unit 50 sets the external access request signal EREQ to "H" (the external read / write control signal ERW maintains "H") from cycle T3 to start the external read access. To do. At the same time, since the value of the transfer method register 13 is 0x1 (burst transfer), the bus control unit 50 sets the external access burst request signal EBURST to "H".

In the example of FIG. 6, an internal read access request (CPU access request signal CREQ is "H", CPU read / write control signal CRW is "H") unrelated to the DMA transfer from the CPU is generated in cycle T3. To do.

At this time, the CPU internal access judging section 62
In the cycle T3, since the burst transfer is the access feedback for the first data of the external bus, the internal access cycle number ic becomes "3" by referring to the internal address table 70 as in the normal transfer. It recognizes and compares the internal access cycle number ic with the external access count value ext_counter. As a result, the CPU internal access determination unit 62 is
CPU internal access acceptance condition “ic ≦ ext_count
er ”is satisfied, it is determined that the CPU internal read access request is accepted.

Therefore, the bus control unit 52 sets the CPU access response signal CACK to "H" in cycle T3 and accepts the internal access by the CPU in cycle T3. As a result, external read access by DMA transfer and internal read access by CPU are executed in parallel.

In the internal read access by the CPU, the data D10 of the internal address 0x00610000 designated by the CPU address signal CADDDR is read as the internal read data signal IRDATA in the cycle T5.
In addition, CP as CPU read data signal CRDATA
By being added to U, the internal read access by the CPU is completed.

On the other hand, in cycle T6, the external address 0x
The data D1 of 00400000 is output as the external read data signal ERDATA, and the external access completion signal E
DC becomes "H", and the external read access to the data D1 is completed. At the end of this cycle T6, the bus controller 52 fetches the data D1 of the external read data signal ERDATA into the internal buffer.

From cycle T6 to cycle T9, 0x00400000 and 0x00400 are continuously output from the external bus.
004, 0x00400008, and 0x004000
Data D1, D2, D3 of the external address in the order of 0c
And D4 are read. Since the value of the DMA transfer counter 12 is 0x4, the external access request signal ER is generated in the next cycle T10 after the completion of the fourth external read access.
EQ and external access burst request signal EBURST
To "L".

On the other hand, the write access to the internal bus is 0x00600000, 0x006 from the cycle T7 following the first read data D1 read from the external bus.
00004, 0x00600008, and 0x0060
The data D1, D2, D3 and D4 are written in the order of 000c, and the write access is completed in cycle T10.

In the example of FIG. 6, another internal bus access request is further issued from the CPU in cycle T8.

At this time, the CPU internal access judging section 62
Since the burst transfer is not at the time of accessing the first data of the external bus, it is judged unconditionally that the internal read access of the CPU is not accepted.

Therefore, in the cycle T11 after the completion of the write access during the burst transfer, the bus control unit 50 sets the CPU access response signal CACK to "H".
The access is accepted and the internal bus access from the CPU is started. Internal address 0 from CPU in cycle T13
The CPU internal bus access for reading the data D20 of x00610000 is completed.

In this way, the CPU internal access judging section 6
2, the DMA burst transfer operation is executed while permitting or prohibiting the CPU or the internal bus access request.

As described above, in the bus control device according to the second embodiment, when the DMA transfer is the normal transfer method and the external bus access operation is being executed even if the DMA transfer operation is being started, the internal operation from the CPU is performed. Based on the comparison between the number of bus access cycles and the external access count value ext_counter, the CPU internal bus access request is permitted / prohibited by C.
Since the PU internal access determination unit 62 makes a determination, the internal bus access type (difference in address, access mode type (read, write)) is taken into consideration, and the cycle of the internal bus is effectively used without causing any trouble in operation. You can do it.

In addition, the bus control device according to the second embodiment is
When the DMA transfer is a burst transfer method and the external bus access operation for the first unit of data is being executed even when the DMA transfer operation is started, the number of cycles of the internal bus access from the CPU and the external access count value ext_
Based on the comparison with the counter, the CPU internal bus access request is permitted / prohibited is determined by the CPU internal access determination unit 62. Therefore, in consideration of the internal bus access type, the cycle of the internal bus is determined without causing any trouble in the operation. It can be effectively used.

<Third Embodiment> FIG. 7 is a block diagram showing a structure of a bus control device according to a third embodiment of the present invention. As shown in the figure, the bus control device 1 is composed of a register group 2, a bus control unit 53, a DMA request detection unit 60, an internal address table 70, and an external access counter 80, and uses a system clock CLK as an operation clock. .

The bus controller 53 controls access to the CPU, the outside and the inside by sending and receiving the CPU / I / F signal group 7, the internal bus access signal group 8 and the external bus access signal group 9a. The CPU / I / F signal group 7, the internal bus access signal group 8, the register group 2, the DMA request detecting unit 60, and the internal address table 70.
The external access counter 80 and the external access counter 80 are the same as those in the second embodiment shown in FIG.

The external bus access signal group 9a has the same signals as the external bus access signal group 9, and further has an external access cycle signal ECYCLE (CYCLE [31: 0]).
You are typing. External access cycle signal ECYCL
E is a signal indicating the number of external access execution cycles for setting the external access count value ext_counter of the external access counter 80.

The external access count value initial value setting unit 73 of the bus control unit 53 uses the external access cycle signal ECYC.
The number of external access execution cycles instructed by LE is the external access count value ext_c of the external access counter 80.
Initialize as unter.

The bus control unit 53 has a CPU internal access determination unit 63 inside. The CPU internal access determination unit 63 determines whether the DMA based on the set value of the transfer method register 13
The DMA transfer method is recognized at startup, and the following operation is executed when the DMA transfer is normal transfer.

The CPU internal access judging section 63 is similar to the CPU internal access judging section 62 of the second embodiment in that the DMA
When there is a CPU internal access request during the external bus access of the transfer operation, the internal address table 7 is based on the access mode (read, write) and the internal address value.
After recognizing the internal access cycle number ic by referring to 0, the internal access cycle number ic is compared with the external access count value ext_counter, and the internal access cycle number ic is determined to be the external access count value ext_cun.
If ter or less, it is determined that the internal access from the CPU is accepted.

FIG. 8 shows a normal DMA according to the third embodiment.
It is a timing diagram which shows a transfer operation. Here, the setting value of the transfer source address register 10 is 0x00400000.
(External bus), set value of transfer destination address register 11 is 0x00600000 (internal bus), value of DMA transfer counter 12 is 0x2, value of transfer method register 13 is 0x
It is assumed that it is set to 0 (normal transfer).

Further, the internal address 0x00610000
The number of internal read accesses to 0 is “3”, internal address 0
The number of internal read accesses to x00620000 is "2"
It is assumed that the internal address table 70 is set so that

In cycle T2, the DMA start request signal dma
_Req becomes "H" and a DMA request is generated. Since the transfer source address is the external address, the bus control unit 53 sets the external access request signal EREQ to "H" (maintains the external read / write control signal ERW to "H") from cycle T3 to start the external read access. To do.

At the same time, the external access count value initial value setting unit 73 sets the external access count value ex based on the external access cycle signal ECYCLE instructing "4".
“4” is initially set in the external access counter 80 as t_counter.

In the example of FIG. 8, an internal read access request (CPU access request signal CREQ is "H", CPU read / write control signal CRW is "H") unrelated to DMA transfer from the CPU is generated in cycle T3. To do.

At this time, the CPU internal access judging section 63
Recognizes that the internal access cycle number ic becomes “3” by referring to the internal address table 70, and the internal access cycle number ic and the external access count value ext.
Compare with _counter. As a result, the CPU internal access determination unit 63 determines that “ic (= 3) <xt_count.
er (= 4) ”and the CPU internal access acceptance condition“ ic ≦ ext_counter ”is satisfied, CP
It is determined whether the internal read access of U is accepted.

Therefore, bus control unit 53 sets CPU access response signal CACK to "H" in cycle T3 and accepts internal access by the CPU in cycle T3. As a result, external read access by DMA transfer and internal read access by CPU are executed in parallel.

Thereafter, in cycle T6, the external address 0
The data D1 of x00400000 is output as the external read data signal ERDATA, the external access completion signal EDC becomes "H", and the external read access is completed. At the end of this cycle T6, the bus controller 53 fetches the data D1 of the external read data signal ERDATA into the internal buffer.

On the other hand, in the internal read access by the CPU, in cycle T5, the data D10 of the internal address 0x00610000 designated by the CPU address signal CADDDR is read as the internal read data signal IRDATA, and further as the CPU read data signal CRDATA to the CPU. By being granted, the internal read access by the CPU is completed.

Therefore, the bus control unit 53 uses the cycle T
After the external read access by the DMA transfer is completed in 6, the internal access request signal IR is immediately sent in the next cycle T7.
The EQ is set to "H" and the internal read / write control signal IRW is set to "L" to start the internal write access.

The internal write data signal IWDATA includes
The data D1 stored in the buffer inside the bus control unit 53 is output. As a result, the internal address 0x0060
The data D1 is written in 0000. Then, in cycle T8, the internal access completion signal IDC becomes "H",
Internal write access is completed.

Since the value of the DMA transfer counter 12 is 0x2, the bus controller 53 starts the second external read access in cycle T9. At the same time, the external access count value initial value setting unit 73 sets the external access count value ext_ based on the external access cycle signal ECYCLE.
The external access counter 80 is "4" as a counter.
Initialize to.

In the example shown in FIG. 8, the CPU is used in the cycle T12.
Another internal bus access request is generated from.

At this time, the CPU internal access judging section 63
Recognizes that the internal access cycle number ic when reading to the internal address 0x00620000 is “2” by referring to the internal address table 70, and determines the internal access cycle number ic and the external access count value ext_counter in the cycle T12. To compare. As a result, the CPU internal access determination unit 63 determines that “ic (=
2)> ext_counter (= 1) ”, and the CPU
Internal access acceptance condition “ic ≦ ext_counter”
Therefore, it is determined that the CPU internal bus access request is not accepted.

At cycle T12, external address 0x00
The data D2 of 400004 is the external read data signal ER.
The data is output as DATA, and the second external read access of DMA is completed.

From the cycle T13, the bus control unit 53 becomes 2
Start the internal write access for the second time. Cycle T14
Then, the internal write access for writing the data D2 to the internal address 0x00600004 is completed, and the DMA transfer is completed.

Thereafter, in cycle T15, the CPU access response signal CACK is set to "H" to accept the CPU access (read access), and the internal bus access from the CPU is started.

In the cycle T16, the CPU address signal C
Internal address specified by ADDR 0x0062000
The data D20 of 0 is the internal read data signal IRDATA.
CPU read data signal CRD after being read as
By being given to the CPU as ATA, the internal bus access from the CPU is completed.

Returning to FIG. 7, the CPU internal access judging section 62 judges as follows when the set value of the transfer method register 13 is 0x1 (burst transfer).

If there is a CPU internal access request at the time of external read access of the first data (corresponding to the data D1 in FIG. 6), the CPU internal access determination unit 63 executes the processing shown in FIG.
As in the burst DMA transfer operation shown by, the internal access cycle number ic and the external access count value ext_c
The CPU internal access determination unit 62 determines whether or not to accept the CPU internal access request based on the result of the comparison with the unter.

Further, the CPU internal access judging section 63 is
Data after the second time (corresponding to data D2 to D4 in FIG. 6)
If there is an internal access request from the CPU during the external read access of the external access count value ext_c
Unter is regarded as “0”, and it is judged unconditionally that the CPU internal access request is not accepted.

In this way, the CPU internal access determination unit 6
3, the DMA burst transfer operation is executed while permitting or prohibiting the internal bus access request from the CPU.

As described above, the bus control device according to the third embodiment performs the DMA transfer when the DMA transfer is the normal transfer operation.
If the external bus access operation is being executed even though the transfer operation is started, the CPU internal bus access request is permitted / prohibited based on the comparison between the number of cycles of the internal bus access from the CPU and the external access count value ext_counter. Since the determination is performed by the CPU internal access determination unit 63, it is possible to effectively use the cycle of the internal bus in consideration of the internal bus access type without causing a hindrance to the operation.

In addition, the bus control device according to the third embodiment is
When the DMA transfer is a burst transfer method and the external bus access operation for the first unit of data is being executed even when the DMA transfer operation is started, the number of cycles of the internal bus access from the CPU and the external access count value ext_
Based on the comparison with the counter, whether the CPU internal bus access request is permitted or prohibited is determined by the CPU internal access determination unit 63. Therefore, in consideration of the internal bus access type, the cycle of the internal bus can be determined without causing any trouble in the operation. It can be effectively used.

Further, the CPU internal access judging section 63.
By setting the external access count value ext_counter based on the external access cycle signal ECYCLE, it is possible to make a determination by accurately recognizing the number of cycles remaining in the external bus access.

<Fourth Preferred Embodiment> FIG. 9 is a block diagram showing a structure of a bus control device according to a fourth preferred embodiment of the present invention. As shown in the figure, the bus control device 1 is composed of a register group 2, a bus control unit 54, a DMA request detection unit 60, an internal address table 70, an external access counter 80, and an internal access counter 90. It is used as an operating clock.

The bus control section 54 controls access to the CPU, the outside and the inside by transmitting and receiving the CPU / I / F signal group 7, the internal bus access signal group 8 and the external bus access signal group 9a. The CPU / I / F signal group 7, the internal bus access signal group 8, the external bus access signal group 9, the register group 2, the DMA request detection unit 60,
Internal address table 70 and external access counter 8
Since 0 is the same as that of the third embodiment shown in FIG. 7, description thereof will be omitted.

The bus control unit 54 has a CPU internal access determination unit 64, an external access count value initial value setting unit 74, an internal access count value initial value setting unit 84, and a DMA access determination unit 94 inside.

External access count value initial value setting unit 74
Indicates the number of external access execution cycles designated by the external access cycle signal ECYCLE.
The external access count value ext_counter of 0 is initialized.

The CPU internal access judging section 64 determines the DMA at the time of starting the DMA based on the set value of the transfer method register 13.
The transfer system is recognized, and the following operation is executed when the DMA transfer is the normal transfer.

The CPU internal access determination unit 64 uses the DMA
During the external bus access for transfer, C of the second embodiment
Similar to the PU internal access determining unit 62, the internal access cycle number i is referred to by referring to the internal address table 70 based on the access mode (read, write) and the internal address value.
After recognizing c, the internal access cycle number ic is compared with the external access count value ext_counter, and the internal access cycle number ic is compared with the external access count value e.
If xt_counter or less, it is determined that the CPU internal access request is accepted.

Further, the internal access count value initial value setting unit 84 refers to the internal address table 70 based on the access mode and the internal address value in the same manner as the CPU internal access determination unit 64, and the internal access cycle number i
c is recognized and the internal access cycle number ic is set to the internal access count value in_cun of the internal access counter 90.
Initially set as ter (the number of remaining cycles of CPU internal bus access). Since the internal access count value initial value setting unit 84 has many functions that overlap with the CPU internal access determination unit 64, the internal access count value initial value setting unit 84 is configured to have the function of the CPU internal access determination unit 64. You may.

If there is a DMA request executed in the order of external bus access and internal bus access during execution of internal bus access by the CPU, the DMA access determination unit 94
A predetermined external bus access predicted execution cycle number (for example, the shortest external bus access cycle number) is compared with the internal access count value in_counter,
"External bus access prediction execution cycle number ≤ in_cun
When it is “ter”, it is determined to accept the DMA request.

The internal access counter 90 sets the internal access count value in_counter to 1 every bus cycle.
Decrement.

FIG. 10 shows a normal DM according to the fourth embodiment.
FIG. 7 is a timing diagram showing an A transfer operation. Here, the setting value of the transfer source address register 10 is 0x00400000.
(External bus), set value of transfer destination address register 11 is 0x00600000 (internal bus), value of DMA transfer counter 12 is 0x2, value of transfer method register 13 is 0x
It is assumed that it is set to 0 (normal transfer).

Also, the internal address 0x00610000
Number of internal read accesses to 0 is "5", internal address 0
The number of internal read accesses to x00620000 is "2"
The internal address table 70 is set so that
It is assumed that the number of external bus access prediction execution cycles preset in the DMA access determination unit 94 is set to "2".

In the example shown in FIG. 10, the CPU is used in the cycle T1.
Internal read access request from CPU (CPU access request signal CREQ is “H”, CPU read / write control signal C
RW is “H”).

Therefore, the bus control unit 54 does not issue a DMA request in cycle T1, so
Then, the CPU access response signal CACK is set to "H" to accept the internal access by the CPU in the cycle T1.
At this time, the internal access count value initial value setting unit 84 initializes the internal access cycle number ic (= “5”) in the internal access counter 90 as the internal access count value in_counter.

After that, in cycle T5, the internal address 0x0061 designated by the CPU address signal CADDDR is set.
The data D10 of 0000 is the internal read data signal IRD
By being read as ATA and further given to the CPU as the CPU read data signal CRDATA,
The internal read access by the CPU is completed.

On the other hand, in cycle T2, the DMA start request signal dma_req becomes "H" and a DMA request is generated. At this time, the DMA access determination unit 94 compares the internal access count value in_counter with the external bus access prediction execution cycle number, and the internal access count value in_counter is “4” and the external bus access prediction execution cycle number is “2”. Therefore, since the acceptance condition “external bus access prediction execution cycle number ≦ in_counter” is not satisfied, it is determined that the DMA request is not accepted.

Thereafter, in cycle T4, the internal access count value in_counter becomes "2", and the acceptance condition "external bus access predicted execution cycle number≤in_cun" is reached.
ter ”is satisfied, the DMA access determination unit 94
Accepts a DMA request.

Since the transfer source address is the external address, the bus control unit 54 sets the external access request signal EREQ to "H" from the cycle T4 (maintains the external read / write control signal ERW to "H"), and the external read Start access.

At the same time, the external access count value initial value setting unit 74 determines the external access count value ex based on the external access cycle signal ECYCLE instructing "3".
Initialize "3" in the external access counter 80 as t_counter.

Therefore, in cycles T4 to T5, external read access by DMA transfer and internal read access by CPU are executed in parallel.

Then, in cycle T6, the external address 0
The data D1 of x00400000 is output as the external read data signal ERDATA, the external access completion signal EDC becomes "H", and the external read access is completed. At the end of this cycle T6, the bus controller 54 fetches the data D1 of the external read data signal ERDATA into the internal buffer.

After the external read access by the DMA transfer is completed in the cycle T6, the bus control unit 54 completes the next cycle T.
At 7, the internal access request signal IREQ is set to "H" and the internal read / write control signal IRW is set to "L" to start the internal write access.

The internal write data signal IWDATA includes
The data D1 stored in the buffer inside the bus control unit 54 is output. As a result, the internal address 0x0060
The data D1 is written in 0000. Then, in cycle T8, the internal access completion signal IDC becomes "H",
Internal write access is completed.

Since the value of the DMA transfer counter 12 is 0x2, the bus controller 54 starts the second external read access in cycle T9. At the same time, the external access count value initial value setting unit 74 sets the external access count value ext_ based on the external access cycle signal ECYCLE.
The external access counter 80 is "4" as a counter.
Initialize to.

In the example of FIG. 10, CP is included in cycle T12.
Another internal bus access request is issued from U.

At this time, the CPU internal access judging section 64
Recognizes that the internal access cycle number ic when reading to the internal address 0x00620000 is “2” by referring to the internal address table 70, and determines the internal access cycle number ic and the external access count value ext_counter in the cycle T12. To compare. As a result, the CPU internal access determination unit 64 determines that “ic (=
2)> ext_counter (= 1) ”, and the CPU
Internal access acceptance condition “ic ≦ ext_counter”
Therefore, it is determined that the internal read access of the CPU is not accepted.

At cycle T12, the external address 0x00
The data D2 of 400004 is the external read data signal ER.
The data is output as DATA, and the second external read access of DMA is completed.

From the cycle T13, the bus control unit 54 becomes 2
Start the internal write access for the second time. Cycle T14
Then, the internal write access for writing the data D2 to the internal address 0x00600004 is completed, and the DMA transfer is completed.

Thereafter, in cycle T15, the CPU access response signal CACK is set to "H" to accept the CPU access (read access), and the internal bus access from the CPU is started. At this time, the internal access count value initial value setting unit 84 sets the internal access cycle number ic (=
"2") as the internal access count value in_counter
Is initialized in the internal access counter 90.

In cycle T16, the CPU address signal C
Internal address specified by ADDR 0x0062000
The data D20 of 0 is the internal read data signal IRDATA.
CPU read data signal CRD after being read as
By being given to the CPU as ATA, the internal bus access from the CPU is completed.

Further, the DMA access judgment unit 94 does not take the setting value of the transfer method register 13 into consideration,
Even if the DMA request is a burst transfer, when the number of predicted external bus access execution cycles falls below the internal access count value in_counter because the DMA request is determined to be permitted or prohibited during the internal bus access by
Allowed

Returning to FIG. 9, the CPU internal access judging section 64 judges in the same manner as in the third embodiment when the set value of the transfer method register 13 is 0x0 (normal transfer).

The set value of the transfer method register 13 is 0.
Also in the case of x1 (burst transfer), determination is performed as follows, as in the third embodiment.

When the CPU internal access request is made during the external bus access of the first data (corresponding to the data D1 of FIG. 6),
As shown in FIG. 6, the CPU internal access determination unit 62 determines that the CPU internal access determination unit 62 determines whether the CPU internal access cycle count ic is compared with the external access count value ext_counter.
It is determined whether or not to accept the internal access request from.

Further, the CPU internal access judging section 64 is
Data after the second time (corresponding to data D2 to D4 in FIG. 6)
If there is an internal access request from the CPU during the external read access of the external access count value ext_c
Unter is regarded as “0”, and it is judged unconditionally that the internal access request from the CPU is not accepted.

As described above, the CPU internal access determination unit 6
4, the DMA burst transfer operation is executed while permitting or prohibiting the internal bus access request from the CPU.

As described above, the bus control device according to the fourth embodiment performs the DMA transfer when the DMA transfer is the normal transfer operation.
If the external bus access operation is being executed even if the transfer operation is started, based on the comparison between the number of cycles of the internal bus access from the CPU and the external access count value ext_counter (the number of remaining external bus access cycles),
CP for permitting / prohibiting internal bus access request from CPU
Since the determination is made by the U internal access determination unit 64, it is possible to effectively use the cycle of the internal bus in consideration of the internal bus access type) without causing a hindrance to the operation.

The bus control device according to the fourth embodiment is D
When the MA transfer is a burst transfer method and the external bus access operation for the first unit of data is being executed even when the DMA transfer operation is started, the cycle number of the internal bus access from the CPU and the external access count value ext_c
Since the CPU internal access determination unit 62 determines whether to permit / prohibit the CPU internal bus access request based on the comparison with the unter, in consideration of the internal bus access type,
The cycle of the internal bus can be effectively used without causing any trouble in the operation.

Further, the CPU internal access judging section 64 is
By setting the external access count value ext_counter based on the external access cycle signal ECYCLE, it is possible to make a determination by accurately recognizing the number of remaining cycles of external bus access.

In addition, according to the fourth embodiment, when a DMA request is executed in the order of external bus access and internal bus access during execution of CPU internal access, internal access count value in_counter and external bus access prediction execution. By comparing with the number of cycles, DM is generated without waiting for completion of CPU internal bus access when a DMA request occurs.
Since the A transfer operation can be executed, the utilization of the internal bus can be further improved.

Furthermore, if the shortest number of external bus access execution cycles is used as the number of predicted external bus access execution cycles, the internal bus access for DMA transfer is always executed after the CPU internal bus access. Even if the transfer is executed, there is no problem in the operation.

[0195]

As described above, the CPU internal access determination unit of the bus controller according to the first aspect of the present invention executes the normal transfer type DMA transfer executed in the order of external bus access to internal bus access. At times, by permitting the CPU internal access request during the external bus access, which has been conventionally prohibited, the internal bus can be effectively used without hindering the operation.

In the bus control device according to the second aspect, when the DMA transfer is the burst transfer method, the CPU internal access request is unconditionally prohibited during the external bus access, so that the burst is generated even when the CPU internal access request is generated. There is no problem in the DMA transfer operation of the transfer method.

CP in the bus controller according to claim 3
The U internal access determining unit refers to the CP obtained by referring to the internal address table during the normal transfer DMA transfer.
When the condition that the number of U internal bus execution cycles is less than or equal to the number of external bus access remaining cycles is satisfied, the CPU internal access request during the external bus access is permitted, so that the internal transfer can be performed without causing a wait state in the normal transfer method DMA transfer operation. The bus can be used effectively.

CP in the bus controller according to claim 4
The U internal access determining unit determines the CPU internal bus execution cycle number obtained by referring to the internal address table during the external bus access in the DMA transfer of the burst transfer method while the first external bus access is accessing the unit data. When the following conditions are met, CP
Since the U internal access request is permitted, the internal bus can be effectively used without causing a wait state in the DMA transfer of the burst transfer method.

The CPU internal access determination unit of the bus control device according to the fifth aspect can acquire a more accurate number of CPU internal bus execution cycles based on the access mode in addition to the CPU internal address.

The external bus access remaining cycle number initial value setting unit of the bus controller according to claim 6 sets the external bus execution cycle number designated by the external access cycle signal at the start of the external bus access as the external bus access remaining cycle number. Since the initialization is performed, a more accurate external bus access remaining cycle number can be obtained.

DM in the bus control device according to claim 7
When the A access determination unit receives a DMA request executed from the external bus access in the order of the internal bus access during execution of the CPU internal access, the predetermined external bus access predicted execution cycle number is the CPU internal bus access remaining cycle number. When the following conditions are satisfied, the external access of the DMA transfer during the CPU internal bus access is permitted, so that the DMA transfer can be started early.

According to another aspect of the bus controller of the present invention, by using the shortest external bus access execution cycle number as the predetermined external bus access prediction execution cycle number, the CPU
Since the internal bus access for DMA transfer is always executed after the internal bus access is completed, there is no problem in the operation even if the DMA transfer is executed during the CPU internal bus access.

Since the transfer method instruction section of the bus control device according to the ninth aspect includes the information storage section for storing the DMA transfer information including the transfer method information, the DMA transfer method can be preset as the transfer method information. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a bus control device according to a first embodiment of the present invention.

FIG. 2 is a timing diagram showing a normal DMA transfer operation according to the first embodiment.

FIG. 3 is a block diagram showing a configuration of a bus control device according to a second embodiment of the present invention.

FIG. 4 is an explanatory diagram showing an internal configuration of an internal address table of FIG.

FIG. 5 is a timing diagram showing a normal DMA transfer operation according to the second embodiment.

FIG. 6 is a timing diagram showing a burst DMA transfer operation according to the second embodiment.

FIG. 7 is a block diagram showing a configuration of a bus control device according to a third embodiment of the present invention.

FIG. 8 is a timing diagram showing a normal DMA transfer operation according to the third embodiment.

FIG. 9 is a block diagram showing a configuration of a bus control device according to a fourth embodiment of the present invention.

FIG. 10 is a timing diagram showing a normal DMA transfer operation according to the fourth embodiment.

FIG. 11 is a block diagram showing a configuration of a bus control device according to a conventional technique.

FIG. 12 is a timing diagram showing a register write operation in the bus control device.

FIG. 13 is a timing diagram showing an internal bus access operation from the CPU.

FIG. 14 is a timing diagram showing a normal DMA transfer operation according to the prior art.

FIG. 15 is a timing diagram showing a burst DMA transfer operation according to a conventional technique.

[Explanation of symbols]

1 bus control device, 2 register groups, 7 CPU / I /
F signal group, 8 internal bus access signal group, 9, 9a external bus access signal group, 51-54 bus control unit, 61
To 64 CPU internal access determination unit, 70 internal address table, 72 to 74 external access count value initial value setting unit, 80 external access counter, 84 internal access count value initial value setting unit, 90 internal access counter, 94 DMA access determination unit .

Claims (9)

[Claims] 1. A transfer method instructing unit for instructing whether the DMA transfer method is a normal transfer method for transferring data in units of one unit or a burst transfer method for collectively transferring data in a plurality of units, a CPU, and an internal unit. A bus control unit that is signal-connected to each of a bus and an external bus and controls these bus connections, and the bus control unit is configured to execute the DMA transfer executed in the order of external bus access and internal bus access. When the transfer method instructing section instructs the normal transfer method, it has a CPU internal access judging section which permits a CPU internal access request for requesting access to the internal bus by the CPU during the external bus access. The bus control device. 2. The bus control device according to claim 1, wherein the CPU internal access determining unit unconditionally performs the external bus access during the external bus access when the transfer system instructing unit instructs the normal transfer system. C
When the PU internal access request is permitted and the transfer method instructing section instructs the burst transfer method, the C is unconditionally accessed during the external bus access.
A bus controller that prohibits PU internal access requests. 3. The bus control device according to claim 1, further comprising: an external bus access remaining cycle number measuring unit for measuring an external bus access remaining cycle number in the external bus access during the DMA transfer according to an operation clock. The CPU internal access determination unit further includes an internal address table in which a CPU internal address that is a target of a CPU internal access request and a CPU internal bus execution cycle number are stored in association with each other. When instructing a system, the CPU internal bus execution cycle number of the CPU internal address is acquired by referring to the internal address table based on at least the CPU internal address.
When the condition that the number of internal bus execution cycles is equal to or less than the number of external bus access remaining cycles is satisfied, the CPU internal access request during the external bus access is permitted.
Bus controller. 4. The bus control device according to claim 3, wherein the CPU internal access determination unit is configured to, based on at least the CPU internal address, generate the internal address when the transfer system instruction unit instructs the burst transfer system. The CPU internal bus execution cycle number of the CPU internal address is acquired by referring to the table, and the CPU
A bus controller that permits the CPU internal access request during access to the first unit data when the external bus access cycle is equal to or less than the external bus access remaining cycle number. 5. The bus control device according to claim 3, wherein the internal address table includes an access mode including a read mode and a write mode of the CPU internal access request in addition to the CPU internal address. Stored in association with the number of CPU internal bus execution cycles, the CPU internal access determination unit refers to the internal address table based on the CPU internal address and the access mode, and executes the CPU internal bus at the CPU internal address. Bus controller that gets the number of cycles. 6. The bus control device according to any one of claims 3 to 5, wherein the external bus is an external access cycle signal indicating a number of external bus execution cycles of the external bus access. The bus control unit further includes an external bus access remaining cycle number initial value setting unit that initializes the external bus execution cycle number as the external bus access remaining cycle number when the external bus access starts. apparatus. 7. The bus control device according to claim 3, wherein the CPU internal bus access remaining cycle number is measured according to the operation clock. Further comprising a measuring unit, wherein the bus control unit acquires the number of CPU internal bus execution cycles of the CPU internal address by referring to the internal address table based on at least the CPU internal address at the start of the CPU internal bus access, A CPU internal bus access remaining cycle number initial value setting unit for initializing the acquired CPU internal bus execution cycle number as the CPU internal bus access remaining cycle number; and an external bus access from an internal bus access during execution of the CPU internal access. When a DMA request executed in the order of A bus control device further comprising a DMA access determination unit that permits external access of the DMA transfer during the CPU internal bus access when the condition that the number of predicted external bus access execution cycles is equal to or less than the number of remaining cycles of the CPU internal bus access is satisfied. . 8. The bus control device according to claim 7, wherein the predetermined number of predicted external bus access execution cycles includes the shortest number of external bus access execution cycles. 9. The bus control device according to claim 1, wherein the transfer method instructing unit transfers the transfer method information for instructing the normal transfer method or the burst transfer. DMA including
A bus control device including a DMA transfer information storage unit for giving transfer information to the bus control unit.