JP2003174082A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2003174082A JP2003174082A JP2001372227A JP2001372227A JP2003174082A JP 2003174082 A JP2003174082 A JP 2003174082A JP 2001372227 A JP2001372227 A JP 2001372227A JP 2001372227 A JP2001372227 A JP 2001372227A JP 2003174082 A JP2003174082 A JP 2003174082A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- groove
- substrate
- semiconductor
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、一般に、半導体
装置に関するものであり、より特定的には、安価で、ノ
イズの伝搬を低減することができるように改良された半
導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor device, and more particularly to a semiconductor device which is inexpensive and improved so as to reduce noise propagation.
【０００２】この発明は、また、そのような半導体装置
の製造方法に関する。The present invention also relates to a method of manufacturing such a semiconductor device.
【０００３】[0003]
【従来の技術】図１２は、従来の高周波用シリコン半導
体装置の断面図である。シリコン基板１中に、酸化膜層
５が形成されている。酸化膜層５の上に、トレンチ分離
６が形成されている。シリコン基板１の上にトランジス
タのゲート電極２をトランジスタの形成されている。ト
ランジスタに、配線３が接続されている。トランジスタ
や配線間の絶縁のために、シリコン基板１の上に層間絶
縁膜４が形成されている。2. Description of the Related Art FIG. 12 is a sectional view of a conventional high frequency silicon semiconductor device. An oxide film layer 5 is formed in the silicon substrate 1. Trench isolations 6 are formed on the oxide film layer 5. The gate electrode 2 of the transistor is formed on the silicon substrate 1 of the transistor. The wiring 3 is connected to the transistor. An interlayer insulating film 4 is formed on the silicon substrate 1 for insulation between transistors and wirings.
【０００４】このように、従来の高周波用シリコン半導
体装置においては、高抵抗シリコン基板をベースとした
ＳＯＩ（Silicon on Insulator）基板を用い、さらにト
レンチ分離などの分離技術と組合せることにより、クロ
ストークノイズの低減を図っている。すなわち、トレン
チ分離６によって、ノイズを発生する回路ブロックとノ
イズレベルを低く抑えたい回路ブロックを分離し、シリ
コン基板１を伝搬するノイズを低減する構成となってい
る。As described above, in the conventional high-frequency silicon semiconductor device, the crosstalk is achieved by using the SOI (Silicon on Insulator) substrate based on the high-resistance silicon substrate and further combining it with the isolation technique such as trench isolation. We are trying to reduce noise. That is, the trench isolation 6 separates a circuit block that generates noise from a circuit block whose noise level is desired to be kept low, and reduces the noise that propagates through the silicon substrate 1.
【０００５】[0005]
【発明が解決しようとする課題】このような高周波用シ
リコン半導体装置は、送受信用の数ＧＨｚ帯の高周波を
発生するものであり、携帯電話、無線ローカルエリアネ
ットワーク、その他の高速通信用機器などに利用されて
いる。Such a high-frequency silicon semiconductor device generates a high-frequency wave of several GHz for transmission and reception, and is used in mobile phones, wireless local area networks, and other high-speed communication equipment. It's being used.
【０００６】従来の高周波用シリコン半導体装置は、以
上のように構成されている。ＳＯＩ基板はイオン注入あ
るいはシリコン基板の貼り合わせ、研磨など複雑な工程
を経て製造されるため、従来のシリコン基板に対して、
価格が高いというデメリットがある。The conventional high-frequency silicon semiconductor device is constructed as described above. Since the SOI substrate is manufactured through complicated processes such as ion implantation, bonding of silicon substrates, and polishing, compared to conventional silicon substrates,
It has the disadvantage of being expensive.
【０００７】この発明は、上記のような問題点を解決す
るためになされたもので、安価に作ることができるよう
に改良された高周波用シリコン半導体装置を提供するこ
とを目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to provide an improved high frequency silicon semiconductor device which can be manufactured at low cost.
【０００８】この発明の他の目的は、安価な方法で、シ
リコン基板を伝搬するノイズを低減することができるよ
うに改良された半導体装置を提供することにある。Another object of the present invention is to provide an improved semiconductor device capable of reducing noise propagating through a silicon substrate in an inexpensive manner.
【０００９】この発明の他の目的は、そのような半導体
装置の製造方法を提供することにある。Another object of the present invention is to provide a method of manufacturing such a semiconductor device.
【００１０】[0010]
【課題を解決するための手段】請求項１に係る半導体装
置は、半導体基板と、該半導体基板を上下に貫通する溝
と、該半導体基板の上に形成された半導体素子とを備え
る。A semiconductor device according to a first aspect of the present invention includes a semiconductor substrate, a groove vertically penetrating the semiconductor substrate, and a semiconductor element formed on the semiconductor substrate.
【００１１】本発明によれば、半導体基板を貫通する溝
を設けたことにより、半導体基板を介したノイズの伝搬
を低減することができる。According to the present invention, since the groove penetrating the semiconductor substrate is provided, the propagation of noise through the semiconductor substrate can be reduced.
【００１２】請求項２に係る半導体装置は、請求項１に
記載の半導体装置において、上記溝は、ノイズ発生源と
なり得る領域を取り囲むように形成されている。A semiconductor device according to a second aspect is the semiconductor device according to the first aspect, wherein the groove is formed so as to surround a region which may be a noise generation source.
【００１３】この発明によれば、ノイズ発生源を取り囲
むように溝を形成することで、ノイズ発生源付近から外
へ伝搬するのを抑制することができる。According to the present invention, by forming the groove so as to surround the noise source, it is possible to suppress the propagation from the vicinity of the noise source to the outside.
【００１４】請求項３に係る半導体装置は、請求項１に
記載の半導体装置において、上記溝は、ノイズレベルを
抑制したい領域を取り囲むように形成されている。According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the groove is formed so as to surround a region where noise level is desired to be suppressed.
【００１５】この発明によれば、ノイズレベルを抑制し
たい領域を取り囲むように溝を形成することで、その領
域内に侵入するノイズを低減することができる。According to the present invention, by forming the groove so as to surround the region where the noise level is desired to be suppressed, it is possible to reduce the noise that enters the region.
【００１６】請求項４に記載の半導体装置は、請求項１
に記載の半導体装置において、上記溝に埋め込まれた絶
縁物をさらに備える。A semiconductor device according to a fourth aspect is the semiconductor device according to the first aspect.
The semiconductor device according to the item 1, further comprising an insulator embedded in the groove.
【００１７】この発明によれば、溝を絶縁物で埋め込む
ことで、機械的強度を向上させることができる。According to the present invention, the mechanical strength can be improved by filling the groove with an insulating material.
【００１８】請求項５に係る半導体装置は、請求項１に
記載の半導体装置において、上記半導体基板の裏面に絶
縁膜層もしくは接地された金属層が設けられている。A semiconductor device according to a fifth aspect is the semiconductor device according to the first aspect, wherein an insulating film layer or a grounded metal layer is provided on the back surface of the semiconductor substrate.
【００１９】半導体基板の裏面に絶縁物層もしくは接地
された金属層を形成することで、機械的強度が向上す
る。By forming an insulating layer or a grounded metal layer on the back surface of the semiconductor substrate, the mechanical strength is improved.
【００２０】請求項６に記載の半導体装置は、請求項１
に記載の半導体装置において、上記溝は、複数個並列さ
せて設けられている。A semiconductor device according to a sixth aspect is the semiconductor device according to the first aspect.
In the semiconductor device described in the paragraph [1], a plurality of the grooves are provided in parallel.
【００２１】複数個の溝を並べて設けることにより、ノ
イズレベルをさらに抑制することができる。By providing a plurality of grooves side by side, the noise level can be further suppressed.
【００２２】請求項７に記載の半導体装置は、請求項１
に記載の半導体装置において、上記基板はシリコン基板
を含むことを特徴とする。シリコン基板を用いるので安
価に半導体装置を製造することができる。A semiconductor device according to a seventh aspect is the semiconductor device according to the first aspect.
In the semiconductor device described in (1), the substrate includes a silicon substrate. Since the silicon substrate is used, the semiconductor device can be manufactured at low cost.
【００２３】請求項８に記載の半導体装置は、請求項１
に記載の半導体装置において、上記半導体基板の厚み
は、３０μｍ〜５０μｍに調節されている。半導体基板
の厚みを３０μｍ〜５０μｍにすることにより、基板中
を貫通する溝を形成しやすくすることができる。The semiconductor device according to claim 8 is the semiconductor device according to claim 1.
In the semiconductor device described in (1), the thickness of the semiconductor substrate is adjusted to 30 μm to 50 μm. By setting the thickness of the semiconductor substrate to 30 μm to 50 μm, it is possible to easily form the groove penetrating the substrate.
【００２４】請求項９に記載の半導体装置は、請求項１
に記載の半導体装置において、上記溝は、平面形状にお
いて四角形状に形成されていることを特徴とする。A semiconductor device according to a ninth aspect is the semiconductor device according to the first aspect.
In the semiconductor device described in [1], the groove is formed in a quadrangular shape in a plan view.
【００２５】請求項１０に係る方法は、上下に貫通する
溝が形成された半導体基板を有する半導体装置の製造方
法に係る。まず、上記半導体基板の上記溝を形成する部
分を、基板の途中まで掘り下げる。上記掘り下げられた
部分に絶縁物を完全にまたは部分的に埋め込む。上記半
導体基板の上記溝を形成する部分を、基板の反対側か
ら、上記絶縁物が現れるまで掘る。A tenth aspect of the present invention relates to a method of manufacturing a semiconductor device having a semiconductor substrate having a vertically penetrating groove formed therein. First, the portion of the semiconductor substrate on which the groove is formed is dug down to the middle of the substrate. An insulator is completely or partially embedded in the dug portion. A portion of the semiconductor substrate where the groove is formed is dug from the opposite side of the substrate until the insulator appears.
【００２６】請求項１１に記載の方法は、上下に貫通す
る溝が形成された半導体基板を有する半導体装置の製造
方法に係る。まず、上記半導体基板の裏面に絶縁物層を
形成する。上記半導体基板の上記溝を形成する部分を、
基板表面から基板の裏面に至るまで掘り下げる。The method according to claim 11 relates to a method of manufacturing a semiconductor device having a semiconductor substrate in which a vertically penetrating groove is formed. First, an insulating layer is formed on the back surface of the semiconductor substrate. A portion of the semiconductor substrate where the groove is formed,
Dig from the front surface of the substrate to the back surface of the substrate.
【００２７】請求項１２に記載の半導体装置の製造方法
は、請求項１０または１１に記載の半導体装置の製造方
法において、上記溝を、平面形状において四角形状に形
成することを特徴とする。A method of manufacturing a semiconductor device according to a twelfth aspect is the method of manufacturing a semiconductor device according to the tenth or eleventh aspect, characterized in that the groove is formed in a quadrangular shape in a plan view.
【００２８】[0028]
【発明の実施の形態】以下、この発明の実施の形態を図
について説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.
【００２９】実施の形態１
図１は、実施の形態１に係る高周波用シリコン半導体装
置の断面図である。 First Embodiment FIG. 1 is a sectional view of a high frequency silicon semiconductor device according to a first embodiment.
【００３０】図１を参照して、シリコン基板１中に、基
板を貫通する溝１０が設けられている。溝１０内に、絶
縁物１１が埋め込まれている。シリコン基板１の厚み
は、３０μｍ〜５０μｍにされるのが好ましい。シリコ
ン基板１の上にトランジスタのゲート電極２が形成され
ている。トランジスタに、配線３が接続されている。ト
ランジスタや配線間の絶縁のために、シリコン基板１の
上に絶縁層４が設けられている。溝１０は、ノイズを発
生する回路モジュールまたはノイズレベルを低く抑えた
い回路モジュールを取り囲むように設けられている。Referring to FIG. 1, a silicon substrate 1 is provided with a groove 10 penetrating the substrate. An insulator 11 is embedded in the groove 10. The silicon substrate 1 preferably has a thickness of 30 μm to 50 μm. A gate electrode 2 of a transistor is formed on a silicon substrate 1. The wiring 3 is connected to the transistor. An insulating layer 4 is provided on the silicon substrate 1 for insulation between transistors and wirings. The groove 10 is provided so as to surround a circuit module that generates noise or a circuit module whose noise level is desired to be kept low.
【００３１】溝１０により、半導電性のシリコン基板１
は２つの部分に分離され、ノイズの伝搬が抑制される。
本実施の形態によれば、基板は通常のシリコン基板でよ
く、高価なＳＯＩ基板を使用する必要がない。したがっ
て、安価に、ノイズの伝搬が低減されるように改良され
た高周波用シリコン半導体装置が得られる。Due to the groove 10, the semiconductive silicon substrate 1 is formed.
Is separated into two parts, and the propagation of noise is suppressed.
According to this embodiment, the substrate may be a normal silicon substrate, and it is not necessary to use an expensive SOI substrate. Therefore, it is possible to obtain the high-frequency silicon semiconductor device that is improved so that the noise propagation can be reduced at low cost.
【００３２】なお、このような半導体装置の製造方法に
ついては、後述する。実施の形態２
図１を参照して、シリコン基板１を貫通する溝１０は、
絶縁物１１で埋め込まれているが、このような固体絶縁
物がなくてもよく、中空にしてもよい。この場合、溝１
１を絶縁物で埋め込む工程を省略することができ、製造
工程をさらに簡略化することができるという利点があ
る。A method of manufacturing such a semiconductor device will be described later. Second Embodiment Referring to FIG. 1, the groove 10 penetrating the silicon substrate 1 is
Although it is embedded with the insulator 11, such a solid insulator may be omitted or may be hollow. In this case, groove 1
There is an advantage that the step of burying 1 with an insulator can be omitted and the manufacturing process can be further simplified.
【００３３】実施の形態３
１つの半導体装置内にノイズを発生する部分とノイズレ
ベルを小さく抑えたい部分が共存しているとき、ノイズ
の伝搬を抑制する方法として、ノイズを発生源から外へ
出さないようにすることが考えられる。 Embodiment 3 When a portion which generates noise and a portion which is desired to reduce the noise level coexist in one semiconductor device, a method of suppressing the noise propagation is to output the noise from the source. It may be possible not to.
【００３４】図２に、本実施の形態に係る半導体装置の
平面図を示す。ノイズを発生している回路ブロック２０
を溝１０で囲み、その外であるノイズレベルを低く抑え
たい回路ブロック２１へのノイズ伝搬を低減する。図２
におけるＩ−Ｉ線に沿う断面図は、例えば図１に示す断
面図で表される。FIG. 2 is a plan view of the semiconductor device according to this embodiment. Circuit block 20 generating noise
Is surrounded by the groove 10 to reduce the noise propagation to the circuit block 21 outside which the noise level is desired to be kept low. Figure 2
A sectional view taken along line I-I in FIG. 1 is represented by, for example, the sectional view shown in FIG.
【００３５】実施の形態４
図３は、実施の形態４に係る高周波用シリコン半導体装
置の平面図である。図２の装置では、回路ブロック２１
へ侵入するノイズを低減するために、ノイズ発生源であ
る回路ブロック２０を溝１０で取り囲む構成を採用して
いる。しかしこの発明はこれに限られるものではなく、
図３に示すように、ノイズレベルを低く抑えたい回路ブ
ロック２１の方を溝１０で取り囲む構成にすることによ
って、ノイズの低減を図ることができる。 Fourth Embodiment FIG. 3 is a plan view of a high frequency silicon semiconductor device according to a fourth embodiment. In the device of FIG. 2, the circuit block 21
In order to reduce the noise penetrating into, the circuit block 20 which is the noise source is surrounded by the groove 10. However, the present invention is not limited to this,
As shown in FIG. 3, noise can be reduced by surrounding the circuit block 21 whose noise level is desired to be kept low with the groove 10.
【００３６】実施の形態５
発生したノイズが大きい場合、あるいは許容ノイズレベ
ルを小さく設定したい場合には、単一の溝だけでは十分
でないことがあり得る。このような場合には、たとえ
ば、図４（断面図）と図５（平面図）に示すように、溝
１０ａ，１０ｂを複数本並べることにより、ノイズレベ
ルをさらに低減させることができる。 Embodiment 5 When a large amount of noise is generated, or when it is desired to set the allowable noise level to a low level, a single groove may not be enough. In such a case, for example, as shown in FIG. 4 (cross-sectional view) and FIG. 5 (plan view), by arranging a plurality of grooves 10a and 10b, the noise level can be further reduced.
【００３７】なお、図４および図５の装置では、溝が２
本の場合について示しているが、本数を増やせば、さら
に大きな効果が得られる。In the apparatus shown in FIGS. 4 and 5, the groove is 2
Although the case of books is shown, an even greater effect can be obtained by increasing the number of books.
【００３８】実施の形態６
図６〜図９は、実施の形態６に係る高周波用シリコン半
導体装置の製造方法を示す図である。 Sixth Embodiment FIGS. 6 to 9 are views showing a method of manufacturing a high frequency silicon semiconductor device according to a sixth embodiment.
【００３９】図６を参照して、シリコン基板１の溝を形
成する部分を、基板の途中まで掘り下げ、溝１３を形成
する。With reference to FIG. 6, the groove forming portion of silicon substrate 1 is dug into the middle of the substrate to form groove 13.
【００４０】図７を参照して、溝１３内に絶縁物１１を
埋め込む。図８を参照して、シリコン基板１の溝を形成
する部分を、基板の反対側から、絶縁物１１が現われる
まで掘る。図９を参照して、掘り下げられた部分に、絶
縁物１１をさらに埋め込む。この上に、図１を参照し
て、ゲート電極２を含むトランジスタと配線３と絶縁層
４を形成することによって、高周波用シリコン半導体装
置が完成する。Referring to FIG. 7, insulator 11 is embedded in groove 13. Referring to FIG. 8, a portion of silicon substrate 1 where a groove is formed is dug from the opposite side of the substrate until insulator 11 appears. Referring to FIG. 9, insulator 11 is further embedded in the dug portion. On this, referring to FIG. 1, a transistor including gate electrode 2, wiring 3 and insulating layer 4 are formed to complete a high frequency silicon semiconductor device.
【００４１】実施の形態７
図１０〜図１１は、実施の形態７に係る高周波用シリコ
ン半導体装置の製造方法を説明するための図である。図
１０を参照して、シリコン基板１の裏面に絶縁物層また
は接地された金属層１４を形成する。 Seventh Embodiment FIGS. 10 to 11 are views for explaining a method of manufacturing a high frequency silicon semiconductor device according to a seventh embodiment. Referring to FIG. 10, an insulating layer or a grounded metal layer 14 is formed on the back surface of silicon substrate 1.
【００４２】図１１を参照して、シリコン基板１の溝を
形成する部分を、基板表面から基板の裏面に至るまで掘
り下げ、貫通溝１０を形成する。その後、貫通溝１０内
に、絶縁物を部分的あるいは完全に埋め込み、トランジ
スタと配線を形成することにより、図１に示す高周波用
シリコン半導体装置が得られる。Referring to FIG. 11, the portion of silicon substrate 1 where the groove is formed is dug down from the front surface of the substrate to the back surface of the substrate to form through groove 10. Then, an insulating material is partially or completely buried in the through groove 10 to form a transistor and a wiring, thereby obtaining the high frequency silicon semiconductor device shown in FIG.
【００４３】今回開示された実施の形態はすべての点で
例示であって制限的なものではないと考えられるべきで
ある。本発明の範囲は上記した説明ではなくて特許請求
の範囲によって示され、特許請求の範囲と均等の意味お
よび範囲内でのすべての変更が含まれることが意図され
る。The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.
【００４４】[0044]
【発明の効果】以上説明したように、この発明によれ
ば、従来のシリコン基板と同様の価格で、ノイズの伝搬
が低減された高周波用シリコン半導体装置が得られると
いう効果を奏する。As described above, according to the present invention, it is possible to obtain the high-frequency silicon semiconductor device in which the propagation of noise is reduced at the same price as the conventional silicon substrate.
【図１】 実施の形態１に係る高周波用シリコン半導体
装置の断面図である。FIG. 1 is a cross-sectional view of a high frequency silicon semiconductor device according to a first embodiment.
【図２】 実施の形態３に係る高周波用シリコン半導体
装置の平面図である。FIG. 2 is a plan view of a high frequency silicon semiconductor device according to a third embodiment.
【図３】 実施の形態４に係る高周波用シリコン半導体
装置の平面図である。FIG. 3 is a plan view of a high frequency silicon semiconductor device according to a fourth embodiment.
【図４】 実施の形態５に係る高周波用シリコン半導体
装置の断面図である。FIG. 4 is a cross-sectional view of a high frequency silicon semiconductor device according to a fifth embodiment.
【図５】 図４に示す装置の平面図である。5 is a plan view of the device shown in FIG.
【図６】 実施の形態６に係る半導体装置の製造方法の
順序の第１の工程における半導体装置の断面図である。FIG. 6 is a cross-sectional view of the semiconductor device in a first step of the order of the method for manufacturing the semiconductor device according to the sixth embodiment.
【図７】 実施の形態６に係る半導体装置の製造方法の
順序の第２の工程における半導体装置の断面図である。FIG. 7 is a cross-sectional view of the semiconductor device in a second step of the order of the method for manufacturing the semiconductor device according to the sixth embodiment.
【図８】 実施の形態６に係る半導体装置の製造方法の
順序の第３の工程における半導体装置の断面図である。FIG. 8 is a sectional view of the semiconductor device in a third step of the order of the method for manufacturing the semiconductor device according to the sixth embodiment.
【図９】 実施の形態６に係る半導体装置の製造方法の
順序の第４の工程における半導体装置の断面図である。FIG. 9 is a sectional view of a semiconductor device in a fourth step of the order of the method for manufacturing a semiconductor device according to the sixth embodiment.
【図１０】 実施の形態７に係る高周波用シリコン半導
体装置の製造方法の順序の第１の工程における半導体装
置の断面図である。FIG. 10 is a sectional view of the semiconductor device in a first step of the order of the method for manufacturing the high-frequency silicon semiconductor device according to the seventh embodiment.
【図１１】 実施の形態７に係る高周波用シリコン半導
体装置の製造方法の順序の第２の工程における半導体装
置の断面図である。FIG. 11 is a cross-sectional view of the semiconductor device in a second step of the order of the method for manufacturing the high-frequency silicon semiconductor device according to the seventh embodiment.
【図１２】 従来の高周波用シリコン半導体装置の断面
図である。FIG. 12 is a cross-sectional view of a conventional high frequency silicon semiconductor device.
１ シリコン基板、２ トランジスタのゲート電極、３
配線、４ 絶縁層、１０ 貫通溝、１１ 絶縁物。1 silicon substrate, 2 gate electrode of transistor, 3
Wiring, 4 insulating layers, 10 through grooves, 11 insulators.
Claims (12)
半導体装置。1. A semiconductor device comprising a semiconductor substrate, a groove vertically penetrating the semiconductor substrate, and a semiconductor element formed on the semiconductor substrate.
を取り囲むように形成されている、請求項１に記載の半
導体装置。2. The semiconductor device according to claim 1, wherein the groove is formed so as to surround a region that can be a noise generation source.
域を取り囲むように形成されている、請求項１に記載の
半導体装置。3. The semiconductor device according to claim 1, wherein the groove is formed so as to surround a region whose noise level is desired to be suppressed.
える、請求項１に記載の半導体装置。4. The semiconductor device according to claim 1, further comprising an insulator embedded in the groove.
は接地された金属層が設けられている、請求項１に記載
の半導体装置。5. The semiconductor device according to claim 1, wherein an insulating film layer or a grounded metal layer is provided on the back surface of the semiconductor substrate.
いる、請求項１に記載の半導体装置。6. The semiconductor device according to claim 1, wherein a plurality of the grooves are provided in parallel.
１に記載の半導体装置。7. The semiconductor device according to claim 1, wherein the substrate includes a silicon substrate.
０μｍに調節されている、請求項１に記載の半導体装
置。8. The semiconductor substrate has a thickness of 30 μm to 5 μm.
The semiconductor device according to claim 1, wherein the semiconductor device is adjusted to 0 μm.
形成されている、請求項１に記載の半導体装置。9. The semiconductor device according to claim 1, wherein the groove is formed in a rectangular shape in a plan view.
基板を有する半導体装置の製造方法であって、 前記半導体基板の前記溝を形成する部分を、基板の途中
まで掘り下げる工程と、 前記掘り下げられた部分に完全に、または部分的に絶縁
物を埋め込む工程と、 前記半導体基板の前記溝を形成する部分を、基板の反対
側から、前記絶縁物が現れるまで掘る工程と、を備えた
半導体装置の製造方法。10. A method of manufacturing a semiconductor device having a semiconductor substrate having a vertically penetrating groove formed therein, the method comprising: a step of digging a portion of the semiconductor substrate where the groove is formed halfway through the substrate; A semiconductor device comprising: a step of completely or partially embedding an insulating material in a recessed portion; and a step of digging a portion of the semiconductor substrate where the groove is formed from the opposite side of the substrate until the insulating material appears. Manufacturing method.
基板を有する半導体装置の製造方法であって、 前記半導体基板の裏面に絶縁物層を形成する工程と、 前記半導体基板の前記溝を形成する部分を、基板表面か
ら基板の裏面に至るまで掘り下げる工程と、を備えた半
導体装置の製造方法。11. A method of manufacturing a semiconductor device having a semiconductor substrate having a vertically penetrating groove formed therein, the method comprising: forming an insulator layer on a back surface of the semiconductor substrate; and forming the groove of the semiconductor substrate. A method of manufacturing a semiconductor device, comprising the step of digging a portion to be etched from the front surface of the substrate to the back surface of the substrate.
に形成する、請求項１０または１１に記載の半導体装置
の製造方法。12. The method of manufacturing a semiconductor device according to claim 10, wherein the groove is formed in a rectangular shape in a plan view.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001372227A JP2003174082A (en) | 2001-12-06 | 2001-12-06 | Semiconductor device and manufacturing method thereof |
| US10/164,427 US6787874B2 (en) | 2001-12-06 | 2002-06-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001372227A JP2003174082A (en) | 2001-12-06 | 2001-12-06 | Semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003174082A true JP2003174082A (en) | 2003-06-20 |
Family
ID=19181154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001372227A Pending JP2003174082A (en) | 2001-12-06 | 2001-12-06 | Semiconductor device and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6787874B2 (en) |
| JP (1) | JP2003174082A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010016296A (en) * | 2008-07-07 | 2010-01-21 | Seiko Instruments Inc | Semiconductor device |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003174082A (en) * | 2001-12-06 | 2003-06-20 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method thereof |
| JP3765314B2 (en) * | 2004-03-31 | 2006-04-12 | セイコーエプソン株式会社 | Mask, mask manufacturing method, electro-optical device manufacturing method, and electronic apparatus |
| SE533579C2 (en) * | 2007-01-25 | 2010-10-26 | Silex Microsystems Ab | Method of microcapsulation and microcapsules |
| US8710568B2 (en) * | 2007-10-24 | 2014-04-29 | Denso Corporation | Semiconductor device having a plurality of elements on one semiconductor substrate and method of manufacturing the same |
| US7911023B2 (en) * | 2007-11-06 | 2011-03-22 | Denso Corporation | Semiconductor apparatus including a double-sided electrode element and method for manufacturing the same |
| US9673275B2 (en) | 2015-10-22 | 2017-06-06 | Qualcomm Incorporated | Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits |
| US10546816B2 (en) * | 2015-12-10 | 2020-01-28 | Nexperia B.V. | Semiconductor substrate with electrically isolating dielectric partition |
| JP6584977B2 (en) | 2016-02-24 | 2019-10-02 | 日立オートモティブシステムズ株式会社 | Semiconductor device |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3343256A (en) * | 1964-12-28 | 1967-09-26 | Ibm | Methods of making thru-connections in semiconductor wafers |
| US3801949A (en) * | 1973-03-08 | 1974-04-02 | Rca Corp | Thermal detector and method of making the same |
| US3963489A (en) * | 1975-04-30 | 1976-06-15 | Western Electric Company, Inc. | Method of precisely aligning pattern-defining masks |
| US4238278A (en) | 1979-06-14 | 1980-12-09 | International Business Machines Corporation | Polycrystalline silicon oxidation method for making shallow and deep isolation trenches |
| US5298450A (en) | 1987-12-10 | 1994-03-29 | Texas Instruments Incorporated | Process for simultaneously fabricating isolation structures for bipolar and CMOS circuits |
| JP2604071B2 (en) | 1991-05-14 | 1997-04-23 | 株式会社東芝 | Method for manufacturing semiconductor device |
| US5453713A (en) * | 1992-07-06 | 1995-09-26 | Digital Equipment Corporation | Noise-free analog islands in digital integrated circuits |
| US5485029A (en) * | 1994-06-30 | 1996-01-16 | International Business Machines Corporation | On-chip ground plane for semiconductor devices to reduce parasitic signal propagation |
| US5864168A (en) * | 1997-02-18 | 1999-01-26 | Texas Instruments Incorporated | Apparatus and method for reduced substrate noise coupling |
| JP2003174082A (en) * | 2001-12-06 | 2003-06-20 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method thereof |
-
2001
- 2001-12-06 JP JP2001372227A patent/JP2003174082A/en active Pending
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2002
- 2002-06-10 US US10/164,427 patent/US6787874B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010016296A (en) * | 2008-07-07 | 2010-01-21 | Seiko Instruments Inc | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| US6787874B2 (en) | 2004-09-07 |
| US20030107061A1 (en) | 2003-06-12 |
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