JP2003173689A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory array whose write-in drain disturbance characteristics can be improved. <P>SOLUTION: A source line of a nonvolatile memory cell array is grounded through an element having a resistance component, and a resistance value is switched depending on the time of write-in operation and the read-out operation. A resistance value at the time of write-in operation is set to a large value and a source potential is floated, a sub-threshold leak current of a non-selection cell is decreased, and write-in drain disturbance tolerance is improved. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to a nonvolatile semiconductor memory device having a floating gate structure type nonvolatile memory cell and having an electrical rewriting function, and a system LSI incorporating such a nonvolatile memory. Regarding technology.

[0002]

2. Description of the Related Art In recent years, non-volatile semiconductor memory devices have come to be widely used in industrial and consumer electronic devices as represented by flash EEPROMs, and the conventional magnetic memory devices have been replaced with small size, light weight and low power consumption devices. Contribute to

In a non-volatile semiconductor memory device, a method of storing information by accumulating electrons in an electrically insulated floating gate (floating gate) and detecting a change in threshold voltage depending on the presence or absence of electric charge, or an electronic Further, a method of accumulating charges in, for example, a silicon nitride thin film including a hole trap level and reading a change in threshold voltage is widely used.

Several array structures have been proposed and put to practical use as means for integrating these nonvolatile semiconductor memory devices on a large scale and for allowing random access on the array. Among them, the NOR type array configuration is most commonly used because of its simple structure and high speed.

In this specification, the NOR type array structure will be mainly described below.

No floating gate type flash memory cell
FIG. 4 shows a conventional example arranged in an R-type array. Such an array arrangement is disclosed in, for example, IEEE Press 199.
William D Brown & Joe E. Bre published in 8
wer "Nonvolatile Semiconductor Memory Techno
logy ”on page 225.

In FIG. 4 showing the structure of a conventional NOR type nonvolatile memory array, 11 is a floating gate type flash memory cell, 10 is a selected cell of the memory cells 11,
Reference numeral 12 is a word line that connects the control gates of the flash memory cells to each column, and 13 is a bit line that connects the drain electrodes of the flash memory cells to each row.
It is provided in a direction orthogonal to 2. Reference numeral 14 is a source line to which the source electrode of the flash memory cell is connected. In the case of a flash memory, it is general to commonly connect the source lines included in an array of one erase unit for batch erase.
Here, the common source line 14 is connected to the ground level. It should be noted that this common source line 14 is grounded.

First, the operation of selectively writing data in the memory cell designated by 10 in the drawing among the memory cells will be described.

Non-volatile memory cells The writing method for the cells is the channel hot electron injection method, Fauler-
Several methods such as the Nordheim tunnel electron injection method and the band-to-band transition electron injection method have been proposed. Here, a case where the channel hot electron injection method is used will be described.

Table 1 summarizes the conventional write and read bias conditions of the stack gate type flash memory cell of the channel hot electron injection write system.

[0011]

【table 1】 For example, 10V is applied to the word line WLn connected to the control gate of the selected cell 10, and the other word lines are grounded to 0V. Next, for example, 5V is applied to the bit line BLm connected to the drain of the selected cell 10, and the other bit lines are grounded to 0V. The source lines are all grounded to 0V in one erase block.

As a result, the channel current flows only in the selected cell 10 of the memory cells in the array, and the electrons obtained by the high electric field near the drain cross the electrical barrier of the insulating film separating the channel and the floating gate. Injected into the floating gate. As a result, the gate threshold voltage of the memory cell transistor can be increased. Then, by changing the word line and the bit line, random accessible data writing can be performed.

In order to read the information held in the memory cell, a bias is applied to the word line WLn and the bit line BLm connected to the selected cell 10 in the same manner as in the case of writing, and according to the gate threshold voltage of the selected cell. A circuit is used to determine whether or not a channel current flows, and the result is output as a result of the determination.

Regarding the applied bias during the read operation, for example, the word line 3.3V and the bit line 1V, which are lower than those used during the write operation, are employed, which are high-energy electrons injected into the floating gate. This is to prevent a weak write operation.

In the channel hot electron injection writing non-volatile memory array configuration described above,
There is a problem that the non-selected cells are easily affected by the fluctuation of the gate threshold voltage during the write operation.

In FIG. 4, the selected cell 10 and the bit line B
The bias value applied to each terminal of the memory cell 11 that shares Lm, that is, the disturb cell is shown in the middle row of Table 1. The control gate is grounded to 0V, and the same 5V as the selected cell 10 is applied to the drain. To be done. At this time, although the control gate potential is 0 V, when a subthreshold leak current slightly flows between the source and drain of the memory cell 11, some electrons gain energy from the high electric field in the vicinity of the drain and enter the floating gate. An unintended phenomenon occurs in which the threshold voltage rises after being injected.

Generally, this is called a write drain disturb. If the number of word lines in another memory array is N, all the word lines in one array are sequentially activated to write data. Is (N-
1) Receive write drain disturb once. As the number of word lines increases, the total time for receiving the write drain disturb becomes longer, and the threshold voltage is easily changed.

When the gate threshold voltage of the cell which is not written in this way rises, an error occurs that an erroneous output is produced during the read operation.

In order to reduce the sub-threshold leak current for the purpose of alleviating the write drain disturb phenomenon described above and improving the reliability of the non-volatile semiconductor memory device, in the prior art, in the case of a stack gate type cell, , The erase level is set shallow to set the threshold voltage of the erased cell high, and in the case of the split gate type cell, the diffusion process condition is set so that the threshold voltage of the control gate side connected in series with the floating gate becomes high. Was.

[0020]

However, the conventional setting of the threshold voltage of the non-volatile memory array has a problem that the cell current flowing in the erased cell at the time of reading decreases. If the cell current decreases, the sense amplifier operation may malfunction, resulting in incorrect output.

Further, if sufficient time is taken for the sensing operation so as not to malfunction, the time until the read result is output, that is, the access time, becomes long, high-speed operation cannot be performed, and the performance as the semiconductor memory device is impaired. Will be invited.

A method of applying a negative potential instead of 0 V to the non-selected word line during the write operation to suppress the leak current of the non-selected cell can be considered, but an internal power supply circuit for generating a negative voltage in the semiconductor chip is also possible. Therefore, problems such as an increase in chip area and an increase in power consumption occur.

The present invention was devised in view of such circumstances, and it is possible to reduce the subthreshold leak current of a non-selected cell that undergoes write drain disturb without lowering the memory cell current during a read operation. The purpose is to do so.

[0024]

(1) A nonvolatile semiconductor memory device according to the present invention solves the above problems by taking the following means. As a premise, a plurality of nonvolatile semiconductor memory elements (memory cells) are arranged in an array, a plurality of word lines having gate electrodes commonly connected, a plurality of bit lines having drain electrodes commonly connected, and all in one array. Of the source electrodes are commonly connected. Further, means for selecting one memory element from the plurality of nonvolatile semiconductor memory elements, and means for changing a threshold voltage of the selected nonvolatile semiconductor memory element (selected cell) by passing a current through the channel. A means for performing one operation (writing operation) and a means for performing a second operation (reading operation) that determines the magnitude of the current flowing through the channel of the selected nonvolatile semiconductor memory element (selected cell) and outputs the result. Have.

In the nonvolatile semiconductor memory device having such a structure, the present invention solves the above-mentioned problems by taking the following means. That is, for a non-selected storage element (non-selected cell) that shares a bit line with the storage element selected during the first operation (write operation), the potential of the source applied to the non-selected storage element is the non-selected storage element. The potential of the word line of the memory element is higher than that of the word line. Furthermore, during the second operation (during read operation)
The source potential of the selected storage element is set to be lower than the source potential of the non-selected storage element sharing the bit line with the selected storage element during the first operation (write operation). .

According to this, the memory element (non-selected cell) that receives the write drain disturb during the write operation.
Has a higher source terminal potential than the control gate potential, which corresponds to a relative decrease in the control gate potential, the drain potential, and the substrate potential. In particular, the control gate potential is lower than that in the prior art. It is possible to reduce the subthreshold leak current that causes the write drain disturb.

Further, the substrate bias effect also works, the subthreshold leakage current can be further reduced, and an array which is not affected by the write drain disturb can be obtained.

As another means for suppressing the subthreshold leakage current, an internal power supply circuit for generating a negative voltage as in the method of applying a negative potential to a non-selected word line at the time of write operation is not required, which increases the chip area and It does not cause an increase in power consumption.

At the same time, it is ensured that the source potential during the read operation is set lower than the source potential during the write operation (the bias condition during the read operation is the same as in the prior art). It is possible to maintain stable sense amplifier operation and high speed without decreasing the memory cell current.

(2) As a preferred embodiment of the structure at a more specific level for realizing the above structure,
The source line of the nonvolatile semiconductor memory element array is grounded through an element having a resistance component, and the first operation (write operation) and the second operation (read operation) are performed.
It is possible to cite that the resistance value of the element is switched so that the resistance value during the first operation is higher than the resistance value during the second operation. That is, the gist is to switch so that the resistance value in the write operation becomes larger than that in the read operation of the memory cell. According to this, the source potential can be adjusted and the subthreshold leakage current can be suppressed by a relatively simple configuration of switching the resistance value.

(3) Further, regarding a configuration at a more specific level for realizing the above-described resistance value switching configuration, in a preferred mode, the means for switching the resistance value of the element having the resistance component is provided with a plurality of means. It can be mentioned that the MOS transistors are connected in parallel and the gate potential of at least one of the plurality of MOS transistors is switched. According to this, the subthreshold leakage current can be suppressed by an extremely simple configuration in which MOS transistors are connected in parallel.

(4) Further, regarding a configuration at a more specific level for realizing the above-described resistance value switching configuration, as yet another preferred embodiment, a means for switching the resistance value of the element having the resistance component is , MO formed on the surface of the semiconductor well electrically separated from the semiconductor substrate
The drain of the S-transistor is connected to the source line, the semiconductor well is connected to the drain,
It can be mentioned that the gate potential of the MOS transistor is switched.

According to this, a triple well process MOS transistor is used as an element having a resistance component, but the number may be one, and the configuration is further simplified as compared with the case where a plurality of MOS transistors are connected in parallel. Can be converted.

Further, since the forward voltage of the pn junction is used, even if the write current of the entire array changes, the fluctuation of the source line potential during the write operation is small, and the operation stability is secured.

(5) As a solution different from the solution of the above (1), the present invention also presents the following solution. That is, the potential of the drain applied to the non-selected memory element (non-selected cell) sharing the bit line with the memory element selected during the first operation (write operation) is the potential of the source line of the non-selected memory element. It is configured to be lower than. Further, the drain potential of the memory element selected in the second operation (reading operation) is higher than the source potential.

According to this, the source
Since the polarity of the drain terminal is inverted and the drain potential of the memory cell receiving the write drain disturb is set lower than the source potential, the subthreshold leak current that causes the write drain disturb can be reduced.

At the same time, it is ensured that the source potential during the read operation is set lower than the source potential during the write operation (the bias condition during the read operation is the same as the conventional one). It is possible to maintain stable sense amplifier operation and high speed without decreasing the memory cell current.

(6) In a preferred aspect of the invention (5), the bit line of the non-volatile semiconductor memory element array is grounded via an element having a resistance component during the first operation. It is that. According to this, the configuration for reversing the polarities of the source / drain terminals during the write operation can be made relatively simple.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a nonvolatile semiconductor memory device according to the present invention will be described below in detail with reference to the drawings.

(First Embodiment) A non-volatile semiconductor memory device according to a first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of the floating gate type flash memory array of this embodiment. In FIG. 1, the same reference numerals as those in FIG. 4 of the prior art indicate the same components, and thus detailed description thereof will be omitted. Briefly, 11 is a memory cell, 12 is a word line, 13 is a bit line, 14 is a source line, 30 is a sense amplifier, and 10 is a selected cell.

In the conventional memory array configuration shown in FIG. 4, the source line 14 is directly grounded, whereas in the present embodiment, it is grounded via two N-channel MOS transistors 15 and 16 connected in parallel. Has been done.

The gate terminal of the MOS transistor 15 is connected to the power supply potential, and in this case, the MOS transistor 15 functions as a resistor. In addition, the gate terminal 17 of the MOS transistor 16 is configured to receive a write / read switching signal that becomes “L” during a write operation and “H” during a read operation.

The N-channel MOS transistor 16 is
At the time of writing operation, it is cut off by the gate input of "L", and the MOS transistor 1 is connected between the source line 14 and the ground.
Only 5 will be inserted. Therefore, (channel current of memory cell being written) × (number of simultaneously written cells in array) × (resistance component of MOS transistor 15)
And a potential of the source line 14 becomes higher than the ground level.

In the present embodiment, the device size of the MOS transistor 15 is adjusted so that the value is about 0.6V.

In this case, the channel width / channel length ratio of the MOS transistor 16 is determined by the MOS transistor 15
If it is made sufficiently larger than that, the MOS transistor 16 becomes conductive during the read operation, and the potential of the source line can be lowered to approximately the ground level.

Table 2 shows the write and read bias conditions in this embodiment.

[0048]

[Table 2] Focusing on the middle part of Table 2, the source terminal potential of the memory cell receiving the write drain disturb is 0.6V. This corresponds to the control gate potential, the drain potential, and the substrate potential decreasing by 0.6V, and in particular, the control gate potential of 0V in the past is equivalent to -0.6V in the present embodiment. Becomes Therefore, the subthreshold leak current that causes the write drain disturb can be reduced by about three digits.

Further, the substrate bias effect also works, the subthreshold leakage current can be further reduced, and an array which is not affected by the write drain disturb can be obtained.

Also, an internal power supply circuit for generating a negative voltage is not required as in the case of another method of suppressing a subthreshold leak current by applying a negative potential to a non-selected word line during a write operation, and the chip area is reduced. It does not cause an increase or increase in power consumption.

Since the bias condition during the read operation of this embodiment is no different from the conventional read bias condition in Table 1, the memory cell current during the read operation does not decrease, and the stable sense amplifier operation and high speed operation are achieved. You can keep your sex.

As described above, according to the present embodiment, by inserting the element having the resistance component in the source line and switching the resistance value between the write operation and the read operation, the write performance is not sacrificed. It is possible to improve the drain disturb resistance ability by about three digits.

(Second Embodiment) Next, a nonvolatile semiconductor memory device according to a second embodiment of the present invention will be described.

FIG. 2 shows the structure of the floating gate type flash memory array of this embodiment. In FIG. 2, the same reference numerals as those in FIG. 4 of the prior art indicate the same constituent elements, and thus detailed description thereof will be omitted.

In this embodiment, the source line 14 of the memory array is the N-channel MO of the triple well process.
It is grounded through the S transistor 18. The N-channel MOS transistor 18 can apply a potential other than the ground potential to the well potential by using the so-called triple well technique, and the well potential is connected to the drain terminal here.

Further, similarly to the first embodiment, the gate terminal 19 of the MOS transistor 18 is configured so that the write / read switching signal which becomes "L" during the write operation and "H" during the read operation is input. ing.
The write and read bias conditions of this embodiment are the same as in Table 2.

The operation of this embodiment will be described. Since the "L" level signal is applied to the gate terminal 19 during the write operation, the channel current does not flow, but since the well is connected to the drain, the MOS transistor 18 is connected. The pn junction between the well and the source becomes the forward direction, and the write current flows therethrough to the ground potential. Therefore, the potential of the source line 14 during the write operation becomes about 0.6 V which is the forward voltage of the pn junction.

Next, in the read operation, the gate terminal 1
Since an "H" level signal is applied to 9 and a channel is formed between the source and drain of the MOS transistor 18, the channel current is added to the forward current of the pn junction described above between the source line 14 and the ground to reduce the resistance. Therefore, the potential of the source line 14 becomes almost equal to the ground potential.

Using this embodiment, although there is a constraint that a triple well process must be used, by adding one transistor to the conventional technique, the same write / read bias conditions of Table 2 as in Embodiment 1 can be obtained. Can be realized, and the same effect can be exhibited.

Further, since the forward voltage of the pn junction is used, even if the write current of the entire array changes, the source line potential change during the write operation is small and stable.

(Third Embodiment) Next, a third embodiment according to the present invention will be described. FIG. 3 shows a configuration diagram of a floating gate type flash memory array according to a third embodiment of the present invention. In FIG. 3, the same reference numerals as those in FIG. 4 of the related art refer to the same components, and thus detailed description thereof will be omitted.

Table 3 shows the write and read bias conditions in this embodiment.

[0063]

[Table 3] In the present embodiment, as shown in FIG. 3, the drains of N-channel MOS transistor 16 for setting source line 14 to the ground level and P-channel MOS transistor 20 for applying a bias of 5 V to source line 14 are connected to each other. Are connected in a complementary manner, and their common connection point is connected to the source line 14. Also, N channel MO
The gate of the S transistor 16 and the gate of the P channel MOS transistor 20 are connected to the common gate terminal 21. Reference numeral 22 is a selection gate inserted between each bit line and the sense amplifier 30. This selection gate 2
2 is inserted as an element having a resistance component.

First, the write operation will be described. The N-channel MOS transistor 16 and the P-channel MO are provided.
The “L” level is applied to the common gate terminal 21 of the S-transistor 20, the N-channel MOS transistor 16 is cut off, and the P-channel MOS transistor 20.
Is conducted, 5V is applied to the source line 14.

On the other hand, of the plurality of bit lines, the select gate 2
The bit line corresponding to the address designated by 2 is connected to the sense amplifier 30 side.
Connected to ground potential in the circuit.

When a bias is selectively applied to the word line WLm of the selected cell 10, a channel current flows from the source terminal of the selected cell 10 to the drain terminal, and writing is performed by hot electron injection.

Here, the polarities of the source / drain and the direction of the channel current are opposite to those in the above-described first and second embodiments.

Since the channel current flows through the select gate 22, the drain terminal potential can be made higher than the ground level due to the resistance component of the select gate 22, as in the first and second embodiments. The same operation and effect as those of the first embodiment can be obtained.

In order to set the drain potential to a predetermined value, for example, 0.6 V, the device size of the select gate 22 may be set according to the channel current during the write operation.

Next, the read operation will be described. During read operation, N-channel MOS transistor 1
6 and the common gate terminal 21 of the P-channel MOS transistor 20 is applied with "H" level, the N-channel MOS transistor 16 becomes conductive, and the P-channel MOS transistor
The transistor 20 is cut off, and the source line 14 becomes the ground level.

Of the plurality of bit lines, only the bit line BLm corresponding to the selected cell 10 is connected to the sense amplifier 30 by the selection gate 22, and 1V is applied to the selected bit line BLm to start the sensing operation.

Here, if the device size of the N-channel MOS transistor 16 is set to a sufficiently large value and the voltage drop is set to a level that can be ignored, there is no concern that the read characteristics will deteriorate.

The method of the third embodiment is characterized in that the polarities of the source and drain of the memory cell are inverted during the write operation and the read operation. In particular, in a split-gate non-volatile memory, by adopting a memory array configuration in which a floating gate is arranged on the source side where the potential is low during a read operation, electrons are injected into the floating gate during a read operation and the threshold voltage rises. On the other hand, the variation can be made extremely small, and the data retention characteristic can be dramatically improved.

Although the NOR type memory cell array has been described in the embodiment of the present invention, the present invention can be applied to other array configurations such as NAND type, and the same operation and effect can be expected.

In addition to the floating gate type non-volatile semiconductor memory device, MNOS or MONOS using a thin film including a trap level such as a silicon nitride film as a gate insulating film.
The present invention can be applied to a nonvolatile semiconductor memory device called a structure, and the same operation and effect can be obtained.

Further, although the MOS transistor is inserted between the source line and the ground in the above embodiment, any element having a resistance component may be used, and a resistance element or wiring material using polysilicon or an active region is used. A resistor, a diode or the like may be used.

[0077]

As described above, by applying the present invention, the source terminal potential of the non-selected cell which receives the write drain disturb during the write operation is made higher than the control gate potential, thereby causing the write drain disturb. The sub-threshold leakage current can be reduced and the source potential during the read operation is kept lower than the source potential during the write operation so that the memory cell current during the read operation does not decrease. The stable sense amplifier operation and high speed can be maintained. In this case, as another means for suppressing the subthreshold leakage current, an internal power supply circuit for generating a negative voltage unlike the method of applying a negative potential to a non-selected word line during a write operation is unnecessary, which increases the chip area. And increase in power consumption.

Further, in adjusting the source potential in order to suppress the subthreshold leakage current, it can be realized by a relatively simple structure of switching the resistance value. Further, it is possible to adopt an extremely simple configuration of parallel connection of MOS transistors. Alternatively,
Using a triple well process MOS transistor,
The number of MOS transistors may be one, and the configuration can be further simplified. In addition, since the forward voltage of the pn junction is used, even if the write current of the entire array changes, the source during the write operation is changed. The fluctuation of the line potential is small, and the stability of the operation can be secured.

As another mode, the polarity of the source / drain terminals is inverted during the write operation, and the drain potential of the memory cell receiving the write drain disturb is set lower than the source potential, which causes the write drain disturb. The subthreshold leakage current can be reduced.

Further, as a structure for reversing the polarities of the source / drain terminals at the time of writing operation, if the bit line is grounded through an element having a resistance component, it can be relatively easily realized.

In summary, according to the present invention, it is possible to obtain a memory array that is resistant to write / drain disturb without impairing the stability of sense amplifier operation and access time, and is a nonvolatile memory of high performance and excellent reliability. Extremely effective in realizing a flexible semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a memory array configuration diagram in a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a memory array configuration diagram in a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 3 is a memory array configuration diagram in a nonvolatile semiconductor memory device according to a third embodiment of the present invention.

FIG. 4 is a memory array configuration diagram in a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

10 ... Selected memory cell 11 ... Memory cell 12 subjected to write drain disturb ... Word line 13 ... Bit line 14 ... Source line 15 ... N-channel MOS transistor 16 ... N-channel MOS transistor 17 ... Gate terminal 18 ... N-channel of triple well structure MOS transistor 19 ... Gate terminal 20 ... P-channel MOS transistor 21 ... Common gate terminal 22 ... Select gate 30 ... Sense amplifier

Claims (6)

[Claims] 1. A plurality of word lines having a plurality of non-volatile semiconductor memory elements arranged in an array and having a gate electrode connected in common and a plurality of bit lines having a drain electrode connected in common and 1
A source line in which all source electrodes in one array are commonly connected, and means for selecting one of the plurality of nonvolatile semiconductor memory elements, and a channel of the selected nonvolatile semiconductor memory element And a means for performing a second operation of determining the magnitude of the current flowing through the channel of the selected nonvolatile semiconductor memory element and outputting the current. A non-selected storage element sharing a bit line with the storage element selected in the first operation, the potential of the source applied to the non-selected storage element is higher than the potential of the word line of the non-selected storage element. , And the source potential of the storage element selected in the second operation is applied to the non-selected storage element sharing a bit line with the storage element selected in the first operation. The nonvolatile semiconductor memory device characterized by being configured to lower than. 2. A plurality of word lines having a plurality of non-volatile semiconductor memory elements arranged in an array and having a gate electrode connected in common and a plurality of bit lines having a drain electrode connected in common and 1
A source line in which all source electrodes in one array are commonly connected, and means for selecting one of the plurality of nonvolatile semiconductor memory elements, and a channel of the selected nonvolatile semiconductor memory element And a means for performing a second operation of determining the magnitude of the current flowing through the channel of the selected nonvolatile semiconductor memory element and outputting the current. A source line of the nonvolatile semiconductor memory element array is grounded through an element having a resistance component, and has a means for switching the resistance value of the element between the first operation and the second operation, A nonvolatile semiconductor memory device, wherein a resistance value during the first operation is higher than a resistance value during the second operation. 3. The means for switching the resistance value of the element having the resistance component is configured such that a plurality of MOS transistors are connected in parallel and the gate potential of at least one MOS transistor among the plurality of MOS transistors is switched. The nonvolatile semiconductor memory device according to claim 2, wherein the nonvolatile semiconductor memory device is a nonvolatile semiconductor memory device. 4. The means for switching the resistance value of the element having the resistance component, wherein the semiconductor well of a MOS transistor formed on the surface of the semiconductor well electrically separated from the semiconductor substrate is connected to the drain, The non-volatile semiconductor memory device according to claim 2, wherein the non-volatile semiconductor memory device is configured to switch a gate potential. 5. A plurality of non-volatile semiconductor memory elements arranged in an array, a plurality of word lines having gate electrodes commonly connected, and a plurality of bit lines having drain electrodes commonly connected, and 1
A source line in which all source electrodes in one array are commonly connected, and means for selecting one of the plurality of nonvolatile semiconductor memory elements, and a channel of the selected nonvolatile semiconductor memory element And a means for performing a second operation of determining the magnitude of the current flowing through the channel of the selected nonvolatile semiconductor memory element and outputting the current. And a potential of the drain applied to the non-selected storage element sharing the bit line with the storage element selected in the first operation is lower than a potential of the source line of the non-selected storage element, and selected in the second operation. The nonvolatile semiconductor memory device, wherein the drain potential of the stored memory element is higher than the source potential. 6. The bit line of the non-volatile semiconductor memory element array is configured to be grounded through an element having a resistance component during the first operation. Nonvolatile semiconductor memory device.