JP2003168754A - Manufacturing method of package for semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a package for a semiconductor element without generating cracks or cutouts on an insulation substrate even when the insulation substrates are collided hard against each other. <P>SOLUTION: A metallized layer 6 for connecting, which is adhered to the outer peripheral side surface 1b of the insulation substrate 1, is ground and removed but not all is removed so that a part of the layer 6 remains. One part of the metallized layer 6 for connection, which remains on the outer peripheral side surface 1b of the insulation substrate 1, functions as a shock absorbing member for absorbing shock whereby the generation of cracks or cutouts on the insulation substrate 1 can be prevented even when the insulation substrates are collided hard against each other. <P>COPYRIGHT: (C)2003,JPO

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device housing package for housing a semiconductor device. 2. Description of the Related Art Conventionally, a dual-in-line type semiconductor element housing package has been known as a semiconductor element housing package for housing a semiconductor element. [0003] Such a dual-inline type semiconductor element housing package is formed by laminating a plurality of ceramic layers, such as an aluminum oxide sintered body, and the semiconductor element is housed in a substantially central portion of the upper surface thereof. A substantially square plate-shaped insulating base having a concave portion, a plurality of external lead terminals joined to a pair of outer peripheral side surfaces parallel to each other in a row, and an airtight sealing of the concave portion of the insulating base. Metal cover. A plurality of metallization layers for wiring, each electrically connected to the external lead terminal, are applied to the insulating base from the inside of the recess to a pair of outer peripheral side surfaces to which the external lead terminal is joined. A metallization layer for fixing a semiconductor element is fixed on the bottom surface of the concave portion, and a metallizing layer for sealing for bonding a metal lid is formed on the upper surface so as to surround the concave portion. ing. The semiconductor element is fixed to the metallized layer for fixing the semiconductor element, which is adhered to the bottom surface of the concave portion of the insulating base, through a brazing material such as a gold-silicon alloy.
Each electrode of the semiconductor element is connected to a metallization layer for wiring in the concave portion via a bonding wire, and thereafter, a metal cover is formed on the metallization layer for sealing on the upper surface of the insulating substrate via a brazing material such as a gold-tin alloy. And a semiconductor device as a final product is formed by hermetically sealing the semiconductor element in the concave portion of the insulating base, and the semiconductor device is internally formed by connecting external lead terminals to wiring conductors of an external electric circuit board. Is electrically connected to an external electric circuit. Such a package for accommodating a semiconductor element prevents the metallization layer for wiring, the metallization layer for fixing the semiconductor element, the metallization layer for sealing, and the external lead terminals, which are adhered to the insulating base, from being oxidized and corroded. The connection between the metallization layer and the bonding wire, the connection between the metallization layer for fixing the semiconductor element and the semiconductor element, the connection between the metallization layer for sealing and the metal cover, and the connection between the external lead terminal and the wiring conductor of the external electric circuit board. In general, a plating metal layer composed of a nickel plating layer and a gold plating layer is sequentially deposited on the surface of each metallized layer and the surface of the external lead terminal by an electrolytic plating method in order to improve the quality. In order to apply a plating metal layer to the surface of each metallization layer and external lead terminals by electrolytic plating, one of the metallization layers for wiring, the metallization layer for fixing the semiconductor element, and the metallization layer for encapsulation are used. A plurality of plating extraction metallization layers are independently formed in advance on one outer peripheral surface adjacent to a pair of outer peripheral surfaces to which the external lead terminals of the insulating base are joined, and these plating extraction metallizing layers are formed. A metallization layer for connecting each plating lead metallization layer to be electrically connected in common is applied to the outer peripheral side surface derived from the tie bar, and a tie bar for electrically connecting each external lead terminal to each column electrically in common is further provided. By providing the metallized layer for wiring, the metallized layer for fixing the semiconductor element, and the metallized layer for sealing, The rise layer and the external lead terminals are electrically connected in common, and thereafter, for example, through a tie bar electrically connecting each external lead terminal to each metallized layer and the external lead terminals, for electrolytic plating. A method is employed in which a charge is supplied to deposit a plating metal layer by electrolytic plating on the exposed surfaces of each metallized layer and the external lead terminals. [0008] Finally, the metallization layer for connection, which is applied to the outer peripheral side surface of the insulating base, is polished and removed by using a mechanical polishing method, and the tie bars connecting the lead terminals are cut and removed to thereby remove each metallization. The layers are made electrically independent. However, in order to electrically isolate each metallized layer on which a plated metal layer is formed by electrolytic plating, a metallization for connection formed on an outer peripheral side surface of an insulating base is used. If the layer is polished and removed by employing a mechanical polishing method, a slight step is formed on the outer peripheral side surface of the insulating base by polishing. If such a step is formed on the outer peripheral side surface of the insulating base, cracks and chips are likely to occur from the step when a mechanical shock is applied to the step from the outside. Recently, when a semiconductor device is manufactured, an operation of accommodating a semiconductor element in a concave portion of an insulating base and a process of connecting an electrode of the semiconductor element to a metallization layer for wiring in the concave portion are performed on an automated manufacturing line. Is being done. In such an automated manufacturing line, a large number of semiconductor element housing packages are sequentially dropped at high speed using an inclined surface in order to move the semiconductor element housing packages on the manufacturing line, or A method has been adopted in which compressed air is blown onto a semiconductor element storage package to sequentially move the package at high speed. Therefore, the insulating substrates repeatedly collide with each other violently on the manufacturing line, and cracks or chips are likely to occur in the insulating substrate starting from the steps formed by polishing formed on the outer peripheral side surface of the insulating substrate. There has been a problem that airtight failure due to chipping or chipping, disconnection of the metallization layer for wiring or the like occurs, and the function as a package is lost, or a semiconductor device manufacturing line is stopped due to fragments of the insulating base. The present invention has been completed in view of the above-mentioned problems, and an object of the present invention is to provide the insulating substrate with cracks and chips even if the insulating substrates repeatedly collide with each other on a production line of an electronic device. Can be effectively prevented from occurring, and as a result, a highly reliable semiconductor element housing without losing the function as a package or stopping the semiconductor device manufacturing line due to debris of the insulating base. To provide a package. According to the present invention, there is provided a method of manufacturing a package for accommodating a semiconductor element, the method comprising stacking a plurality of ceramic layers, and having an upper surface having a recess having a recess for accommodating the semiconductor element. A plurality of wiring metallization layers extending from the inside of the recess to a pair of outer peripheral side surfaces of the insulation base parallel to each other, and a semiconductor element fixing metallization layer attached to the bottom of the recess and / or the insulation. A sealing metallization layer attached to the upper surface of the base so as to surround the concave portion; and one of the wiring metallization layers and the semiconductor element fixing metallization layer and / or the sealing metallization layer. A plurality of plating lead-out metallization layers independently derived from each other on one outer peripheral side adjacent to the pair of outer peripheral side faces; A metallization layer for connection is provided on the outer peripheral side surface so as to electrically connect the plurality of metallization layers for plating extraction to each other in common, and the pair of outer peripheral side surfaces of the insulating base are connected to each other by a tie bar. Brazing a plurality of electrically connected external lead terminals in a row so as to be electrically connected to the wiring metallization layer, and then fixing the wiring metallization layer and the semiconductor element. Depositing a plating metal layer on the surfaces of the metallization layer and / or the metallization layer for sealing and the external lead terminals by electrolytic plating, and then connecting the metallization layer for connection with the metallization layer for plating extraction. Are electrically separated from each other, and at least a part of the metallization layer for connection is at least 0.
And polishing and removing the insulating substrate so as to remain on the one outer peripheral side surface of the insulating base with an area of 25 mm ² or more. According to the method of manufacturing a package for accommodating a semiconductor element of the present invention, a plating metal layer is applied to the surface of each metallization layer and external lead terminals by electrolytic plating, and then a part of the connection metallization layer is formed. Is at least 0.25m
The metallization layer for connection remaining on the outer peripheral side surface of the insulating substrate is polished and removed so as to remain on the outer peripheral side surface of the insulating substrate with an area of at least m ^2. As a role.
Therefore, even if the insulating substrates of the package for accommodating the semiconductor element obtained according to the present invention violently collide with each other on, for example, a production line of a semiconductor device, the impact is reduced by the metallization layer for connection remaining on the outer peripheral side surface of the insulating substrate. Collision is prevented, and as a result, it is possible to effectively prevent the occurrence of cracks or chips in the insulating base, to lose the function as a package, or to stop the semiconductor device manufacturing line due to debris of the insulating base. It is possible to provide a method for manufacturing a highly reliable package for housing semiconductor elements without performing the method. Further, since no cracks, chips or the like occur in the insulating base of the package for housing semiconductor elements, the package for housing semiconductor elements can be manufactured with a high yield. The present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a perspective view showing an example of an embodiment of a package for housing a semiconductor element manufactured by the manufacturing method of the present invention, wherein 1 is an insulating base, 2 is a metallization layer for wiring, and 3 is a metallization for fixing a semiconductor element. Layers 4 and 4 are metallization layers for sealing, and 5 is an external lead terminal. The insulating substrate 1 has a substantially rectangular flat plate shape made of a ceramic material, and has a concave portion 1a for accommodating a semiconductor element formed on an upper surface thereof. The semiconductor element is accommodated in the concave portion 1a. The insulating substrate 1 is provided with a plurality of metallization layers 2 for wiring extending from the inside of the recess 1a to a pair of outer peripheral side surfaces 1c parallel to each other. 3 is attached,
Further, a metallization layer 4 for sealing is attached on the upper surface so as to surround the concave portion 1a. The metallization layer 2 for wiring functions as a conductive path for electrically connecting each electrode of the semiconductor element mounted in the recess 1 a to the external lead terminal 5. And the recess 1
The electrode of the semiconductor element is electrically connected to the portion exposed in a through a bonding wire. A plurality of external lead terminals 5
Are brazed through a row of brazing material such as silver brazing. The metallized layer 3 for fixing the semiconductor element on the bottom surface of the concave portion 1a functions as a base metal for fixing the semiconductor element on the bottom surface of the concave portion 1a. The semiconductor element is fixed in the recess 1a by fixing the element through a brazing material such as a gold-silicon alloy. The metallizing layer 4 for sealing, which is attached on the upper surface of the insulating substrate 1 so as to surround the concave portion 1a, functions as a base metal for bonding a metal cover to the insulating substrate 1, and this sealing metal A substantially flat metal cover made of a metal such as an iron-nickel-cobalt alloy is joined to the metallization layer 4 via a brazing material such as a gold-tin alloy. The external lead terminal 5 is made of a metal such as an iron-nickel alloy or an iron-nickel-cobalt alloy.
One end thereof is brazed via a brazing material such as a silver-copper alloy to a metallization layer 2 for wiring led out to a pair of outer peripheral side surfaces 1 c of the insulating base 1, and the other ends are respectively directed downward of the insulating base 1. It is arranged to protrude. The external lead terminal 5 functions as a connection terminal for electrically connecting each electrode of the semiconductor element housed in the concave portion 1a to an external electric circuit. Each electrode of the semiconductor element is electrically connected to the external electric circuit by connecting to the wiring conductor of the external electric circuit board via solder or the like. Further, in this package for accommodating a semiconductor element, the surface of the metallization layer 2 for wiring, the metallization layer 3 for fixing the semiconductor element, the metallization layer 4 for encapsulation, and the external lead terminal 5 are provided with nickel having a thickness of about 1 to 10 μm. A plating layer and a gold plating layer having a thickness of about 0.1 to 3 μm are sequentially applied by an electrolytic plating method. As described above, the surface of the metallized layer 2 for wiring, the metallized layer 3 for fixing the semiconductor element, the metallized layer 4 for sealing, and the external lead terminals 5 have a thickness of 1 to 10 mm.
Nickel plating layer of about μm and thickness of 0.1 to 3 μm
Since the gold plating layers having the same degree are sequentially applied by the electrolytic plating method, the metallization layer 2 for wiring, the metallization layer 3 for fixing the semiconductor element, the metallization layer 4 for sealing, and the external lead terminal 5 are oxidized and corroded. It is effectively prevented, and the connection between the metallization layer 2 for wiring and the bonding wire, the bonding between the metallization layer 3 for fixing the semiconductor element and the semiconductor element, the bonding between the metallization layer 4 for sealing and the metal cover, and the external lead terminals 5 and the wiring conductor of the external electric circuit board are connected well. According to the package for accommodating a semiconductor element, the semiconductor element is fixed to the metallization layer 3 for fixing the semiconductor element, which is attached to the bottom surface of the concave portion 1a of the insulating base 1, and each electrode of the semiconductor element is connected. The metallization layer 2 is electrically connected to the wiring metallization layer 2 via a bonding wire. Thereafter, a metal lid is bonded to the metallization layer 4 for sealing, and the semiconductor element is hermetically sealed in the recess 1a. A semiconductor device as a product is completed. Next, a plating metal layer is formed on the surfaces of the metallization layer 2 for wiring, the metallization layer 3 for fixing the semiconductor element, the metallization layer 4 for encapsulation, and the external lead terminals 5 in the above-mentioned package for housing a semiconductor element by electrolytic plating. A method for manufacturing the semiconductor element housing package of the present invention to be attached will be described. First, as shown in a perspective view in FIG. 2, a plurality of ceramic layers are laminated, and an insulating substrate 1 having a concave portion 1a for accommodating a semiconductor element on an upper surface is placed on the insulating substrate 1 from the concave portion 1a. A plurality of wiring metallization layers 2 extending to a pair of parallel outer peripheral side surfaces 1c, a semiconductor element fixing metallization layer 3 provided on the bottom surface of the recess 1a, and a metallization layer 3 provided on the upper surface of the insulating base 1 so as to surround the recess 1a. The metallized layer 4 for sealing and one of the metallized layers 2 for wiring, the metallized layer 3 for fixing the semiconductor element and the metallized layer 4 for sealing are formed on the outer peripheral side 1b adjacent to the outer peripheral side 1c of the insulating base 1. A plurality of metallization layers 2a, 3a, 4a for lead-out independently derived from each other, and metallization layers 2a, 3a, 4a for plating-out are electrically connected in common to the outer peripheral side surface 1b. The connection metallization layer 6 thus adhered is provided, and a plurality of external lead terminals 5 electrically connected to each other by the tie bars 5a are provided on the pair of outer peripheral side surfaces 1c of the insulating base 1. Are brazed in a row so that they are electrically connected to each other. As described above, one of the metallization layers 2 for wiring, the metallization layer 3 for fixing the semiconductor element, and the metallization layer 4 for sealing are formed on the insulating base 1 from the outer peripheral side surface 1 of the insulating base 1.
b, a plurality of metallization layers 2a, 3a, 4a for lead-out independently of each other are provided, and the metallization layers 2a, 3a, 4a for lead-out plating are formed on the outer peripheral side surface 1b from which the metallization layers 2a, 3a, 4a are led out.
a, 3a and 4a are electrically connected in common, and a metallization layer 6 for connection is adhered, and the external lead terminals 5 are connected with tie bars 5a, so that the metallization layer 3 for fixing the semiconductor element and the metallization layer 3 for sealing are formed. Metalized layer 4 is tie bar 5a
Is electrically connected to The insulating substrate 1 is made of a ceramic such as a sintered body of aluminum oxide, a sintered body of aluminum nitride, a sintered body of mullite, a sintered body of silicon carbide, a sintered body of silicon nitride, and a glass-ceramic. If it is made of a material, for example, an aluminum oxide sintered body, an appropriate organic binder and a solvent are added to and mixed with the raw material powder of aluminum oxide, silicon oxide, calcium oxide, magnesium oxide, etc. This was formed into a sheet by employing a sheet forming method such as a doctor blade method to obtain a plurality of ceramic green sheets, and then these ceramic green sheets were subjected to an appropriate punching process and laminated vertically. A green ceramic molded body for the insulating substrate 1 was obtained. Thereafter, the green ceramic molded body was heated in a reducing atmosphere at a temperature of about 1600 ° C. It is manufactured by firing at a temperature. The metallization layer 2 for wiring, the metallization layer 3 for fixing the semiconductor element, the metallization layer 4 for encapsulation, the metallization layer 2a, 3a, 4a for plating, and the metallization layer 6 for connection are made of tungsten, molybdenum, copper, A metal paste made of a metal powder of silver or the like, for example, a metal paste obtained by adding and mixing an appropriate organic binder and solvent to tungsten powder is applied to a ceramic green sheet or green ceramic molded body for the insulating substrate 1 by a conventionally known screen printing method. A predetermined pattern is printed and applied, and is fired together with the green ceramic molded body for the insulating substrate 1 to be formed on the insulating substrate 1. Further, the external lead terminals 5 are formed into a predetermined shape by punching a plate material of an iron-nickel alloy or an iron-nickel-cobalt alloy, and are led out to a pair of outer peripheral side surfaces 1c of the insulating base 1. An electroless nickel plating layer of about 0.2 to 2 μm is previously deposited on the exposed surface of the wiring metallization layer 2, and one end of the metallization layer 2 is sandwiched between the wiring metallization layer 2 and a foil-like brazing material, for example. These are brought into contact with each other and heated to a temperature equal to or higher than the melting point of the brazing material, thereby brazing to the metallization layer 2 for wiring. At this time, since the other ends of the external lead terminals 5 are integrally connected by the tie bars 5a, it is possible to hold the external lead terminals 5 at regular intervals and to braze the insulating base 1 accurately. It will be easier. Further, when a plating metal layer is applied by an electrolytic plating method described later, the metallization layer 2 for wiring, the metallization layer 3 for fixing the semiconductor element, the metallization layer 4 for sealing, and the external lead terminal 5 are provided via the tie bar 5a. An electric charge for electrolytic plating can be supplied. The tie bar 5a may be cut and removed after a semiconductor device is housed in a package to form a semiconductor device. Next, electric charges for electrolytic plating are supplied to all the metallization layers 2 for wiring, the metallization layers 3 for fixing semiconductor elements, the metallization layers 4 for encapsulation, and the external lead terminals 5 through tie bars 5a to perform electrolytic plating. The plating metal layer is applied to the surfaces of the metallization layer 2 for wiring, the metallization layer 3 for fixing the semiconductor element, the metallization layer 4 for sealing, and the external lead terminals 5 by plating.
In this case, the metallization layers 2a, 3a,
4a and metallization layer 6 for connection and tie bar 5a
The metallization layer 2 for wiring, the metallization layer 3 for fixing the semiconductor element, the metallization layer 4 for encapsulation, and the external lead terminal 5 are electrically connected in common through the connection. The plating metal layer can be simultaneously applied to the surfaces of the metallizing layer 3 for sealing, the metallizing layer 4 for sealing, and the external lead terminals 5 by electrolytic plating. In addition, as such a plating metal layer, an electrolytic nickel plating layer having a thickness of about 1 to 10 μm and an electrolytic gold plating layer having a thickness of about 0.1 to 3 μm are sequentially applied. Finally, as shown in an enlarged sectional view of the main part in FIG. 3, the connection metallization layer 6 adhered to the outer peripheral side surface 1b of the insulating base 1 is replaced with the plating extraction metallization layer 2
a, 3a, and 4a are polished and removed so as to be electrically separated from each other and such that a portion of the connection metallized layer 6 remains on the outer peripheral side surface 1b with an area of at least 0.25 mm ² or more. The metallized layer 3 and the sealing metallized layer 4 are electrically independent. As a result, the metallized layer 2 for wiring, the metallized layer 3 for fixing the semiconductor element, the metallized layer 4 for encapsulation, and the surface of the external lead terminal 5 are covered with a plated metal layer by electrolytic plating. The semiconductor element housing package shown in FIG. 1 in which the fixing metallization layer 3 and the sealing metallization layer 4 are electrically independent is obtained. At this time, according to the method for manufacturing a package for housing a semiconductor element of the present invention, a part of the metallization layer 6 for connection is formed on the outer peripheral side face 1b of the insulating base 1 by at least 0.25 mm ^2.
It is important and necessary that it be polished and removed so as to remain in the above area. As described above, a part of the metallization layer 6 for connection is formed on the outer peripheral side surface 1b of the insulating base 1 by at least 0.25 mm.
^Since the connection metallized layer 6 remaining on the outer peripheral side surface 1b of the insulating base 1 serves as a shock absorbing cushioning material and a collision preventing member, it is polished and removed so as to remain in ^two or more areas. Therefore, even if the insulating bases 1 of the package for accommodating the semiconductor element obtained according to the present invention collide violently on, for example, a production line of a semiconductor device, the impact will not affect the connection metallization layer 6 remaining on the outer peripheral side surface 1b of the insulating base 1. Mitigation and collision avoidance, resulting in
It is possible to effectively prevent the occurrence of cracks, chips, and the like in the insulating base 1, and to maintain reliability without losing the function as a package or stopping the production line of the semiconductor device due to fragments of the insulating base 1. It is possible to provide a semiconductor device housing package having high reliability. If the area of the connection metallization layer 6 remaining on the outer peripheral side surface 1b of the insulating base 1 is less than 0.25 mm ² ,
When the insulating bases 1 collide violently on the semiconductor device manufacturing line, it is difficult to sufficiently absorb and mitigate the impact and prevent the collision by the connection metallization layer 6 remaining on the outer peripheral side surface 1b of the insulating base 1. There is a tendency. Therefore,
Connection metallization layer 6 remaining on outer peripheral side surface 1b of insulating base 1
Is specified to be 0.25 mm ² or more. The area of the connection metallization layer 6 remaining on the outer peripheral side surface 1b is preferably 4 mm ² or less, and if it exceeds 4 mm ² , the metallization layers 2a, 3a, and 4a for plating extraction are electrically separated from each other. In addition, since the effect of absorbing and reducing impact and preventing collision can be sufficiently obtained with an area of 4 mm ² or less, the area of the metallization layer 6 for connection tends to be unnecessarily large. The thickness of the connection metallization layer 6 is 10 to
When the thickness is less than 10 μm, the effect of absorbing and reducing impact and preventing collision is reduced, and cracks and chips are likely to occur in the insulating substrate 1. When the thickness exceeds 50 μm, the adhesion strength of the metallization layer 6 for connection is reduced. As a result, the metallization layer 6 for connection tends to be brittle. More preferably, it is 20 to 30 μm. The present invention is not limited to the above-described embodiment, and it goes without saying that various changes can be made without departing from the scope of the present invention. For example, in the above-described embodiment, the connection metallization layer 6 is polished and removed so that the lower end remains, but as shown in the enlarged perspective view of the main part in FIG. The lower end may be polished and removed so as to remain, or as shown in an enlarged perspective view of a main part in FIG. 5, may be polished and removed such that both left and right ends thereof remain. Also,
In one example of the above-described embodiment, a part of the connection metallized conductor 6 is left on only one outer peripheral side surface 1b. However, the connection metallized conductor 6 is provided on both outer peripheral side surfaces 1b, and both connection metallized layers are provided. 6 may remain. Further, in one example of the above-described embodiment, a case has been described in which a semiconductor element storage package provided with both the semiconductor element fixing metallization layer 3 and the sealing metallization layer 4 is manufactured. The manufacturing method of the present invention can also be applied to the case of manufacturing a semiconductor device housing package provided with one of the metallizing layer 3 for sealing and the metallizing layer 4 for sealing. As described above, according to the method of manufacturing a package for housing a semiconductor element of the present invention, a plating metal layer is applied to the surface of each metallized layer and external lead terminals by electrolytic plating. After that, the metallization layer for connection is polished and removed so that a part of the metallization layer remains on the outer peripheral surface of the insulating substrate with an area of at least 0.25 mm ² or more. It serves as a cushioning material for the vehicle and a collision prevention member. Therefore, even if the insulating substrates of the package for accommodating the semiconductor element obtained according to the present invention violently collide with each other on, for example, a production line of a semiconductor device, the impact is reduced by the metallization layer for connection remaining on the outer peripheral side surface of the insulating substrate. Collision is prevented, and as a result, cracks, chips, and the like can be effectively prevented from being generated in the insulating base, and the function as a package for storing semiconductor elements is lost. A method for manufacturing a highly reliable package for housing a semiconductor element without stopping the semiconductor device can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing an example of an embodiment of a semiconductor element housing package manufactured by a manufacturing method of the present invention. FIG. 2 is a perspective view of a semiconductor device housing package for explaining a manufacturing method of the present invention. FIG. 3 is an enlarged perspective view of a main part of a package for housing a semiconductor element for explaining a manufacturing method of the present invention. FIG. 4 is an enlarged perspective view of a main part of a package for housing a semiconductor element for explaining another example of the manufacturing method of the present invention. FIG. 5 is an enlarged perspective view of a main part of a package for housing a semiconductor element for explaining still another example of the manufacturing method of the present invention. [Description of Signs] 1: Insulating base 2: Metallization layer for wiring 3: Metallization layer for fixing semiconductor element 4: Metallization layer for sealing 5: External lead terminal 6: Metallization layer for connection

Claims (1)

Claims: 1. An insulating substrate having a substantially rectangular flat plate shape formed by laminating a plurality of ceramic layers and having a recess for accommodating a semiconductor element on an upper surface thereof. A plurality of metallization layers for wiring extending to a pair of parallel outer peripheral side surfaces, and a metallization layer for fixing a semiconductor element attached to the bottom surface of the recess and / or a metallization layer attached to an upper surface of the insulating base so as to surround the recess. A metallization layer for sealing, and one of the metallization layers for wiring and one of the metallization layers for fixing the semiconductor element and / or the metallization layer for sealing on one of outer peripheral side surfaces adjacent to the pair of outer peripheral side surfaces of the insulating base; A plurality of plating extraction metallization layers independently derived from each other and the plurality of plating extraction metallization layers are electrically connected to each other on the one outer peripheral side surface of the insulating base. A plurality of external lead terminals electrically connected to each other by a tie bar on the pair of outer peripheral side surfaces of the insulating base. A step of brazing the metallization layer so as to be electrically connected to the metallization layer, and then the wiring metallization layer, the metallization layer for fixing the semiconductor element and / or the metallization layer for sealing, and the external part. A step of applying a plating metal layer to the surface of the lead terminal by electrolytic plating, and then the connecting metallized layer so that the metallized layers for plating extraction are electrically separated from each other; A step of polishing and removing a part of the metallized layer so as to remain on the one outer peripheral side surface of the insulating substrate with an area of at least 0.25 mm ² or more; A method for manufacturing a package for housing a semiconductor element, comprising: