JP2003167559A - Planar display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve constraints on low power consumption dependent on the number of bits of display data. <P>SOLUTION: A liquid crystal display device is provided with a plurality of display pixels PX composing a display screen, a scanning line- and signal line driving circuits 3, 4 for dividing a plurality of the display data into at least two partial display data of the equal number of bits and sequentially outputting them to a plurality of the display data each, and a plurality of data holding means for holing the partial display data, which are sequentially outputted to the corresponding display pixels PX from each of the driving circuits 3, 4, in a plurality of different memory blocks, respectively, and driving the corresponding display pixels. The driving circuits 3, 4 are configured so as to compare the contents of at least two partial display data with each other, and output only any one of these partial display data when the contents coincide and make the memory blocks hold it in common. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device in which each display pixel is driven corresponding to a plurality of bits of display data, and more particularly, a flat panel display device in which display data is held in a memory section provided for each display pixel. Regarding the device.

[0002]

2. Description of the Related Art For example, a liquid crystal display device is characterized by being thin, small, and lightweight, and is used in a mobile phone or a PDA (Portable Digital As
It is widely used as an image monitor for portable terminal equipment such as a computer. Since such portable terminal devices generally operate using a rechargeable battery as a power source, the consumption rate of the battery greatly affects the usable time. For these reasons, low power consumption of liquid crystal display devices has been actively studied.

Recently, SRAM (Static Random Acce
A memory technology typified by ss Memory) is used to reduce the power consumption of a liquid crystal display device. This SRAM
In the technology, a static memory unit is provided for each of a plurality of display pixels that form a display screen.

In each display pixel, when the pixel switch selectively takes in digital display data sequentially supplied from the external drive circuit, the static memory section holds this display data and drives the liquid crystal capacitance in accordance with this display data. To do.
With such a configuration, when it is not necessary to update the image frequently, the output operation of the external drive circuit is temporarily stopped to maintain the display image as a still image, which can reduce power consumption. is there. By the way, when a multi-gradation image is displayed on such a liquid crystal display device, for example, a multi-bit static memory unit is provided in each display pixel, and each display pixel is divided into a plurality of area-weighted sub-pixels, It is conceivable to allocate the 1-bit static memory of 1 to each of these sub-pixels. For example, if 6-bit, 64-gradation display is realized, each display pixel
It is divided into sub-pixels weighted with an area ratio of 1: 2: 4: 8: 16: 32.

[0005]

In such a configuration, it is conceivable to serially transmit, for example, 6-bit display data to each display pixel, but the transfer rate is increased as the number of gradations increases. It is necessary to increase the power consumption during normal display. The present invention has been made in view of the above technical problems, and it is an object of the present invention to provide a flat display device capable of improving the constraint of low power consumption depending on the number of bits of display data.

[0006]

According to the present invention, a plurality of display pixels forming a display screen, and display data of a plurality of bits for each of the plurality of display pixels are provided with at least two partial display data having the same number of bits. Drive circuits for dividing and sequentially outputting to the corresponding display pixels, and a plurality of data holding means for holding the partial display data sequentially output from the respective drive circuits to the plurality of different memory blocks to drive the corresponding display pixels. And a drive circuit that compares the contents of at least two partial display data, and if the contents match, outputs only one of the partial display data and holds it in each memory block in common. A configured flat panel display device is provided.

In this flat panel display device, the contents of at least two partial display data are compared by the drive circuit. When the contents match, the number of times of outputting these partial display data can be reduced, and accordingly, the drive circuit causes the data holding means to hold the display data, so that the power consumption can be reduced. As a result, it is possible to improve the constraint of low power consumption depending on the number of bits of display data.

[0008]

DETAILED DESCRIPTION OF THE INVENTION A liquid crystal display device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic circuit configuration of this liquid crystal display device, and FIG. 2 shows a circuit configuration around the display pixel shown in FIG.

This liquid crystal display device comprises a liquid crystal display panel 1 and a liquid crystal controller 2 for controlling the liquid crystal display panel 1. The liquid crystal display panel 1 has, for example, a structure in which the liquid crystal layer LQ is held between the array substrate AR and the counter substrate CT, and the liquid crystal controller 2 is arranged on a drive circuit substrate independent of the liquid crystal display panel 1.

The liquid crystal display panel 1 includes a plurality of liquid crystal display pixels PX arranged in a matrix to form a display screen DS.
A plurality of scanning line pairs Y (Y1 to Ym) formed along the rows of the plurality of liquid crystal display pixels PX, and a plurality of signal buses X (X1 to Xn) formed along the columns of the plurality of liquid crystal display pixels PX. , And a scanning line driving circuit 3 for driving the scanning line pairs Y1 to Ym, and a signal line driving circuit 4 for driving the signal buses X1 to Xn.

The liquid crystal controller 2 receives a digital video signal and a sync signal supplied from the outside, and receives 6-bit digital display data DATA and a vertical scanning control signal YC.
The T and horizontal scanning control signals XCT are generated. The vertical scanning control signal YCT includes, for example, a vertical start pulse and a vertical clock signal YCK, and is supplied to the scanning line driving circuit 3. The horizontal scanning control signal XCT includes a horizontal start pulse, a horizontal clock signal, a polarity inversion signal, etc., and is supplied to the signal line drive circuit 4 together with the display data DATA. The vertical clock signal YCK is also supplied to the signal line drive circuit 4 as the column pixel clock φ.

The scanning line driving circuit 3 includes a shift register circuit, and a vertical scanning control signal YC is supplied to the scanning line pairs Y1 to Ym sequentially for each vertical scanning (frame) period.
Controlled by T. The shift register circuit shifts a vertical start pulse supplied every one vertical scanning period in synchronization with a vertical clock signal YCK to select one of the plurality of scanning line pairs Y1 to Ym to select a selected scanning line pair. To output a scanning signal. Each of the scanning line pairs Y1 to Ym is composed of scanning lines G1 and G2 driven by different scanning signal waveforms, as will be described later.

The signal line drive circuit 4 has a shift register circuit, and 6-bit display data DAT in one horizontal scanning period (1H) in which each scanning line pair Y is driven by a scanning signal.
Control is performed by the horizontal scanning control signal XCT so that A of one row is fetched and these display data DATA are divided into upper 3 bits and lower 3 bits, and upper and lower partial display data are output to the signal buses X1 to Xn, respectively. To be done. Each of these signal buses X1 to Xn is composed of three signal lines for transmitting 3 bits of upper and lower part display data in parallel.

The liquid crystal display panel 1 includes signal buses X1 to Xn.
And a plurality of data holding units PD respectively arranged near the intersections of the scanning line pairs Y1 to Ym and driving a plurality of display pixels PX.

As shown in FIG. 2, each data holding section PD has three pixel switches S for fetching upper partial display data from the signal bus X when driven through the scanning line G1.
W3 to SW5, three pixel switches SW0 to SW2 that capture lower order display data from the signal bus X when driven through the scanning line G2, and these pixel switches SW0 to SW0
It has six static memories M0 to M5 which hold the upper and lower part display data fetched by SW2 as display data DATA. The static memories M3 to M5 form a memory block MB1 holding the upper partial display data, and the static memories M0 to M2 form a memory block MB2 holding the lower partial display data. Here, the pixel switches SW0 to SW5 and the static memories M0 to M5 are composed of high mobility semiconductor elements such as low temperature polysilicon thin film transistors. Further, when the scanning line driving circuit 3 and the signal line driving circuit 4 are incorporated in the liquid crystal display panel 1 as described above, these may also be composed of high mobility semiconductor elements such as low temperature polysilicon thin film transistors. preferable.

Each liquid crystal display pixel PX is formed on the array substrate AR and divides the display pixel PX into six sub-pixels PE1 to PE6, and a common electrode C formed on the counter substrate CT.
E, and the pixel electrodes PE1 to PE6 and the common electrode C
The liquid crystal layer LQ is sandwiched between E via an alignment film (not shown). The pixel electrodes PE1 to PE6 receive the grayscale voltages corresponding to the first to sixth bits of the display data DATA held in the static memories M0 to M5 of the data holding unit PD, and the common electrode receives the common voltage Vcom. Connected. Furthermore, the pixel electrodes PE1 to PE1
The PE 4 is the first to sixth bits of the display data DATA stored in the static memories M1 to M6, that is, 2 ⁰ , 2 ¹ , 2 ² , 2 ³ , 2 ⁴ , 2 ⁵ between the grayscale voltages.
The area ratios are set so that the respective loads are given.

FIG. 3 shows a circuit configuration of a data output section provided in the signal line drive circuit 4 for each signal bus. The right side of the broken line shown in FIG. 3 is a configuration added to output 6-bit display data in 3-bit units.

The data output section serially / parallel converts the input display data corresponding to each signal bus, and holds the latch circuit 11, and the latch circuit 12 for sequentially latching the output from the latch circuit 11. 13, 15, 16, 17
And 22, a comparator 14, a delay circuit 18, a multiplexing circuit 19, an OR circuit 20 and an AND circuit 22.
The latch circuit 11 latches 6-bit display data DATA sequentially supplied to the display pixels PX of one column. The latch circuit 12 latches the upper 3 bits of the display data DATA latched by the latch circuit 11 as the upper partial display data, and the latch circuit 13 latches the lower 3 bits of the display data DATA latched by the latch circuit 11 to the lower partial display data. To latch as. The upper part display data is supplied from the latch circuit 12 to the input end of the latch circuit 16 and the input end A of the comparator 14, and the lower part display data is supplied from the latch circuit 13 to the input end of the latch circuit 17 and the input end B of the comparator 14. To be done. The comparator 14 compares 3 bits of the upper partial display data supplied to the input terminal A with 3 bits of the lower partial display data supplied to the input terminal B, and when these contents match, as shown in FIG. An output signal that is set to a high level is generated as a comparison result. The output signal of the comparator 14 is latched by the latch circuit 15 and the delay circuit 18
Is supplied to. The latch circuits 16 and 17 latch the upper portion display data and the lower portion display data at the same time as the operation of the latch circuit 15, and multiplex these to the multiplexing circuit 19
Supply to. By the way, the latch circuits 11, 12, 13,
15, 1617 and the multiplexing circuit 19 operate at the timing synchronized with the column pixel clock φ. The multiplexing circuit 19 switches the upper partial display data and the lower partial display data latched by the latch circuits 16 and 17 in this order in one horizontal scanning period (1H) defined by the column pixel clock φ and causes the latch circuit 22 to switch. Output. The delay circuit 18 delays the output timing of the comparison result latched by the latch circuit 15 by a fixed time, thereby performing timing adjustment for compensating the delay generated in the multiplexing circuit 19. The AND circuit 20 outputs the comparison result from the delay circuit 18 to the OR circuit 21 in synchronization with the column pixel clock φ. The latch circuit 22 synchronizes with the double column pixel clock 2φ supplied via the OR circuit 21 except when the output signal of the AND circuit 20 is set to the high level, and the upper partial display data and the lower partial display are respectively obtained. The data is sequentially latched and output to the signal bus X in the first half and the second half of one horizontal scanning period, respectively.

FIG. 4 shows the driving waveforms of the scanning signals supplied from the scanning line driving circuit 3 to the scanning lines G1 and G2 of each scanning line pair Y every horizontal scanning period. Here, the first half of one horizontal scanning period is assigned to a data output period period for outputting upper partial display data, and the latter half of one horizontal scanning period is assigned to a data output period for outputting lower partial display data. The scanning line G1 is continuously driven in the first half of one horizontal scanning period, and the scanning line G2 is continuously driven in the first and second half of the one horizontal scanning period. Here, the scanning line G1
Can be obtained by superimposing the vertical clock signal YCK on the scanning signal for the scanning line G2 obtained from the shift register circuit, for example.

When the signal line drive circuit 4 outputs the upper partial display data to the signal bus X in the first half of one horizontal scanning period, the upper partial display data is taken into the memory block MB1 via the pixel switches SW3 to SW5. Further, when the signal line driving circuit 4 outputs the lower-order display data to the signal bus X in the latter half of one horizontal scanning period, the lower-order display data is taken into the memory block via the pixel switches SW0 to SW2.

By the way, the display data DATA is, for example, "
000000 "," 111111 "," 100100 "
In the case of the contents such as, the comparator 14 detects that the upper 3 bits and the lower 3 bits of the display data DATA, that is, the upper partial display data and the lower partial display data match, and outputs the output rising as shown in FIG. Generate a signal. Accordingly, when the output signal of the AND circuit 20 is set to a high level in synchronization with the column pixel clock φ, the OR circuit 21 doubles the number of column pixels supplied to the latch circuit 22 as the sampling clock of the partial display signal. The clock 2φ is masked by the output signal of the AND circuit 20, and the latch operation of the latch circuit 22 is prohibited in the latter half of one horizontal scanning period. As a result, the output of the lower part display data is omitted.

On the other hand, since the scanning line G2 is continuously driven even in the first half of one horizontal scanning period, the upper partial display data is transferred through the pixel switches SW3 to SW5 to the memory block MB.
While being loaded into 1, it is also loaded into the memory block MB2 via the pixel switches SW0 to SW2. Even if the output of the lower part display data is omitted, the memory block MB2 is set to have an appropriate content.

In the above-mentioned liquid crystal display device, each liquid crystal display pixel PX has display data DAT held in the data holding section PD.
Since the gradation voltage corresponding to A can be received, the power supply to all the output parts of the signal line drive circuit 4 is cut off or the bias level is reduced when it is not necessary to change the display image frequently. By doing so, power consumption in the signal line driver circuit can be reduced. Further, since the upper 3 bits and the lower 3 bits of the display data DATA are supplied to the display pixels PX of each column via the three signal lines in two steps, the signals to be simultaneously driven by the signal line drive circuit 4. The number of lines can be reduced and the circuit scale of the signal line drive circuit 4 can be reduced. As a result, it is possible to improve the constraint of low power consumption depending on the number of bits of display data, that is, the number of gradations.

Further, in this liquid crystal display device, when the upper partial display data and the lower partial display data which are the upper 3 bits and the lower 3 bits of the display data DATA supplied to each display pixel PX have the same content, The data output unit of the signal line drive circuit 4 outputs the upper partial display data to the signal bus X in the first half of one horizontal scanning period and outputs the upper partial display data to the memory block MB1 of the corresponding data holding unit PD.
And MB2 are commonly held. As a result, the output of the lower part display data can be omitted and the data output normally required twice in one horizontal scanning period can be reduced to once. Therefore, the operating frequency of the output latch circuit 22 is reduced to half each time the upper 3 bits and the lower 3 bits of the display data DATA match, so that the power consumption can be automatically reduced. Furthermore, the power supply to the output part of the signal line drive circuit 4 and the bias level are not actively controlled, and the total display data DATA is set to "0000" for still image display, for example.
The power consumption can be reduced by merely setting the contents such as "00", "111111", and "100100".

The present invention is not limited to the above-described embodiment, and can be variously modified without departing from the gist thereof. That is, it can be applied to an organic EL display device and the like, and a DRAM or the like can be used as a memory. Further, the sub-pixel size is not necessarily weighted corresponding to the bits, but the area ratio may be compensated by changing the voltage of the memory power supply, for example. Further, in the above-described embodiment, the 6-bit display data is equally divided into the upper 3 bits and the lower 3 bits and is output twice to the signal bus X. However, when the number of bits of the display data is increased, the display data is displayed. The data may be equally divided into three or more partial data, and these may be sequentially output to the signal bus X. In this case, it is preferable to compare three or more partial data with each other and omit the data output between the partial data having the same contents.

[0027]

As described above, according to the present invention, it is possible to provide a flat display device capable of improving the constraint of low power consumption depending on the number of bits of display data.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic circuit configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration around the display pixel shown in FIG.

3 is a diagram showing a circuit configuration of a data output unit provided for each signal bus in the signal line drive circuit shown in FIG.

FIG. 4 is a diagram showing drive waveforms of scan signals supplied from the scan line drive circuit shown in FIG. 1 to signal line pairs.

5 is a time chart showing the operation of the data output unit shown in FIG.

[Explanation of symbols]

X: Signal bus Y: scanning line pair PD: Data holding unit PX ... Liquid crystal display pixel SW0 to SW5 ... Pixel switch M0 to M5 ... Static memory MB1, MB2 ... Memory block 14 ... Comparator 22 ... Latch circuit

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 2H093 NA54 NB07 NB11 NC09 NC11                       NC25 NC26 NC29 NC33 NC34                       ND39                 5C006 AA12 AC24 BB16 BC03 BC06                       BC12 BC16 BF01 BF04 BF14                       BF34 FA47                 5C080 AA10 BB05 DD26 EE29 FF11                       GG12 JJ02 JJ04

Claims (8)

[Claims] 1. A plurality of display pixels constituting a display screen,
A drive circuit that divides display data of a plurality of bits into at least two partial display data having the same number of bits for each of the plurality of display pixels and sequentially outputs the divided display data, and sequentially outputs from each of the drive circuits to a corresponding display pixel. And a plurality of data holding means for driving corresponding display pixels by holding partial display data in different memory blocks respectively,
The drive circuit is configured to compare the contents of the at least two partial display data, and when the contents match, to output only one of the partial display data and hold it in each memory block in common. A flat display device characterized by the above. 2. The flat panel display device according to claim 1, wherein the display data is equally divided into upper and lower partial display data and sequentially output from the drive circuit. 3. The driving circuit fetches one of the upper partial display data and the lower partial display data into the first and second memory blocks in the first data output period and receives the other of the upper partial display data and the lower partial display data. 3. The flat panel display device according to claim 2, wherein the data holding unit is controlled so as to be loaded into the second memory block during a subsequent data output period. 4. The flat panel display device according to claim 1, wherein at least the data holding means is composed of a low temperature polysilicon semiconductor element. 5. The flat panel display device according to claim 1, wherein each of the memory blocks includes a 1-bit memory equal to the number of bits of corresponding display data. 6. The display pixel is provided with a sub-pixel electrode corresponding to the 1-bit memory.
The flat panel display device according to. 7. The flat display device according to claim 5, wherein each of the sub-pixel electrodes is set to have an area ratio corresponding to a weight of data held in the corresponding 1-bit memory. . 8. The flat display according to claim 1, wherein the driving circuit is electrically connected to each display pixel via a signal bus having a line number corresponding to the bit number of the partial display data. apparatus.