JP2003163815A - Sawtooth wave oscillation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sawtooth wave oscillation circuit provided with a function of revising a kind of a packet used depending on a reception state of data. <P>SOLUTION: The sawtooth wave oscillation circuit is provided with: a waveform generating circuit that generates a vertical deflection purpose sawtooth wave; an automatic gain control circuit that converges the amplitude of the sawtooth wave to a target value; an oscillation current generating circuit; an amplitude compensation circuit that compensates the amplitude of the sawtooth wave; a constant current that detects a period from the generation of an own reset pulse to input of a vertical synchronizing signal and forcibly charges/discharges an automatic gain controlling capacitor from the generation of the own reset pulse to the input of the vertical synchronizing signal within one vertical synchronizing signal; and an own reset detection circuit that shuts off a sampling pulse output to activate the amplitude compensation circuit of the sawtooth wave oscillation circuit from the generation of the own reset pulse to the input of the vertical synchronizing signal. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sawtooth wave oscillating circuit, and more particularly to a sawtooth wave oscillating circuit having a function of changing the type of packet to be used according to a data reception state.

[0002]

2. Description of the Related Art In recent years, a sawtooth wave oscillation circuit with a self-reset function is used particularly in a display device for a personal computer and is generally capable of synchronizing with a wide range of vertical synchronizing signal frequencies. It is well known to collect.

Such a conventional sawtooth wave oscillation circuit is
For example, it is disclosed in Japanese Unexamined Patent Publication No. 2001-157075 (cited document).

The saw-tooth wave oscillating circuit according to the prior art can control the display area of the display from the personal computer side. Changing the display area of the display changes the frequency of the horizontal / vertical synchronizing signal. is doing.

The vertical sawtooth wave amplitude performs vertical scanning, and the vertical sawtooth wave amplitude determines the screen size in the vertical direction.
When the vertical synchronizing signal frequency is changed, the vertical sawtooth wave amplitude changes, and the feedback loop operates so that the amplitude converges to the target value. Therefore, the display device generally displays the screen when the vertical synchronizing signal frequency is changed. The display is turned off to make the vertical screen size fluctuation invisible. Therefore, in order to improve the performance of the display device, it is desired to shorten the convergence response time of the vertical sawtooth wave amplitude when the vertical synchronizing signal frequency changes.

Further, the shortening of the convergence response time of the vertical sawtooth wave amplitude when the vertical synchronizing signal frequency changes can be realized by the sawtooth wave oscillation circuit described in the above-mentioned reference (Japanese Patent Laid-Open No. 2001-157075). However, it is apparent that the sawtooth wave oscillating circuit cannot generate the sawtooth wave without the vertical synchronizing signal.

Therefore, the sawtooth wave level rises to the circuit saturation level during the non-synchronization signal period at the time of signal switching, which may cause high stress to the deflecting device of the display and damage. To prevent this, give a pseudo vertical sync signal from the microcomputer during the no sync signal period.
It may be possible to always generate a sawtooth wave or to use a high withstand voltage component that causes no problem even if a high stress is applied to the deflection device.

However, the method of giving a pseudo vertical synchronizing signal from the microcomputer puts a burden on the microcomputer and the cost of using a high withstand voltage component increases. Therefore, a sawtooth wave can be generated in hardware even in the non-synchronizing signal period. Is desired.

FIG. 9 shows the above cited document (Japanese Patent Laid-Open No. 2001-2001).
FIG. 1 is an improved configuration diagram in which a self-reset function is added to the sawtooth wave oscillation circuit (circuit within dotted line) described in Japanese Patent No. 157075). First, the above cited document (Japanese Patent Laid-Open No. 2001-157).
No. 075), the operation of the sawtooth wave oscillation circuit described in FIG.
0, FIG. 11 (a), FIG. 11 (b), and FIG. 11 (c), respectively.

First, the operation of generating a sawtooth wave for vertical deflection by the waveform generating circuit 1A will be described. When the vertical synchronizing signal VSYNC is constantly input to the input terminal IN, the leading edge of the vertical synchronizing signal VSYNC rises. (Time t1)
At this time, the one-shot circuit 17 is triggered, the flip-flop 16 is set at the trailing edge (time t2) of the sampling pulse signal TS, and the flip-flop 16 is set.
Switch 13 is turned on by the output of the current source 12
Discharge of the capacitor 11 is started by the voltage VSAW
1 decreases, and when the voltage VSAW1 becomes equal to or lower than the set lower limit voltage VLOW at time t4, the flip-flop 16 is reset by the comparison result output of the comparator 15, and the switch 13 is off-controlled by the output of the flip-flop 16. The discharge of the capacitor 11 stops. Capacitor 1
Since the oscillating current generating circuit 3A constantly supplies the oscillating current IC1 to 1, the charging starts again when the discharging is stopped, the voltage VSAW1 rises, and the trailing edge of the next sampling pulse signal TS falls (time t7). ), The flip-flop 16 is set again, the switch 13 is turned on again by the output of the flip-flop 16, and the current source 1
2 starts discharging the capacitor 11 again, and the voltage V
SAW1 descends again. The above operation is repeated, and the vertical synchronization signal VSYNC is generated every cycle of the vertical synchronization signal VSYNC.
A sawtooth wave is generated at the output terminal OUT in synchronization with C.

Next, the operation of converging the amplitude value of the sawtooth wave to the target value by the automatic gain control circuit 2A and the oscillation current generating circuit 3A will be described. The voltage VSAW1 is the midpoint voltage VCEN
During the period from time t3 to time t5, which is less than T, the comparator 21 outputs the current of the current source 23, so that the AGC current IA1 becomes the value + a, and the capacitor 31 is charged. Time t5 when the voltage VSAW1 is equal to or higher than the midpoint voltage VCENT
During a period from to the time t8, the comparator 21 outputs the current of the current source 24, so that the AGC current IA1 becomes the value -a and the capacitor 31 is discharged. The voltage between the terminals of the capacitor 31 is level-shifted by the base-emitter terminal voltage of the NPN transistor 72, the potential difference across the resistor 71 becomes the AGC voltage, and the current flowing through the resistor 71 and the constant current 7
The sum of 5 is folded back by the current mirror circuit composed of PNP transistors 73 and 74, and becomes the oscillation current IC1 which is given to the capacitor 11. In this way, the vertical synchronization signal VS
For the entire period of the YNC cycle, that is, the sawtooth wave cycle,
Since the voltage VSAW1 is compared with the midpoint voltage VCENT by the comparator 21 and the feedback operation is performed so that the charging period and the discharging period of the capacitor 31 become equal, the AGC voltage VA1 becomes almost constant and the amplitude of the sawtooth wave becomes constant. Become. The amplitude value of the sawtooth wave is set to 2 * (VCENT-VLOW).

Next, the operation of the amplitude compensation circuit 4A will be described. As shown in FIG. 11A, when the vertical synchronizing signal VSYNC does not change in the steady state and the voltage VTOP1 is larger than the set voltage V1 and smaller than the set voltage V2, the comparators 51 and 61 always perform comparison. However, the switch 41 is closed only during the pulse width period (time t2-time t1) of the sampling pulse signal TS, and the switch 5 is closed during this pulse width period.
Since both 2 and 62 are off, the compensation signal current IB
1 becomes 0, which has no effect on the oscillation current generating circuit 3A. Further, as shown in FIG. 11B, the vertical synchronizing signal VSYNC frequency changes to a high level and the slope of the sawtooth waveform does not change immediately. Therefore, when the voltage VTOP1 becomes equal to or lower than the set voltage V1, the switch 52 is turned on and the switch 41 is closed only during the pulse width period (time t2 to time t1) of the sampling pulse signal TS, so that the compensation signal current IB1 output by the quick charging circuit 5A has a current value at the same timing as the sampling pulse signal TS. It becomes the pulse current of b, the capacitor 31 is rapidly charged, and the AGC
Since the voltage VA1 is increased, the oscillation current IC1 is increased and the waveform slope of the sawtooth wave is also increased. And VTO
When P1 exceeds the set voltage V1, the compensation signal current becomes 0, and thereafter, the amplitude converges to the target value by the normal feedback loop by the automatic gain control circuit 2A. In addition, FIG.
As shown in (c), when the vertical sync signal VSYNC frequency changes to a low level and the voltage VTOP1 becomes equal to or higher than the set voltage V2, the switch 62 is turned on and the pulse width period of the sampling pulse signal TS (time t2 -Time t
Only in 1) the switch 41 is closed, so the rapid discharge circuit 6A
The compensating signal current IB1 output by the pulse current becomes a pulse current having a current value -b at the same timing as the sampling pulse signal TS, rapidly discharges the capacitor 31, and lowers the AGC voltage VA1. Therefore, the oscillation current IC1 decreases and the sawtooth wave The slope of the waveform also decreases. Then, when VTOP1 becomes less than the set voltage V2, the compensation signal current becomes 0, and thereafter, the amplitude converges to the target value by the normal feedback loop by the automatic gain control circuit 2A.

As described above, the cited document (Japanese Patent Laid-Open No. 20
No. 01-157075), the sawtooth wave oscillation circuit has an effect of shortening the amplitude convergence response time when the frequency of the vertical synchronizing signal changes, while it causes VSA when the vertical synchronizing signal becomes no signal.
Since the W1 level rises to the circuit saturation level and the sawtooth wave cannot be generated, the self reset circuit 8A is added. Next, the operation of the self-reset circuit 8A will be described. When the vertical synchronizing signal VSYNC is present, VSAW1 operates as shown in FIG. 10, and the maximum peak voltage of VSAW1 is 2 * (VCENT-
VLOW) + VLOW. By setting the voltage VHIGH connected to the inverting input terminal of the comparator 81 higher than the maximum peak voltage of VSAW1, the output of the comparator 81 is always at the LOW level, and the OR circuit 82 always outputs the vertical synchronization signal VSYNC. To do. Vertical sync signal VSYN
When there is no C, the one-shot circuit 1 of the waveform generation circuit 1A
Since the trigger signal of 7 disappears, the VSAW1 voltage rises above the maximum peak value, and when it exceeds the voltage VHIGH connected to the inverting input terminal of the comparator 81, the comparator 81
Output becomes HIGH level, and the output of the OR circuit 82 also becomes HIGH level.
The trigger signal of the one-shot circuit 17 of A is given,
A sawtooth wave can be obtained without the vertical synchronization signal VSYNC.

Next, a specific operation of the sawtooth wave oscillating circuit with the self-reset function of FIG. 9 will be described. When the vertical synchronizing signal frequency fvsync is input, the AGC voltage VA1 and the oscillation current IC1 provided from the resistor 71 and the capacitor 11
The sawtooth amplitude is given by, and the amplitude value of the sawtooth amplitude is 2
Since it converges to * (VCENT-VLOW) by the feedback loop, the relationship between the vertical synchronizing signal frequency fvsync and the AGC voltage VA1 can be expressed as Expression 5-1. Here, the discharge time of the capacitor 11 is short and is ignored. fvsync = (VA1 + R71 * I75) / (2 * (VCENT-VLOW) * C11 * R71) Equation 5-1 That is, when the vertical synchronizing signal frequency changes, the AGC voltage VA1 changes and the sawtooth wave amplitude becomes constant. I try to keep it. VLOW = 2.0V, VCENT = 3.5V,
C11 = 0.068μF, R71 = 245K, I75 =
Assuming 5 μA, the vertical synchronizing signal frequency fvsync = 1
The AGC voltage VA1 (100 Hz) at 00 Hz is 3.7.
73 V, and vertical sync signal frequency fvsync = 50
AGC voltage VA1 (50Hz) at Hz is 1.274V
Must be

Next, when the vertical synchronizing signal frequency is high (10
The operation when changing from 0 Hz) to a low state (50 Hz) will be described with reference to FIG. Vertical sync signal is time t
At 1, 100 Hz is input and the sawtooth wave amplitude is in a stable state. From this state, the vertical synchronization signal is 50 at time t3.
When the frequency is switched to Hz, the vertical synchronization signal becomes a non-synchronization signal state between the time t1 and the time t3, and the sawtooth wave generation circuit operates the self-reset circuit 8A to generate the sawtooth wave amplitude. The oscillation period Tfree of the sawtooth wave at time t2 is
If the pulse width of the sampling pulse TS is TW, equation 5
It can be represented as -2. Tfree = (VHIGH-VLOW) * C11 * R71 / (VA1 (100Hz) + I75 * R71) + TW (Equation 5-2) The automatic gain control circuit 2A operates during the period from time t1 to time t2, and the capacitor 31 The charging time TC and the discharging time TD can be expressed by Expression 5-3 and Expression 5-4. TC = (VCENT-VLOW) * C11 * R71 / (VA1 (100Hz) + I75 * R71) Formula 5-3 TD = (VHIGH-VCENT) * C11 * R71 / (VA1 (100Hz) + I75 * R71) + TW ... Formula 5-4 Further, when the sampling pulse is generated, the amplitude compensating circuit 4A also acts, and the sawtooth wave level becomes higher than V2 during this period. Therefore, the capacitor 31 is driven by the constant current 63 from the rapid discharge circuit 6A only during the TW period. To discharge. As a result, the period from time t1 to time t2 (one cycle period of sawtooth wave generation)
The amount of change in AGC voltage DVA5_1 is expressed by equations 5-3 and 5-5, where a is the charge / discharge current from the automatic gain control circuit 2A and b is the constant current 63 of the rapid discharge circuit 6A.
Can be expressed as DVA5_1 = {a * (TC-TD) -b * TW} / C31 = [{a * {(2 * VCENT-VLOW-VHIGH) * C11 * R71 / (VA1 (100Hz) + I75 * R71) -TW}- b * TW] / C31 Formula 5-5 VHIGH = 5.5V, a = 200 μA, b = 20 m
If A, TW = 50 μSEC, and C31 = 33 μF,
DVA5_1 = -40.7 mV, and the AGC voltage VA1 is discharged during the non-synchronous signal period from time t1 to time t3.

Now, when the period of the first sawtooth wave in the non-synchronous signal period from time t1 to time t3 is calculated from the equation 5-2, it is 1
1.717 mSEC and the non-synchronization signal period Ta is 10
If 0 mSEC is set, the cycle of the sawtooth wave generated in this period becomes 100 mSEC / 11.717 mSEC 8 cycles, and from the result of Equation 5-5, the AGC voltage VA in this period is obtained.
The change amount of 1 is -40.7 mV * 8 = -0.326 V, and the AGC voltage VA1 (t3) at time t3 is VA1 (t3) = VA (100 Hz) -0.326 =
It is 3.447V, and the AGC voltage VA1 (50Hz) obtained previously is =
It is higher than 1.274V, and the oscillation current at this time is 5
Since it is higher than the oscillation current at 0 Hz, the self-reset circuit 8A operates at the time t4 and the sampling pulse T
Since S occurs, the sawtooth wave falls, and at time t5, the vertical synchronizing signal is input, and the sampling pulse TS is generated, so that the sawtooth wave falls. That is, time t3
2 sawtooth waves are generated within one vertical synchronizing signal period from time t5 to time t5. Since the AGC voltage VA1 (t3) = 3.447V at the time t3, the time t3
From the formula 5-2, the time from time t4 to time t4 is t4-t3 = (VHIGH-VLOW) * C11 * R7.
1 / (3.447 + I75 * R71) + TW = 12.5
3 msec is obtained, the sawtooth wave rises from VLOW to VHIGH within a period of t4−t3−TW = 12.48 msec, and the time difference between time t4 and time t5 is 20 mesc−.
Since 12.53 msec = 7.47 msec, the sawtooth wave level Vx at time t5 is Vx = (VHIGH-VLOW) * (7.47 msec.
/12.48 msec) + VLOW = 4.095V, which is larger than the VCENT voltage (3.5V).
From this, the charging time TC and the discharging time TD of the capacitor 31 in the operation of the automatic gain control circuit 2A from the time t3 to the time t5 can be expressed by Expressions 5-6 and 7. TC = 2 * (VCENT-VLOW) * C11 * R71 / (VA1 (t3) + I 75 * R71) Equation 5-6 TD = {(VHIGH-VCENT) + (Vx-VCENT)} * C11 * R7 1 / (VA1 (t3) + I75 * R71) + TW (Equation 5-7) Further, when the sampling pulse is generated, the amplitude compensating circuit 4A also acts, and the sawtooth wave level at time t4 becomes higher than V2. Circuit 6A constant current 6
The capacitor 31 is discharged at 3 and the sawtooth wave level becomes lower than V1 at time t5. Therefore, the capacitor 31 is discharged by the constant current 53 of the quick charging circuit 5A only during the TW period. The constant current 53 of the quick charging circuit 5A is set to c
Then, the AGC voltage change amount DVA5_2 within one vertical synchronization signal period from the time t3 to the time t5 is given by the formula 5-
6, can be expressed as Equation 5-7 to Equation 5-8. DVA5_2 = a * (TC-TD) / C31 + (c-b) * TW / C31 = a * [{2 * (VCENT-VLOW)-(VHIGH-VCENT)-(Vx-VCENT)} * C11 * R71 / (VA1 (t3) + I75 * R71) − TW] / C31 + (c−b) * TW / C31 Equation 5-8 Now, the constant current 53 of the rapid charging circuit 5A and the rapid discharging circuit 6A.
Assuming that the constant currents 63 are equal (c = b), the equation 5-8 is DVA5_2 (c = b) = a * [{2 * (VCENT-VLOW)-(VHIGH-VCENT)-(Vx-VCENT). } * C11 * R71 / (VA1 (t3) + I75 * R71) -TW] / C31, and the value of DVA5_2 (c = b) changes depending on the value of Vx, and the maximum value is when Vx = VCENT. Is. DVA5_2 (c = b, Vx = VCENT) = a * [{2 * (VCENT-VLOW)-(VHIGH-VCENT)} * C11 * R71 / (VA1 (t3) + I75 * R71) -TW] / C31 = + 21.3 mV At time t3, the AGC voltage is VA1 (t3) = 3.
It is 447V, and the AGC voltage has to be lowered in order to shift to the required AGC voltage VA1 (50Hz) = 1.274V at the vertical synchronizing signal 50Hz, but the above result should be increased to + 21.3mV. Since it operates as described above, an abnormal state occurs in which two sawtooth waves are generated within one vertical synchronization signal period. In order to avoid this, (c−b) * TW / C31 <−21.3 mV → c−
b <-14.06 mA It is necessary to satisfy the above conditions.

If b = 20 mA is set, c <
The condition of 5.94 mA is required. Here, when the current value c of the constant current 53 of the quick charging circuit 5A is 0 mA and 5 mA, the AGC voltage change amount DVA5_2 within one vertical synchronizing signal period from the time t3 to the time t5 is calculated from the equation 5-8 to a. ) When b = 20 mA and c = 0 mA DVA5_2 = -2
1.9 mV b) b = 20 mA, c = 5 mA DVA5_2 = -1
It becomes 4.3 mV, and the current value c of the constant current 53 is the current value b of the constant current 63.
On the other hand, when the vertical sync signal frequency is 50 Hz, the amount of change in the AGC voltage in one vertical sync signal period is large, and the time required to converge the sawtooth wave amplitude is shortened. FIG. 13 shows a tracking waveform of the AGC voltage when the vertical synchronizing signal frequency changes from 100 Hz to 50 Hz.

Next, when the vertical synchronizing signal frequency is low (50
The operation when the frequency shifts from (Hz) to a high state (100 Hz) will be described. Even when the vertical synchronizing signal is switched from 50 Hz to 100 Hz, the no-signal state is generated, and the self-resetting circuit 8A of the sawtooth wave generating circuit operates to generate the sawtooth wave amplitude. The oscillation period Tfree of the sawtooth wave at this time is expressed by Equation 5-
2 is replaced with VA1 (100 Hz) by VA1 (50 Hz). The automatic gain control circuit 2A operates even in this sawtooth wave state, and further, there is an action from the amplitude compensation circuit 4A due to the generation of the sampling pulse, and the variation amount DVA5_3 of the AGC voltage during one cycle period of the sawtooth wave generation is also expressed by the formula 5 is replaced with VA1 (100 Hz) by VA1 (50 Hz). DVA5_3 = [{a * {(2 * VCENT-VLOW-VHIGH) * C11 * R71 / (VA1 (50Hz) + I75 * R71) -TW} -b * TW] / C31 ... Formula 5-9 Same value as above Is used, DVA5_3 = -50.8 mV
Then, the AGC voltage VA1 is discharged in the non-synchronization signal period.

When the period of the first sawtooth wave in the non-synchronous signal period is calculated from the equation 5-2, it is 23.38 mSEC, and when the non-synchronous signal period Ta is 100 mSEC, the sawtooth wave generated in this period. Cycle is 100mSEC / 2
At 3.38 mSEC, there are almost 4 cycles, and the change amount of the AGC voltage VA1 within the non-synchronous signal period is −50.8 mV * 4.
= -0.203V.

From now on, the AGC voltage when the vertical synchronizing signal of 100 Hz is input is VA1 (50 Hz) -0.20.
3V = 1.071V, which is lower than the AGC voltage VA1 (100) = 3.773V in the stable state of the sawtooth wave amplitude when the vertical synchronization signal 100Hz is input, which is obtained earlier, and the oscillation current at this time is 100Hz. Lower than the oscillation current of
Unlike the period from time t3 to time t5 in FIG. 12, two sawtooth waves do not occur within one vertical synchronization signal period.
The amplitude VSAWAMP5_1 of the sawtooth wave at this time is VSAWAMP5_1 = (VA1 + R71 * I75) / (fvsync * C11 * R71) = 1.378Vpp obtained from the above-mentioned formula 5-1 and the maximum peak voltage of the sawtooth wave is VSAWAMP1 +
VLOW = 3.378V.

The maximum peak voltage of the sawtooth wave is VCENT =
Since the voltage is 3.5 V or less, only the charging operation is performed from the automatic gain control circuit 2A to the capacitor 31, and the vertical synchronizing signal is further input, so that a sampling pulse is generated, and the action from the amplitude compensating circuit 4A is generated. The charging operation is performed from the quick charging circuit 5A to the capacitor 31.

As a result, the amount of change DVA5_4 of the AGC voltage in one vertical synchronizing signal at the time of inputting the vertical synchronizing signal can be expressed by equation 5-10. DVA5_4 = {a * (1 / fvsync) + C * TW} / C31 Formula 5-10 In other words, the change amount of the AGC voltage in one vertical synchronizing signal at this time depends on the current value c of the constant current 53. Shows. Due to this change in the AGC voltage, the sawtooth wave amplitude value gradually converges to the target value.

[0023]

However, this conventional technique has the following problems.

That is, the operation when the vertical synchronizing signal frequency changes from the high state to the low state is described. Finally, "If the current value c of the constant current 53 is smaller than the current value b of the constant current 63, one vertical synchronization is performed. The AGC voltage change amount during the signal period becomes large, and the time for the sawtooth wave amplitude convergence at the vertical synchronizing signal frequency of 50 Hz is shortened. "
As is clear from FIG. 10, when the vertical synchronizing signal frequency changes from the low state to the high state, if the current value c of the constant current 53 is small, the AGC voltage change amount within one vertical synchronizing signal period becomes small, and the sawtooth wave amplitude converges. The time to go will not be shortened.

In FIG. 14, the vertical synchronizing signal frequency is 50 Hz.
2 shows a tracking waveform of the AGC voltage when changing from 100 Hz to 100 Hz. In other words, in the conventional sawtooth wave oscillator circuit with the self-reset function, when the sawtooth wave amplitude convergence time is shortened when the vertical synchronizing frequency changes from the low state to the high state, the vertical synchronizing frequency changes from the high state to the low state. When the vertical sync frequency is changed from high to low, conversely, when the sawtooth amplitude convergence time is increased when the vertical sync frequency is changed from high to low, the vertical sync frequency is changed from low to high. There was a problem when it could not be speeded up.

Further, when the vertical synchronizing signal frequency changes from a low state to a high state, from the result of equation 5-9, the AGC voltage is excessively lowered due to the influence of the amplitude compensating circuit 4A in the non-synchronizing signal period. Therefore, there is also a problem that delays the sawtooth wave amplitude convergence time.

Therefore, an object of the present invention is to provide a sawtooth wave oscillation circuit which solves the above problems.

That is, according to the present invention, the sawtooth wave oscillation circuit described in the above-mentioned reference (Japanese Patent Laid-Open No. 2001-157075) is provided with a self-reset function, and the output of the amplitude compensation circuit in the sawtooth wave oscillation circuit is set. The purpose is to provide a self-reset detection circuit in the controlled part to shorten the time to converge the sawtooth wave amplitude.

[0029]

SUMMARY OF THE INVENTION A sawtooth wave oscillating circuit according to the present invention is a waveform generating circuit for generating a sawtooth wave for vertical deflection in the period from the generation of a self-reset pulse to the input of a vertical synchronizing signal, and the waveform generating circuit. And an oscillation current generating circuit that generates an oscillation waveform corresponding to the sawtooth wave, and an automatic gain control circuit that receives the output of the waveform generating circuit and converges the amplitude value of the sawtooth wave to a target value. An amplitude compensating circuit for compensating the amplitude value of the sawtooth wave; and a period from the self-reset pulse generation to the vertical sync signal input in the period from the self-reset pulse generation to the vertical sync signal input. And a self-reset detection circuit for interrupting the sampling pulse output that operates the amplitude compensation circuit.

Further, in the sawtooth wave oscillation circuit of the present invention, the self-reset detection circuit detects a period from the generation of the self-reset pulse to the input of the vertical sync signal, and the self-reset pulse within one vertical sync signal. In the configuration from the generation to the input of the vertical synchronizing signal, a constant current source for forcibly charging / discharging the automatic gain control capacitor of the oscillation current generating circuit is provided.

Further, in the self-reset detecting circuit of the sawtooth wave oscillating circuit of the present invention, the data terminal is always input high, the vertical synchronizing signal is input to the clock terminal, and the vertical synchronizing signal is input to the data terminal at the falling edge. Holding the data, the output of the self-reset circuit is connected to the reset terminal, and the first reset D flip-flop is reset when the self-reset pulse is high, and the inversion of the first reset D flip-flop. An output of the first flip-flop with reset and a D flip-flop for inputting the output to the data terminal, the vertical synchronizing signal being input to the clock terminal, and holding the data input to the data terminal at the rising edge of the vertical synchronizing signal. And the sampling pulse signal output from the inverted output of the D flip-flop and the waveform generation circuit. And an input signal, and a logical product circuit for controlling the switch of the amplitude compensation circuit by the output signal, the inverted output of the first D flip-flop with reset and the output of the D flip-flop are input, and the output signal It is configured to include a logical product circuit for controlling the switch and a constant current for discharging the electric charge of the capacitor by controlling the switch.

Furthermore, the self-reset detection circuit of the sawtooth wave oscillation circuit of the present invention detects the period from the self-reset pulse generation to the input of the vertical synchronizing signal in the SR latch circuit and the D flip-flop. It is configured to include an inverter that prevents data acquisition error at the rise of the vertical synchronization signal.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail below with reference to the drawings.

The present invention is based on the above-cited document (Japanese Patent Laid-Open No. 2001-2001).
-157075), the self-reset detection circuit is provided in the portion of the sawtooth wave oscillator circuit that controls the output of the amplitude compensation circuit in the sawtooth wave oscillator circuit having the self-reset function. There is.

FIG. 1 shows a sawtooth wave oscillation circuit with a self-reset function according to the present invention. The self-reset detection circuit detects a period from the generation of a self-reset pulse to the input of a vertical synchronizing signal, and this period is an amplitude compensation circuit. The sampling pulse output that acts on is cut off. Further, in the period having the vertical synchronizing signal, the switch 95 is closed to forcibly discharge the automatic gain control capacitor 31 in the period from the generation of the self-reset pulse to the input of the vertical synchronizing signal, and in the period having no vertical synchronizing signal, During the period from the generation of the self-reset pulse to the input of the vertical synchronizing signal, the switch 95 is opened and the automatic gain control capacitor 31 is forcibly discharged.

As a result, during the non-synchronization signal period that occurs when the vertical synchronization signal frequency is switched, the sawtooth wave is generated while the self-reset pulse is generated. Therefore, from the self-reset pulse generation to the vertical synchronization signal input. During the period, the effect on the automatic gain control capacitor 31 is only the automatic gain control circuit 2A, and the decrease in the voltage VA1 can be reduced. When the vertical synchronizing signal frequency changes from a low state to a high state, the potential of the automatic gain control capacitor 31 has to transition from a low potential to a high potential, so that the automatic gain control capacitor 31 has a potential within the non-synchronization signal period. Capacitor 31 for automatic gain control in which the sawtooth wave becomes stable by suppressing the decrease in potential
The follow-up to the potential of can be speeded up. Also, when the vertical synchronizing signal frequency changes from a high state to a low state, a self-reset pulse is generated within one vertical synchronizing signal period.
During the period from the generation of the self-reset pulse to the input of the vertical synchronizing signal, the switch 95 is closed to forcibly discharge the automatic gain control capacitor 31 and the voltage VA1 can be rapidly lowered. When the vertical synchronizing signal frequency shifts from a high state to a low state, the potential of the automatic gain control capacitor 31 has to shift from a high potential to a low potential, so that the potential of the automatic gain control capacitor 31 is rapidly lowered. As a result, it is possible to speed up the follow-up to the potential of the automatic gain control capacitor 31 in which the sawtooth wave becomes stable. Further, in a situation where the self-reset pulse is not generated, the self-reset pulse detection circuit does not operate, and therefore, the reference document (Japanese Patent Laid-Open No. 2001-157
The operation of the sawtooth wave oscillating circuit of Japanese Laid-Open Patent Publication No. 075) is not disturbed.

Therefore, the sawtooth wave oscillating circuit with the self-reset function of the present invention has the effect of increasing the follow-up speed until the sawtooth wave changes to a stable state when the vertical synchronizing signal frequency changes. FIG. 1 shows a sawtooth wave oscillation circuit with a self-reset function of the sawtooth wave oscillation circuit.

The waveform generation circuit 1A, the automatic gain control circuit 2A, the oscillation current generation circuit 3A and the self-reset circuit 8 in FIG.
A and the amplitude compensation circuit 4A are the same as those described in the conventional example, and since they are not directly related to the present invention, their detailed configuration will be omitted. The present invention is characterized in that the self-reset detection circuit 9A is provided, and its configuration will be described.

In the self-reset detection circuit 9A of the sawtooth wave oscillation circuit according to the first embodiment of the present invention, the data terminal is always h.
The vertical synchronizing signal is input to the clock terminal, the data input to the data terminal is held at the falling edge of the vertical synchronizing signal, and the self reset circuit 8 is input to the reset terminal.
D flip-flop with reset 91 connected to the output of A and reset when the self-reset pulse is high
And a D flip-flop 92 for inputting the inverted output of the D flip-flop with reset 91 to the data terminal, inputting the vertical synchronizing signal to the clock terminal, and holding the data input to the data terminal at the rising edge of the vertical synchronizing signal. ,
The output of the D flip-flop 91 with reset and the D
An AND circuit 93 that receives the inverted output of the flip-flop 92 and the sampling pulse signal TS output from the waveform generating circuit 1A as input and controls the switch 41 of the amplitude compensation circuit 4A by the output signal, and the D flip-flop with reset The inverted output of 91 and the output of the D flip-flop 92 are input, and an AND circuit 94 for controlling the switch 95 by the output signal and a constant current 96 for discharging the electric charge of the capacitor 31 by the control of the switch 95 are provided. To do.

In the D flip-flop with reset 91, the output is always h when the self-reset pulse is not generated.
When the self-reset pulse is generated, the output during the falling period of the vertical sync signal from the occurrence of the self-reset pulse becomes the low output, and it is possible to detect the falling period of the vertical sync signal from the occurrence of the self-reset pulse. You can do it. D flip-flop 92
In order to latch the inverted output of the D flip-flop with reset 91 at the rising edge of the vertical synchronization signal, the vertical synchronization signal is input, and the self-reset pulse is generated in the D flip-flop with reset 91 and the vertical synchronization signal rises. When the falling period is detected, the D flip-flop 92 takes a high output and can detect a period having a self-reset pulse in one vertical synchronizing signal. as a result,
The output of the AND circuit 93 is always a low output when the self-reset pulse is generated, and the switch 4 of the amplitude compensation circuit 4A
1 is opened, the action of the amplitude compensation circuit 4A is not applied to the capacitor 31, and when the self-reset pulse is not generated, the sampling pulse signal TS output from the waveform generation circuit 1A is output and the switch 41 of the amplitude compensation circuit 4A is sampled. Amplitude compensation circuit 4A closed at the timing of pulse TS
To the capacitor 31. Further, the AND circuit 9
The output of No. 4 becomes high during the falling period of the vertical synchronizing signal from the occurrence of the self-resetting pulse in the period in which one vertical synchronizing signal has the self-resetting pulse, and the switch 9
5 is closed, the capacitor 31 is discharged with the constant current 96, the output of the AND circuit 94 becomes low at other timings, the switch 95 is opened, and the capacitor 3
Does not affect 1.

Next, the operation of the sawtooth wave oscillation circuit according to the first embodiment of the present invention will be described.

The operation of the sawtooth wave oscillation circuit with self-reset function shown in FIG. 1 when the vertical synchronizing signal is applied and the sawtooth wave amplitude is in a stable state is as described in the conventional example. Since it is not directly related, detailed description of its operation is omitted.

In the sawtooth wave generator with self-reset of the present invention shown in FIG. 1, the vertical synchronizing frequency is high (100H).
The operation at the time of transition from z) to the low state (50 Hz) will be described in detail with reference to FIG.

The vertical synchronizing signal is 100H at time t1.
z is input and the sawtooth wave amplitude is in a stable state.

From this state, the vertical synchronizing signal becomes 5 at time t5.
When the frequency is switched to 0 Hz, the vertical synchronizing signal is in the no signal state (t00) between time t1 and time t5, and the sawtooth wave generation circuit operates the self-reset circuit 8A to generate the sawtooth wave amplitude.

At time t2, the voltage VSAW1 level exceeds VHIGH, so that the self-reset circuit 8A becomes H level.
IGH output, D flip-flop 91 with reset
Are reset and the output becomes LOW level.

The output of the D flip-flop with reset 91 outputs a LOW level until the time t6 when the falling edge of the vertical synchronizing signal is input, and the sampling pulse TS is generated by the generation of the reset pulse. Since the sampling pulse TS and the output of the reset D flip-flop 91 are ANDed, the output (point C) of the AND circuit 93 is L during the period from time t2 to time t6.
It becomes OW level and the switch 41 is not controlled.

That is, in the period from time t2 to time t6, the amplitude compensating circuit 4A does not act on the capacitor 31. As a result, the action on the capacitor 31 in one cycle of the sawtooth wave from the time t1 to the time t2 is only from the automatic gain control circuit 2A, and the charging time T to the capacitor 31 is T.
C and the discharge time TD are given by the equations 5-3 and 4 shown in the conventional example. AG of one cycle of sawtooth wave from time t1 to time t2
The change amount DVA3_1 of the C voltage VA1 can be expressed as Expression 3-1. DVA3_1 = a * (TC-TD) / C31 = a * {2 * VCENT-VLOW-VHIGH) * C11 * R71 / (VA1 (100 Hz) + I75 * R71) -TW} / C31 ... Formula 3-1 The constant is To quote the same example as the conventional example, DVA3_1
= -10.4 mV, which is a conventional example (DVA5_1 = -4).
It can be seen that it is smaller than 0.7 mV).

As a result, after the time t5, two sawtooth waves are generated within one vertical sync signal period from the time t5 to the time t10 after the vertical sync signal is input, as in the conventional example. Is. As in the conventional example, the non-synchronous signal period T
If a is 100 mSEC, the cycle of the sawtooth wave generated within this period is 8 cycles as in the conventional case, and A at time t5
The GC voltage VA1 (t5) is VA1 (t5) = VA1 (100HZ) -10.4 mV
* 8 = 3.690V, and the time from time t5 to time t8 is t8-t5 = (VHIGH-VLOW) * C11 * R7 from the equation 5-2.
1 / (3.690 + I75 * R71) + TW = 11.9
1 msec is obtained, the sawtooth wave rises from VLOW to VHIGH within a period of t8-t5-TW = 11.86 msec, and the time difference between time t10 and time t8 is 20 mesc.
Since −11.91 msec = 8.09 msec, the level Vx of the sawtooth wave at time t10 is Vx = (VHIGH-VLOW) * (8.09 msec
/11.86 msec) + VLOW = 4.387V.

At the timing of time t4, the data terminal (A
Since the reset pulse is detected by the D flip-flop with reset 91 before the time t4,
It is at the H level and further the D flip-flop 92
Since the rising edge of the vertical synchronizing signal is input to the clock terminal of, the output (point B) of this D flip-flop 92 becomes HIGH level. The inverted output of the reset D flip-flop 91 (point A) and the output of the D flip-flop 92 (point B) are input to the AND circuit 94, and the output of the AND circuit 94 (point D) during the period between time t4 and time t6. ) Becomes HIGH level, switch 95 is closed and constant current 9
6, the capacitor 31 is discharged.

At time t7, the voltage VSAW1
When the level exceeds VHIGH, the self-reset circuit 8A becomes HIGH output, so that the output of the D flip-flop with reset 91 becomes LOW level.

The output of the D flip-flop with reset 91 is time t11 when the falling edge of the vertical synchronizing signal is input.
Since the LOW level is output up to, the sampling pulse TS is generated by the generation of the reset pulse at time t7 and the input of the vertical synchronizing signal at time t9, but the output of the AND circuit 93 (point C) becomes the LOW level and the switch 41 is turned on. Do not control.

On the other hand, at time t9, the D flip-flop 92
The rising edge of the vertical sync signal is input to the clock terminal of the D flip-flop 92, since the data terminal at this timing is at the HIGH level.
Continues to output HIGH level, and time t7 and time t
In the period of 11, the output (point D) of the AND circuit 94 is H
IGH level, switch 95 is closed and constant current 96
To discharge the capacitor 31.

As a result, 1 from time t5 to time t10
The action on the capacitor 31 within the vertical synchronizing signal period is the action from the automatic gain control circuit 2A and the constant current 96. The charging time TC and the discharging time TD from the automatic gain control circuit 2A to the capacitor 31 are calculated by the formula 5-shown in the conventional example.
It becomes 6,7. The discharge time TD96 from the constant current 96 is
Assuming that the SYNC width of the vertical synchronization signal is Tsync, equation 3-
It can be expressed as 2. TD96 = (Vx−VLOW) * C11 * R71 / (VA1 (t5) + I75 * R71) + Tsync ... Formula 3-2 The current value of the constant current 96 is d, and from time t5 to time t10.
Voltage VA within one vertical synchronization signal period in
The change amount DVA3_2 of 1 can be expressed as Equation 3-3. DVA3_2 = {a * (TC-TD) -c * TD96} / C31 = [a * [{2 * (VCENT-VLOW)-(VHIGH-VCENT)-(Vx-VCENT)} * C11 * R71 / (VA1) (T3) + I75 * R71) -TW] -d * {(Vx-VLOW) * C11 * R71 / (VA1 (t5) + I75 * R71) + Tsync}] / C31 ... Formula 3-3 Here, Tsync = 100 microseconds. , D = 500 μA
And Vx = 4.387V obtained earlier, VA1 (t5)
= 3.690V, DAV3_2 = -0.122V.

In this way, the AGC voltage can be lowered for each vertical synchronizing signal, and the vertical synchronizing signal 50H
z required AGC voltage VA1 (50 Hz) = 1.
It shows that the voltage can be changed to 274V.

Further, as is clear from the expression 3-3, since the amplitude compensation circuit does not work, at the current value c of the constant current 53 of the quick charging circuit 5A and the current value b of the constant current 63 of the rapid discharging circuit 6A. There is no necessary operating condition as in the conventional example.

During the period between time t10 and time t13, the sawtooth wave oscillating current IC1 also decreases due to the decrease in the AGC voltage VA1, and VSAW is generated within one vertical synchronizing signal period.
The 1 level does not exceed VHIGH and the self-reset pulse does not occur. Therefore, at time t12, the output of the D flip-flop with reset 91 is a HIGH level output, and the inverted output of the D flip-flop 92 is also HIGH.
Change to H level output.

As a result, the output (C
Point) outputs a sampling pulse. The inverted output (point A) of the D flip-flop 91 with reset is LOW.
This is a level output, and the output of the D flip-flop 92 (B
Point) also changes to the LOW level output, the output of the AND circuit 94 (point D) outputs the LOW level, and the switch 95 is kept open, so that the constant current 96 does not force discharge.

Therefore, after time 13, the operation described in the conventional example is performed, and the sawtooth wave amplitude value converges to the target value.

Next, when the vertical synchronizing signal frequency is low (50
The operation when the frequency shifts from (Hz) to a high state (100 Hz) will be described. Even when the vertical synchronizing signal is switched from 50 Hz to 100 Hz, the no-signal state is generated, and the self-resetting circuit 8A of the sawtooth wave generating circuit operates to generate the sawtooth wave amplitude. As described above, since the operation is performed without applying the sampling pulse during the period from the generation of the reset pulse to the input of the vertical synchronizing signal, the action on the capacitor 31 in one cycle of the sawtooth wave is the automatic gain control circuit. 2A only, AGC voltage VA1 of one sawtooth wave period
Change amount DVA3_3 of VA1 (10
0 Hz) is replaced with VA1 (50 Hz). DVA3_3 = a * {2 * VCENT-VLOW-VHIGH) * C11 * R7 1 / (VA1 (50Hz) + I75 * R71) -TW} / C31 Formula 3-4 From this, DVA3_3 = -20.5 mV, and the conventional example ( It can be seen that it is smaller than DVA5_3 = −50.8 mV).

Now, when the period of the first sawtooth wave in the non-synchronous signal period is calculated from the equation 5-1 is 23.38 mSEC, and when the non-synchronous signal period Ta is 100 mSEC, the sawtooth wave generated in this period. Wave cycle is 100mSEC / 2
Since it is 3.38 mSEC, it is almost 4 cycles, and the change amount of the AGC voltage VA1 in the non-synchronization signal period is -20.5.
mV * 4 = -0.082V.

From this, the AGC voltage when the vertical synchronizing signal of 100 Hz is input is VA1 (50 Hz) -0.08.
2V = 1.192V, which is lower than the AGC voltage VA1 (100Hz) = 3.773V in the sawtooth wave amplitude stable state at the time of inputting the vertical synchronizing signal 100Hz, which is obtained earlier,
Since the oscillating current at this time is lower than the oscillating current at 100 Hz, two sawtooth waves do not occur within one vertical synchronizing signal period as in the period from time t5 to time t11 in FIG. The amplitude VSAWAMP3_1 of the sawtooth wave at this time is obtained from the above equation 5-1 and is VSAWAMP3_1 = (VA1 + R71 * I75) /
(Fvsync * C11 * R71) = 1.451Vpp, and the maximum peak voltage of the sawtooth wave is VSAWAMP3_
1 + VLOW = 3.451V. Since the maximum peak voltage of the sawtooth wave is VCENT = 3.5V or less, only the charging operation is performed on the capacitor 31 from the automatic gain control circuit 2A, and the vertical synchronizing signal is input, so that the sampling pulse is generated. Due to the action from the amplitude compensation circuit 4A, the charging operation is performed from the rapid charging circuit 5A to the capacitor 31. As a result, the amount of change DVA3_4 of the AGC voltage during one cycle period at the time of inputting the vertical synchronizing signal is the same as the formula 5-10 of the conventional example. DVA3_4 = {a * (1 / fvsync) + c * TW} / C31 Formula 3-5 Due to this AGC voltage change, the sawtooth wave amplitude value gradually converges to the target value.

Next, a sawtooth wave oscillation circuit according to a second embodiment of the present invention will be described.

The sawtooth wave oscillation circuit according to the second embodiment of the present invention has the basic configuration as described above, but the self-reset detection circuit is further devised.

The structure is shown in FIG. Referring to FIG. 5, in the sawtooth wave oscillation circuit according to the second embodiment of the present invention, the SR latch circuit 591 realizes the detection of the period from the generation of the self-reset pulse to the input of the vertical synchronizing signal. S
An inverter 97 is added to the inverting output of the -R latch circuit 591 to make it the data of the D flip-flop 92.

By adding the inverter 97, the delay effect of the inverter is utilized to prevent the D flip-flop 92 from taking a data error at the rising edge of the vertical synchronizing signal.

The self-reset detection circuit 9B of the sawtooth wave oscillation circuit according to the second embodiment of the present invention and the self-reset detection circuit 9B of the sawtooth wave oscillation circuit according to the first embodiment of the present invention.
FIG. 6 shows a comparison of the timing chart with the above.

As is apparent from FIG. 6, the amplitude compensation circuit 4
The waveform at the control signal (point C) of the A switch 41 is
The same applies to the self-reset detection circuits 9A and 9B. The waveform at the control signal (point D) of the switch 95 is
In the self-reset detection circuit 9B, switching is performed at the falling edge of the vertical synchronization signal, whereas in the self-reset detection circuit 9B
In, the switching is performed at the rising timing of the vertical synchronizing signal. That is, it is apparent that the same effect as that of the self-reset detection circuit 9A can be obtained by using the self-reset detection circuit 9B.

Next, a sawtooth wave oscillation circuit according to a third embodiment of the present invention will be described.

In the sawtooth wave oscillation circuit according to the third embodiment of the present invention, the sampling pulse generation circuit is deleted and the self-reset pulse detection circuit and the amplitude compensation circuit are further devised. The block diagram is shown in FIG.

By removing the sampling pulse generating circuit of the sawtooth wave oscillating circuit of the third embodiment of the present invention, the output of the logical sum circuit 82 of the vertical synchronizing signal and the self-reset pulse is used as the trigger signal of the waveform generating circuit 1B. To use.

The self-reset detection circuit 9C outputs the output of the D flip-flop 91 with reset and the D flip-flop 9
A logical product circuit 793 having the inverted output of 2 and the output of the comparator 61 of the quick discharge circuit 6B as an input is provided.
3 and the logical product circuit 94 are input to the logical sum circuit 7
The output of the OR circuit 795 controls the switch 62 of the quick discharge circuit 6B, the output of the D flip-flop 92 is connected to the reset terminal, the vertical synchronizing signal is connected to the clock terminal, and the data terminal is rapidly connected. Charging circuit 5B
The output of the comparator 51 is connected to the reset D flip-flop 796, and the output of the reset D flip-flop 796 controls the switch 52 of the quick charging circuit 5B.

Next, the operation of the sawtooth wave oscillation circuit according to the third embodiment of the present invention will be described.

The reset D flip-flop 91, the D flip-flop 92, and the AND circuit 94 in the self-reset detection circuit 9C of the sawtooth wave oscillation circuit according to the third embodiment of the present invention have the same basic configuration as described above. Therefore, the description is omitted.

When the vertical synchronizing signal frequency is high (100H
The operation at the time of transition from z) to the low state (50 Hz) will be described with reference to FIG.

At time t1, the sawtooth wave amplitude is in a stable state, and the level of Vsaw1 at this time is V1 or more and
It is in a state of less than 2.

At this time, the output (point E) of the comparator 51 of the quick charge circuit 5B is at the low level, so that the output (point H) of the D flip-flop 96 with reset of the self-reset detection circuit 9C is also at the low level, which is rapid. The switch 52 of the charging circuit 5B is in an open state.

On the other hand, since the output (point F) of the comparator 61 of the rapid discharge circuit 6B is also at the low level, the output (point C) of the AND circuit 793 of the self-reset detection circuit 9C is also at the low level, and the AND circuit is further reached. 94 output (point D) is also l
Since it is at the ow level, the output (G
The point) is low level, and the switch 62 of the quick discharge circuit 6B is in an open state.

That is, when the sawtooth wave is in a stable state, the amplitude compensation circuit 4B does not act on the capacitor 31. The vertical synchronizing signal becomes a non-signal state from the time t2 to the time t5, and the sawtooth wave operates by the self-reset pulse, which is the same as the above-described basic configuration. Time t2
From time t3 to time t3, the sawtooth wave level becomes V2 or higher and the output (point F) of the comparator 61 of the rapid discharge circuit 6B is h.
High level, and at the same time, the self-reset detection circuit 9
The output (point G) of the logical sum circuit 795 of C also becomes a high level, and the switch 62 of the quick discharge circuit 6B is closed to discharge the electric charge of the capacitor 31 with the constant current 63.

Since the reset pulse is detected at time t3, the output of the D flip-flop with reset 91 becomes low and the output of the OR circuit 95 (point G) also becomes low level from time t3 to time t5. The switch 62 of the discharge circuit 6B is in the open state.

That is, the capacitor 31 is discharged in the period in which the sawtooth wave level is V2 or more at the beginning after the non-synchronized signal state, but even if the sawtooth wave level after the second shot becomes V2 or more, the amplitude compensation circuit 4b The action on the capacitor 31 is eliminated, and the drop of the AGC voltage VA2 in the non-synchronized signal state is suppressed.

After time t5, the vertical synchronizing signal is input, but at time t5 and time t6, since the reset pulse is detected before that, the output of the AND circuit 94 (point D). ) Is high level,
The output (point G) of the logical sum circuit 95 also becomes high level, and the switch 62 of the rapid discharge circuit 6B is closed to set the constant current 6
At 3, the charge of the capacitor 31 is discharged.

AGC voltage VA2 at time t5 (time t5)
Is still higher than the originally expected voltage, a reset pulse is generated at time t7. Since the reset pulse is detected at the time t7, the time from the time t7 to the time t
9, the output of the logical product circuit 94 (point D) becomes high level, and the output of the logical sum circuit 795 (point G) becomes high.
At the h level, the switch 62 of the rapid discharge circuit 6B is closed to discharge the electric charge of the capacitor 31 with the constant current 63. That is, when the reset pulse is generated even when the vertical synchronizing signal is input, the electric charge of the capacitor 31 can be discharged by the constant current 63 during the period when the vertical synchronizing signal falls after the reset pulse is generated. When the reset pulse is not generated between time t9 and time t10, the AND circuit 94 is generated after time t10.
Output (point D) becomes low level, the output of the D flip-flop with reset 91 becomes high, and the output of the D flip-flop 92 becomes high, so that the OR circuit 9
The output of 5 (point G) is the same as the output of the comparator 61 of the rapid discharge circuit 6B.

Therefore, the sawtooth wave level Vsaw1 is V
If two or more periods occur, the switch 62 is closed during that period to discharge the electric charge of the capacitor 31 with the constant current 63,
If the sawtooth level Vsaw1 is V2 or less, the switch 6
2 is opened, and the quick discharge circuit 6B has no effect on the capacitor 31.

In the D flip-flop 796 of the self-reset detection circuit 9C, there is no clock signal between the non-synchronous signals, and the reset signal (point B) also remains at the low level, so the low level which is the state at time t1. Is held, and from time t5 to time t10,
Since the reset pulse is detected even when the vertical synchronizing signal is input, the reset signal (point B) becomes high level, and the output remains low level.

After time t10, the reset signal (point B) becomes low level, and the output result of the comparator 51 of the quick charging circuit 5B is latched at the rising edge of the vertical synchronizing signal.

That is, if the sawtooth wave level Vsaw1 is V1 or less at the rising timing of the vertical synchronizing signal, 1
The vertical synchronization signal period switch 52 is closed, the capacitor 31 is charged with a constant current 53, and the sawtooth wave level Vsaw is reached.
If 1 is V1 or more, one vertical sync signal period switch 52
The capacitor 31 is opened, and the quick charging circuit 5B has no effect on the capacitor 31.

As described above, in the sawtooth wave oscillation circuit according to the third embodiment of the present invention, the self-reset detection circuit causes the vertical sync signal to be in the no-signal period during the no-sync signal period when the vertical sync signal is switched. The switch 52 of the quick charge circuit 5B and the switch 62 of the quick discharge circuit 6B are opened by detecting the self-reset pulse generated in the internal circuit, and the change of the AGC voltage during the no signal period is suppressed. When the state changes from a low state to a high state, the follow-up speed at which the sawtooth wave converges to the target value after the vertical synchronization signal is input can be increased by the amount by suppressing the change of the AGC voltage within the non-synchronization signal period.

When a self-reset pulse is generated in one vertical sync signal, the switch 62 of the rapid discharge circuit 6B is closed by the self-reset detection circuit until the vertical sync signal is input by the self-reset detection circuit, and the constant current 63 is supplied. In order to forcibly discharge the AGC voltage and to open the switch 52 of the quick discharge circuit 5B so as to eliminate the action from the quick discharge circuit 5B, when the vertical synchronizing signal frequency changes from a high state to a low state, , The follow-up speed at which the sawtooth wave converges to the target value after the vertical synchronizing signal is input can be increased. That is, also in the sawtooth wave oscillation circuit of the third embodiment of the present invention, it is possible to obtain the same effect as that of the sawtooth wave oscillation circuit of the first embodiment of the present invention described above.

[0090]

As described above, the effect of the present invention is that, when the vertical synchronizing signal frequency changes from a low state to a high state, the self-reset detecting circuit causes a self-reset that occurs within a no-signal period of the vertical synchronizing signal. By detecting the pulse and cutting off the action of the amplitude compensation circuit 4A, A in one cycle of the sawtooth wave in the non-synchronous signal period is detected.
Since the amount of change in the GC voltage is set to be smaller than that in the conventional example as in the conventional example DVA5_3 = −50.8 mV of the present invention DVA3_3 = −20.5 mV,
The follow-up speed at which the sawtooth wave converges to the target value after the vertical synchronizing signal is input can be increased by the amount that the change in the AGC voltage during the no-signal period is suppressed.

Especially, the longer the non-synchronization signal period, the more obvious the effect. FIG. 3 shows a tracking diagram of the AGC voltage when the vertical synchronizing signal frequency changes from a low state to a high state.

Furthermore, in the simulation verification,
VLOW = 2.0V, VCENT = 3.5V, VHIG
H = 5.5V, capacitance value of capacitor 11 C11 = 0.0
68 μF, the capacitance value C31 of the capacitor 31 = 33 μF,
R71 = 245K, pulse width of sampling pulse TS TW = 100 μSEC, I75 = 5 μA, constant current 23,
24 current value a = 200 μA, constant current 63 current value b =
20 mA, current value of constant current 53 c = 20 mA, constant current 9
6 current value d = 500 μA, non-synchronization signal period Ta = 10
Assuming 0 mSEC, when the vertical synchronizing signal frequency changes from 50 Hz to 100 Hz, the time from the 100 Hz input until the sawtooth wave amplitude stabilizes is 0.40 SEC. The current value b of the current 63 = 20 mA, the current value c of the constant current 53 = 5
When it is set to mA, the time until the sawtooth wave amplitude stabilizes is 0.86 SEC, and the effect is clear.

When the vertical synchronizing signal frequency changes from a high state to a low state, a self reset pulse is generated in one vertical synchronizing signal in the state where the vertical synchronizing signal frequency is low. During the period from the self-reset pulse generation to the vertical sync signal input by the detection circuit, the AGC voltage is forcibly discharged with the constant current 96,
Moreover, since the action of the amplitude compensation circuit 4A is cut off, the necessary conditions do not exist for the current values b and c of the constant current 63 and the constant current 53, and the sawtooth wave is generated after the vertical synchronization signal is input. The following speed that converges to the target value can be increased.

In particular, as is clear from the equation 3-3, the effect becomes more apparent as the current value d of the constant current 96 increases. FIG. 4 shows a tracking diagram of the AGC voltage when the state of the vertical synchronizing signal frequency changes from the high state to the low state.

Furthermore, in the simulation verification,
With the same constants as above, the vertical sync signal frequency is 100
When the frequency shifts from 50 Hz to 50 Hz, the time from the 50 Hz input until the sawtooth wave amplitude stabilizes is 0.82 SEC, and the current value b of the constant current 63 is 20 mA when the conventional self-reset detection circuit is not provided. Current value c of constant current 53 =
When it is set to 5 mA, the time until the sawtooth wave amplitude stabilizes is 1.12 SEC, and its effect is clear.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a sawtooth wave oscillator circuit according to a first embodiment of the present invention.

FIG. 2 is an operation waveform diagram of the sawtooth wave oscillator circuit according to the first embodiment of the present invention.

FIG. 3 is a tracking diagram of the AGC voltage when the vertical synchronizing signal frequency of the sawtooth wave oscillator circuit according to the first embodiment of the present invention changes from a low state to a high state.

FIG. 4 is a tracking diagram of the AGC voltage when the direct-synchronization signal frequency of the sawtooth wave oscillator circuit according to the first embodiment of the present invention changes from a high state to a low state.

FIG. 5 is a circuit diagram of a sawtooth wave oscillator circuit according to a second embodiment of the present invention.

FIG. 6 is an operation waveform diagram of the sawtooth wave oscillation circuit according to the second embodiment of the present invention.

FIG. 7 is a circuit diagram of a sawtooth wave oscillator circuit according to a third embodiment of the present invention.

FIG. 8 is an operation waveform diagram of the sawtooth wave oscillation circuit according to the third embodiment of the present invention.

FIG. 9 is a circuit diagram of a conventional sawtooth wave oscillation circuit.

FIG. 10 is an operation waveform diagram of a sawtooth wave oscillation circuit of the related art.

FIG. 11 is another operation waveform diagram of the conventional sawtooth wave oscillation circuit.

FIG. 12 is a state in which the vertical synchronizing signal frequency of the saw-tooth wave oscillator circuit of the related art is high (100 Hz) to low (50 H).
It is an operation waveform diagram when it changes to z).

FIG. 13 is a tracking waveform diagram of the AGC voltage when the vertical synchronizing signal frequency of the conventional sawtooth wave oscillation circuit changes from 100 Hz to 50 Hz.

FIG. 14 is a tracking waveform diagram of the AGC voltage when the vertical synchronizing signal frequency of the conventional sawtooth wave oscillation circuit changes from 50 Hz to 100 Hz.

[Explanation of symbols]

1A waveform generator 2A automatic gain control circuit 3A oscillation current generation circuit 4A amplitude compensation circuit 5A quick charge circuit 6A rapid discharge circuit 7A voltage-current conversion circuit 8A self reset circuit 9A, 9B, 9C Self reset detection circuit 11 capacitors 12 Current source 13 switch 15 Comparator 16 flip-flops 17 One-shot circuit 91 D flip-flop with reset 92 D flip-flop 93 AND circuit 94 AND circuit 95 switch 96 current source

Claims (7)

[Claims] 1. A waveform generating circuit for generating a sawtooth wave for vertical deflection in a period from the generation of a self-reset pulse to the input of a vertical synchronizing signal, and an output of the waveform generating circuit to oscillate corresponding to the sawtooth wave. An oscillating current generation circuit that generates a waveform, an automatic gain control circuit that receives the output of the waveform generation circuit and performs an operation of converging the amplitude value of the sawtooth wave to a target value, and compensates the amplitude of the amplitude value of the sawtooth wave. An amplitude compensation circuit, and a sampling pulse output for operating the amplitude compensation circuit, detecting a period from the self-reset pulse generation to the vertical synchronization signal input in a period from the self-reset pulse generation to the vertical synchronization signal input. A sawtooth wave oscillation circuit, comprising: a self-reset detection circuit for shutting off. 2. The self-reset detection circuit detects a period from the self-reset pulse generation to the vertical synchronization signal input, and a period from the self-reset pulse generation to the vertical synchronization signal input in one vertical synchronization signal. 2. The sawtooth wave oscillation circuit according to claim 1, further comprising a constant current source for forcibly charging and discharging the automatic gain control capacitance of the oscillation current generation circuit. 3. The amplitude compensation circuit includes a rapid charging circuit,
The sawtooth wave oscillation circuit according to claim 1 or 2, further comprising: a rapid discharge circuit; and a first switch that switches the rapid charge circuit and the rapid discharge circuit. 4. The one-shot circuit triggered by the leading edge of the vertical synchronizing signal when the vertical synchronizing signal is constantly input to the input terminal, A flip-flop set at the falling edge of the edge, and a second on-controlled by the output of the flip-flop
Switch, a second current source connected to the second switch, a second capacitor whose discharge is started by the second current source, and a comparison result output voltage not more than a set lower limit voltage. Then,
A comparator for resetting the flip-flop by the output of the comparison result, the second switch is off-controlled by the output of the flip-flop, the discharge of the second capacitor is stopped, and the second capacitor The capacitor is constantly supplied with the oscillating current from the oscillating current generating circuit, and when the discharging is stopped, the capacitor starts charging again, the comparison result output voltage rises, and the trailing edge of the next sampling pulse signal falls, The flip-flop is set again, the second switch is turned on again by the output of the flip-flop, the discharge of the second capacitor is restarted by the second current source, and the comparison result output voltage is again set. The sawtooth wave oscillator circuit according to claim 1, 2 or 3, which descends. 5. The self-reset detection circuit always inputs high to a data terminal, holds a vertical synchronization signal at a clock terminal, holds data input to the data terminal at a falling edge of the vertical synchronization signal, and resets the reset terminal. The output of the self-reset circuit is connected to the first reset D flip-flop that is reset when the self-reset pulse is high, and the inverted output of the first reset D flip-flop is input to the data terminal, A vertical synchronization signal is input to the clock terminal, and a D flip-flop that holds the data input to the data terminal at the rising edge of the vertical synchronization signal, an output of the first D flip-flop with reset and an inverted output of the D flip-flop And the sampling pulse signal output from the waveform generation circuit are input, and the output signal First controlling the second switch of the amplitude compensation circuit
And a second AND circuit that receives the inverted output of the first D flip-flop with reset and the output of the D flip-flop as input and controls the switch with an output signal, and the control of the switch. The saw-tooth wave oscillation circuit according to claim 1, 2 or 3, further comprising a constant current source for discharging the electric charge of the capacitor. 6. The self-reset detection circuit detects the period from the self-reset pulse generation to the input of the vertical synchronizing signal, and an SR latch circuit, and the D flip-flop receives a data error at the rising edge of the vertical synchronizing signal. The sawtooth wave oscillation circuit according to claim 4, further comprising: 7. A third AND circuit which receives the output of the D flip-flop with reset, the inverted output of the D flip-flop, and the output of the second comparator of the rapid discharge circuit as inputs to the self-reset detection circuit. And a first logical sum circuit having the outputs of the second logical product circuit and the third logical product circuit as inputs, and the rapid discharge is performed at the output of the first logical sum circuit. A second reset with controlling the switch of the circuit, in which the output of the D flip-flop is connected to the reset terminal, the vertical synchronizing signal is connected to the clock terminal, and the output of the comparator of the quick charging circuit is connected to the data terminal. The sawtooth wave oscillation circuit according to claim 4, further comprising a D flip-flop, and an output of the second D flip-flop with reset controls a switch of the quick charging circuit.