JP2003163606A - Switch semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switch semiconductor integrated circuit capable of suppressing a higher harmonic level satisfying legal regulations. <P>SOLUTION: Between a common input/output terminal 40 and a first input/ output terminal 41 provided in a switch circuit S1, a first field effect transistor 1 turning the two input/output terminals 40 and 41 to a conductive state as desired is provided. Further, between the common input/output terminal 40 and the ground, a serial resonance circuit 35 serially resonating at desired higher harmonics is provided so as to be serially connected through a second field effect transistor 2. To the first input/output terminal 41, a low-pass filter LPF1a having attenuation characteristics to the desired higher harmonics and constituted so as to pass through fundamental waves to the higher harmonics is cascade-connected, and higher harmonic attenuation characteristics higher than before are obtained. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch semiconductor integrated circuit for switching input / output signals in a high frequency circuit, and more particularly to suppressing or reducing a harmonic component generated by the non-linearity of the switch semiconductor integrated circuit. Related to.

[0002]

2. Description of the Related Art Conventionally, as a circuit of this type, for example,
The single-pole 4-throw switch circuit Sc and the like used in the dual band mobile phone as shown in FIG. 9 are publicly known and well known. The conventional circuit will be described below with reference to FIG.
An antenna 71 of a so-called dual-band mobile phone, which is a semiconductor integrated circuit having first to fourth transistors TR1 to TR4 by field effect transistors as main constituent elements, and which enables transmission and reception at two different radio frequencies. High frequency circuit LNA1, PA1, L in the latter stage
It is provided and used between NA2 and PA2. Here, LNA1 is a reception front end for one of two different frequencies, that is, band A, PA1 is a transmission amplification unit of band A, and LNA2 is the other band of two different frequencies, that is, band B.
The reception front end PA2 is a band B transmission amplification unit.

In such a configuration, for example, when band A is received, the control voltage VA is set to a predetermined value so that TR1 becomes conductive, while the other TR2.
In TR4, the respective control voltages VB, VC and VD are set to predetermined values so as to be in a non-conducting state (see FIG. 8). Also in the case where any one of the other transistors TR2 to TR4 is made conductive, it is assumed that the conduction and non-conduction of the respective transistors TR1 to TR4 are controlled by the control voltages VA to VD as shown in FIG. Has become.

[0004]

However, in the above-mentioned conventional circuit, harmonics are generated due to the non-linear characteristic of the field effect transistor, and in particular, at the time of transmission, it is output from the antenna 71 together with the transmission signal.
With respect to the electromagnetic wave output from No. 1, the output level and the allowable value of unnecessary frequency components are regulated by the Radio Law, and it is necessary to suppress the harmonic level so as to satisfy these requirements. As a measure for suppressing this harmonic level, for example, a single-pole 4-throw switch circuit Sc and an antenna 7 are used.
It is conceivable that a band-pass filter of two bands is provided between 1 and 1. However, there is a limit to the amount of harmonic suppression by the bandpass filter due to the loss of the coil that constitutes the bandpass filter, and the required harmonic suppression level is not always satisfied.

The present invention has been made in view of the above circumstances, and provides a switch semiconductor integrated circuit which suppresses generation of unnecessary harmonics and has a small passage loss.
Another object of the present invention is to provide a switch semiconductor integrated circuit capable of suppressing harmonic levels that satisfy legal regulations.

[0006]

In order to achieve the above object of the present invention, a switch semiconductor integrated circuit according to the present invention is
A switch semiconductor integrated circuit having one input / output terminal and a switch circuit provided with a switch element for short-circuiting terminals for electrically connecting the two input / output terminals as desired. A series resonance circuit that resonates in series at a desired harmonic is provided between one input / output terminal of the switch circuit and the ground so as to be connected in series via a resonance circuit connecting switch element, while the other of the switch circuits is provided. A low-pass filter is connected in series to the input / output terminals of the low-pass filter, and the low-pass filter has a first coil and a second coil from the other input / output terminal side to the other input / output terminal. In addition to being connected in series,
A first capacitor is connected between the mutual connection point of the first and second coils and the ground, and a second capacitor is connected between the other end of the second coil and the ground. A third capacitor is connected in parallel to the second coil and has an attenuation characteristic with respect to the desired harmonic while being capable of passing a fundamental wave with respect to the desired harmonic. is there.

In such a configuration, when the switch element for short-circuiting the terminals through which the signal serving as the fundamental wave with respect to the desired harmonic wave passes is turned on by the control voltage from the outside, the switch element for connecting the resonance circuit is also simultaneously turned on. When turned on, the series resonance circuit is connected between one input / output terminal and the ground, and it is connected to the other input / output terminal and has a low-pass with the same attenuation pole as the resonance frequency of the series resonance circuit. Due to the interaction with the filter, only the predetermined harmonics contained in the signal that passes through the switch device for short-circuiting between terminals, that is, only the signal that matches the resonant frequency of the series resonant circuit, is efficiently removed. The signal of the frequency component can pass through the switching element for short circuit between terminals, which is affected by the series resonant circuit, suppresses the generation of unnecessary harmonics, and Small loss Sutchi semiconductor integrated circuit in which it is to be provided.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS. The members, arrangements, and the like described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention. First, a first configuration example will be described with reference to FIG. The switch semiconductor integrated circuit SIC1 in the first configuration example mainly includes a switch circuit S1 including a series resonance circuit 35, and a low-pass filter LPF1a cascade-connected to the subsequent stage of the switch circuit S1. It is configured as an element. The switch circuit S1 includes first and second field effect transistors (“TR1” and “TR2” in FIG. 1, respectively).
2) and the series resonance circuit 35 as main constituent elements, a so-called semiconductor switch circuit is configured.

That is, first, the drain (or source) of the first field effect transistor 1 as a switching element for short-circuiting terminals is connected to the common input / output terminal 40. The transmitting / receiving antenna 60 is connected outside the switch semiconductor integrated circuit SIC1. The source (or drain) of the first field effect transistor 1 is connected to the first input / output terminal 41. In other words, the first field effect transistor 1 forms a signal line between the common input / output terminal 40 and the first input / output terminal 41 of the switch circuit SC1. A low pass filter LPF1a (details will be described later) is provided between the first input / output terminal 41 and the second input / output terminal 42. In the switch circuit S1, the gate of the first field effect transistor 1 is connected to the first control voltage terminal 46 via the first gate resistor (denoted as “RG1” in FIG. 1) 11. There is.

On the other hand, the drain (or source) of the second field effect transistor 2 as a switching element for connecting a resonance circuit is connected to the common input / output terminal 40, while the source (or drain) is connected to the ground. A series resonance circuit 35 is provided in the above-described circuit. That is,
A fourth capacitor (denoted as “C1” in FIG. 1) 21 is connected between the source of the second field effect transistor 2 and the external element connection terminal 51. Then, outside the switch circuit S1, a third coil (FIG. 1) is provided between the external element connection terminal 51 and the ground.
In FIG. 3, a series resonance circuit 35 is configured by the fourth capacitor 21 and the third coil 31. In other words, the series resonance circuit 35 is provided in series between the signal line (the first field effect transistor 1 in the embodiment of the invention) and the ground. The gate of the second field effect transistor 2 has a second gate resistor (denoted as “RG2” in FIG. 1) 12
Is connected to the first control voltage terminal 46 via.

Next, the low-pass filter LPF1a is provided between the first input / output terminal 41 and the second input / output terminal 42.
The first coil 32 and the second coil 33 are connected in series from the side of the first input / output terminal 41, and the first coil 32 and the second coil 33 are provided.
And the first capacitor 22 is provided between the mutual connection point of the second coils 32 and 33 and the ground, and the mutual connection point of the second coil 33 and the second input / output terminal 42. The second capacitor 23 is provided between the second coil 33 and the ground, and the third capacitor 24 is connected in parallel to the second coil 33 to configure the low-pass filter LPF1a. It has become a thing. The low pass filter LPF1a has component constants set so that the fundamental wave is passed and an attenuation pole is generated at the same frequency as the resonance frequency of the series resonance circuit 35.

Next, the operation of this configuration will be described. For example, a case of applying a signal of frequency f ₀ to the second input / output terminal 42 from the outside and transmitting from the transmitting / receiving antenna 60 will be described. In this case, first, an external circuit (not shown) causes a first control voltage to be applied. When the control voltage VA is applied to the terminal 46, both the first and second field effect transistors 1 and 2 become conductive. As a result, the signal of the frequency f ₀ applied to the second input / output terminal 42 has the low-pass filter LPF1a and the first field effect transistor set so that the second harmonic frequency of f ₀ is set to the attenuation pole. 1 to the common input / output terminal 40. However, after the first pass of the field-effect transistor 1, the second harmonic frequency of the frequency f ₀ contained in the passing signal, since the second field effect transistor 2 is in a conductive state, the f ₀ It is attenuated by the series resonance circuit 35 having the second harmonic frequency as the resonance frequency. As a result, the fundamental wave f is transmitted from the transmitting / receiving antenna 60.
_The fundamental wave from which the second harmonic of ₀ is sufficiently removed is radiated.

Here, when it is desired to remove the second harmonic component of the fundamental wave f ₀ , the component constants (inductance value and capacitance value) of the third coil 31 and the fourth capacitor 21 of the series resonance circuit 35 are as follows. It is set based on Equation 1. _{2 × f 0 = 1 / {} 2π (L1 · C1) 1/2} ··· Equation 1 In this case, L1 is the inductance value of the third coil 31, are C1, the capacity of the fourth capacitor 21 Let it be a value.

[0014] As a result of the series resonant circuit 35 resonates at a frequency of 2 × f _0, the signal of the frequency of 2 × f ₀ becomes to be reflected at the common input-output terminal 40. In other words, 2
The common input / output terminal 40 for the signal of the frequency of × f ₀ is
It is equivalent to being shorted to ground, so
A signal having a frequency of 2 × f ₀ will not be radiated from the transmitting / receiving antenna 60. However, in reality, there is a loss of the third coil 31 that configures the series resonance circuit 35, and the amount of harmonic suppression by the series resonance circuit 35 is limited. In the embodiment of the invention, the signal f ₀ passing through is
Low-pass filter L with the second harmonic frequency of
The PF 1a has a first input / output terminal 41 and a second input / output terminal 4
Since the second harmonic wave frequency component of the fundamental wave is provided, the second harmonic wave frequency component of the fundamental wave is efficiently removed by the interaction with the series resonance circuit 35.

Here, a specific example of the frequency is the second.
The input signal applied to the input / output terminal 42 of
If the frequency is GHz, the series resonance circuit 35 does not radiate the transmission signal of 1.8 GHz, which is the second harmonic, from the transmission / reception antenna 60, and the signal of 0.9 GHz is
It is radiated from the transmitting / receiving antenna 60 without receiving any power loss due to the series resonance circuit 35. next,
The harmonic characteristics of the first configuration example will be described in comparison with those of other circuit configurations with reference to FIGS. 2 to 5. First, in FIG. 2, the switch circuit S1 is used without using the low pass filter LPF1a in the configuration shown in FIG.
FIG. 3 is a circuit diagram showing only the case, and FIG. 3 is a circuit diagram showing the low pass filter LPF1a in the configuration shown in FIG.
FIG. 4 is a circuit diagram when a 3-pole low pass filter LPF1b is provided, and FIG. 4 is a circuit diagram when neither the series resonance circuit 35 nor the low pass filter LPF1a is used.
Then, FIG. 5 shows a characteristic table for explaining these harmonic characteristics. That is, in the characteristic table shown in FIG. 5, a signal of 9000 MHz and +34 dBm is input to the second input / output terminal 42 in the configuration example shown in FIG. In the circuit
The second harmonic level at the common input / output terminal 40 when applied to a terminal corresponding to the second input / output terminal 42 is shown.

According to the table, in the case of the configuration shown in FIG. 1, the second harmonic is at a level of -79.1 dBc, whereas only the series resonance circuit 35 shown in FIG. 2 is used. 2 has a configuration of -70 dBc, and a configuration using the series resonance circuit 35 and the three-pole low-pass filter LPF1b shown in FIG. 70 dBc, the series resonance circuit 35 shown in FIG. 4, and the low pass filter LPF1a (or the three-pole low pass filter LPF1b) are configured to use −60.5 dBc. That is, in the switch circuit S2 shown in FIG. 4 in which no measures are taken against harmonics, the field effect transistor TR
The second harmonic is generated due to the non-linearity of 1, so that the level of the harmonic is the highest and the suppression characteristic of the harmonic is the worst. On the other hand, in the circuit shown in FIG. 2, since the series resonance circuit 35 is provided, it can be understood that higher harmonics are suppressed as compared with the circuit shown in FIG.
Further, the circuit shown in FIG. 3 has a configuration in which a three-pole low-pass filter LPF1b is used in addition to the series resonance circuit 35, but the level of harmonics is different from that of the series resonance circuit 35 of FIG.
It is the same as that of the configuration using only, and it can be understood that the three-pole low-pass filter LPF1b does not have the suppressing effect on the second harmonic generated in the first field-effect transistor 1. There is. On the other hand, in the configuration shown in FIG. 1, the low voltage is provided in the previous stage of the first field effect transistor 1, that is, on the side to which the input signal to the first field effect transistor 1 is applied. Due to the interaction between the band pass filter LPF1a and the series resonance circuit 35, the suppression amount of the second harmonic is increased by 9.1 dB as compared with the circuit shown in FIG. 2 and the circuit shown in FIG. I understand.

Next, a second structural example will be described with reference to FIG. The same components as those shown in FIG. 1 are designated by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below. This second configuration example is a configuration example in the case of being used in a so-called triple band mobile phone configured to be capable of transmitting and receiving in three bands (frequency bands), and the switch semiconductor integrated circuit SIC3 is provided for each band. Reception front ends 61, 63, 65 and transmission amplification units 62, 64
And a transmission / reception antenna 60 are provided between the transmission / reception antenna 60 and the transmission / reception antenna 60. The configuration will be specifically described below. First, the switch circuit S3 in the second configuration example includes first to fifth field effect transistors (in FIG. 6, respectively) as switch elements for short-circuiting terminals. "TR1", "T
Notated as "R2", "TR3", "TR4", "TR5")
A single-pole five-throw switch circuit including 1 to 5 is formed, and a sixth field effect transistor (denoted as "TR6" in FIG. 6) as a resonance circuit connecting switch element 6
The serial resonance circuit 35 is configured to be connected between the common input / output terminal 40 and the ground as will be described later.

That is, the drains (or sources) of the first to sixth field effect transistors 1 to 6 are commonly connected to the common input / output terminal 40. The source (or drain) of the first field effect transistor 1 is connected to the first input / output terminal 41, and the source (or drain) of the second field effect transistor 2 is connected to
The source (or drain) of the third field effect transistor 3 is connected to the second input / output terminal 42 by the third input / output terminal 43.
The source (or drain) of the fourth field effect transistor 4 is at the fourth input / output terminal 44, and the source (or drain) of the fifth field effect transistor 5 is at the fifth input / output terminal 45. Each is connected. And the first
The input / output terminal 41 is connected to the A-band reception front end 61, and the second input / output terminal 42 is connected to the output stage of the low-pass filter LPF1a.
The A-band transmission amplification section 62 is connected to the input stage of F1a. Further, the reception front end 63 for B band is connected to the third input / output terminal 43.
The fourth input / output terminal 44 is connected to the B and C band transmission amplification section 64, and the fifth input / output terminal 45 is connected to the C band reception front end 65.

Here, the reception front end 6 for the A band is used.
Reference numeral 1 denotes a circuit for first amplifying a received wave in the A band, and its output signal is input to an A band receiving circuit in the subsequent stage (not shown). The A-band transmission amplification unit 62 is a circuit that performs final amplification on the A-band transmission wave. Further, the reception front end 63 for the B band is a circuit that firstly amplifies the received wave of the B band, and its output signal is input to a B band reception circuit (not shown) in the subsequent stage. There is. The B- and C-band transmission amplification unit 64 is a circuit that performs final amplification on the B-band and C-band transmission waves. Further, the reception front end 65 for the C band is C
A circuit that applies the first signal amplification to the received wave of the band,
The output signal is input to a C-band receiving circuit (not shown) at the subsequent stage.

Further, the gate of the first field effect transistor 1 is connected to the first control voltage terminal 46 via the first gate resistor 11, and the gate of the second field effect transistor 2 is connected to the second gate. The second control voltage terminal 47 is connected via the resistor 12, and the gate of the third field effect transistor 3 is connected via the third gate resistor (denoted as “RG3” in FIG. 6) 13 to the third control voltage terminal 47. The gate of the fourth field effect transistor 4 is connected to the control voltage terminal 48 via the fourth gate resistor (indicated as “RG4” in FIG. 6) 14 to the fourth control voltage terminal 49 and the fifth gate. The gate of the field effect transistor 5 is connected to the fifth control voltage terminal 5 via a fifth gate resistor (denoted as “RG5” in FIG. 6) 15.
0, and the gate of the sixth field effect transistor 6 is connected to the second control voltage terminal 47 through a sixth gate resistor (denoted as “RG6” in FIG. 6) 16. Has been done. On the other hand, on the source (or drain) side of the sixth field effect transistor 6, a series resonance circuit 35 having the same configuration as shown in FIG. 1 is connected.

Next, the operation of this structure will be described with reference to FIG. For example, when receiving band A, an external circuit (not shown) sets the control voltage VA at the first control voltage terminal 46 to a predetermined voltage that brings the first field effect transistor 1 into a conductive state, The second to fifth control voltages VB, VC, VD and VE are set to predetermined voltages for making the second to fifth field effect transistors 2 to 5 non-conductive, and the sixth field effect transistor 6 The control voltage VB of the second control voltage terminal 47 is applied to the gate of the gate (see FIG. 8). Therefore, only the first field effect transistor 1 becomes conductive (in other words, the common input / output terminal 40 and the first input / output terminal 41 are turned on), and the second to fifth field effect transistors 2 to 2 are connected. 5 becomes non-conductive (in other words, the common input / output terminal 40 and the second to fifth input / output terminals 42 to 45 are turned off), and the sixth field effect transistor 6 has its gate Since the second control voltage VB is applied to, the state becomes non-conductive. Therefore, the band A signal from the transmission / reception antenna 60 passes through the first field effect transistor 1 and is input to the A band reception front end 61, where it is subjected to signal amplification and is supplied to the band A in the subsequent stage (not shown). The signal is input to the receiving circuit, demodulated, etc., and received in band A.

Next, when the band A is transmitted, the control voltage VB at the second control voltage terminal 47 is set to a predetermined voltage for turning on the second field effect transistor 2 by an external circuit (not shown). On the other hand, the first control voltage VA and the third to fifth control voltages VC, VD and VE are
The field effect transistor 1 and the third to fifth field effect transistors 3 to 5 are set to a predetermined voltage to make them non-conductive, and the gate of the sixth field effect transistor 6 has a second control voltage terminal. The control voltage VB of 47 is applied (see FIG. 8). As a result, only the second field-effect transistor 2 becomes conductive (in other words, the common input / output terminal 40 and the second input / output terminal 42 are turned on), and the first field-effect transistor 1 and the third field-effect transistor 3 are turned on. To the fifth field effect transistors 3 to 5 are in a non-conducting state (in other words, between the common input / output terminal 40 and the first input / output terminal 41, and between the common input / output terminal 40 and the third to the fifth). The output signal from the A-band transmission amplification unit 62 is a low-pass filter LPF1a having an attenuation pole at the second harmonic frequency of the A-band transmission frequency.
It will pass through the second field effect transistor 2.

On the other hand, due to the conduction of the sixth field effect transistor 6, the series resonance circuit 35 is connected between the common input / output terminal 40 and the ground, and therefore the second resonance circuit 35 is connected.
Of the signals of the A band that have passed through the field effect transistor 2, the frequency component that is the same as the resonance frequency of the series resonance circuit 35 will be removed by the series resonance circuit 35. The circuit 35 radiates the signal of band A from which the predetermined harmonic component is removed. Here, as a specific example of the frequency, a triple band mobile phone has a band A of 0.9.
In the case where the band, the band B is set to 1.8 GHz, and the band C is set to 1.9 GHz, the series resonance circuit 35 causes the second harmonic wave at the time of transmitting the band A, that is, at the time of transmitting 0.9 GHz. A certain 1.8 GHz transmission signal is not radiated from the transmission / reception antenna 60, and a 0.9 GHz transmission wave is radiated from the transmission / reception antenna 60 without any power loss due to the series resonance circuit 35. . The first field effect transistor 1 and the third to fifth field effect transistors 3 to
Also in the case where any one of the transistors 5 is turned on, as shown in FIG.
Is controlled by control voltages VA and VC to VE.

Next, a third structural example will be described with reference to FIG. The same components as those shown in FIGS. 1 and 6 are designated by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below. The third configuration example is a series resonance circuit 35A.
The third coil 31 configuring the above is configured to be provided in the switch circuit S4 together with the fourth capacitor 21, and the other components are the same as those of the second capacitor shown in FIG. It is the same as the configuration example. That is, the source (or drain) of the sixth field effect transistor 6 is
One end of the fourth capacitor 21 is connected, and the other end of the fourth capacitor 21 is connected to one end of the third coil 31. The other end of the third coil 31 is
The external element connection terminal 51 is connected, and the external element connection terminal 51 is connected to the ground outside the switch circuit S4. The reason why the series resonance circuit 35A is provided inside the switch circuit S4 is as follows. That is, in the case where the coil (the third coil 31 in this third configuration example) is provided inside the switch circuit S4, it is necessary to eliminate the external connection parts in the recent mobile phones that are required to be further downsized. This is because it will meet the demand for miniaturization. Further, in a semiconductor IC that handles high-frequency signals (so-called MMIC), a switch semiconductor integrated circuit SIC
When 4 is an MMIC, if the coil is formed monolithically inside the MMIC, variation in element characteristics can be suppressed as compared with the case where a coil is used as an external component. is there.

The operation in this configuration is basically as shown in FIG.
This is similar to the case of the second configuration example shown in FIG. That is, during transmission of the band A, the second and sixth field effect transistors 2 and 6 are rendered conductive, and the series resonant circuit 35A is connected in series between the common input / output terminal 40 and the ground, whereby series connection is achieved. The transmission wave from which the second harmonic of the transmission wave is removed by the resonance circuit 35A is radiated from the transmission / reception antenna 60. The operation at the time of receiving band A, transmitting bands B and C, and receiving band C is shown in FIG.
Since there is no difference from the case of the second configuration shown in FIG. 2, the detailed description thereof will be omitted here.

In the examples shown in FIGS. 6 and 7 described above, a so-called single-pole 5-throw switch circuit is constructed, but of course, it is not limited to 5 throws, and the switch according to the present invention is not limited. The semiconductor integrated circuit can be similarly applied to a single-pole n-throw switch circuit (n is an integer of 2 or more).

[0027]

As described above, according to the present invention,
By ensuring that only the harmonic components of the signal are bypassed while ensuring the passage of the desired signal,
It is possible to provide an effect that it is possible to provide a switch semiconductor integrated circuit that suppresses the generation of unnecessary harmonics and has less passage loss. In particular, a configuration is such that a series resonance circuit for removing harmonics is provided between the signal line and ground, while a low-pass filter having the resonance frequency of the series resonance circuit as an attenuation pole is connected in series to the signal line. Therefore, the interaction between the series resonance circuit and the low-pass filter has an effect of sufficiently removing harmonics as compared with the conventional case. Furthermore, since the series resonance circuit for removing the harmonics is arranged so that when the fundamental wave generating the harmonics passes through the signal line, the series resonance circuit is arranged in series between the signal line and the ground, for example, a triple band circuit. In the case where the frequency of the signal of one band is in a multiple relationship with the frequency of the other band, the series resonance circuit for removing harmonics of the frequency of the other band is It is possible to reliably avoid the occurrence of loss with respect to the passage of the filter, and it is possible to sufficiently remove harmonics compared to the conventional method by the interaction between the series resonance circuit and the low-pass filter. Is played.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of a switch semiconductor integrated circuit in a first configuration example of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a circuit configuration when a low-pass filter is removed from the configuration shown in FIG.

FIG. 3 is a circuit diagram showing a circuit configuration when the low pass filter in the configuration shown in FIG. 1 is replaced with a three-pole low pass filter.

FIG. 4 is a circuit diagram showing a circuit configuration when a series resonance circuit and a low pass filter are removed from the configuration shown in FIG.

FIG. 5 is an explanatory diagram illustrating a harmonic characteristic of the switch semiconductor integrated circuit according to the first configuration example of the embodiment of the present invention.

FIG. 6 is a circuit diagram showing a circuit configuration of a switch semiconductor integrated circuit according to a second configuration example of the embodiment of the present invention.

FIG. 7 is a circuit diagram showing a circuit configuration of a switch semiconductor integrated circuit according to a third configuration example of the embodiment of the present invention.

FIG. 8 is an explanatory diagram illustrating an operation with respect to a control voltage applied to the conventional circuit and the switch semiconductor integrated circuit according to the embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration example of a conventional circuit.

[Explanation of symbols]

1 ... First field effect transistor 2 ... second field effect transistor 3 ... Third field effect transistor 4 ... Fourth field effect transistor 5 ... Fifth field effect transistor 6 ... Sixth field effect transistor 35, 35A ... Series resonant circuit 40 ... Common input / output terminal 41 ... First input / output terminal 42 ... Second input / output terminal 43 ... Third input / output terminal 44 ... Fourth input / output terminal 45 ... Fifth input / output terminal

Claims (4)

[Claims] 1. A switch semiconductor comprising a switch circuit having two input / output terminals and provided with a switch element for short-circuiting terminals for electrically connecting the two input / output terminals as desired. An integrated circuit, in which a series resonance circuit that resonates in series at a desired harmonic is provided between one input / output terminal of the switch circuit and the ground so as to be connected in series via a resonance circuit connection switch element. A low-pass filter is connected in cascade to the other input / output terminal of the switch circuit, and the low-pass filter is connected to the other input / output terminal from the other input / output terminal side to a first coil. A second coil is provided in series connection, and a first capacitor is provided between the mutual connection point of the first and second coils and the ground and the other end of the second coil. A second capacitor connected between the second coil and a ground, and a third capacitor connected in parallel to the second coil, which has an attenuation characteristic for the desired harmonic, A switch semiconductor integrated circuit, which is configured to pass a fundamental wave of the harmonic. 2. The switch circuit includes a plurality of inter-terminal short-circuiting switch elements, and one terminal of the plurality of inter-terminal short-circuiting switch elements is connected to a common input / output terminal while the plurality of inter-terminal short-circuiting switch elements are connected. The other terminal of the inter-terminal short-circuit switch element is connected to each of a plurality of input / output terminals provided corresponding to the plurality of inter-terminal short-circuit switch elements, and the plurality of inter-terminal short-circuit switch elements are desired. 2. The switch semiconductor integrated circuit according to claim 1, wherein the corresponding input / output terminal and the common input / output terminal are made conductive by setting one of them to be conductive. 3. The series resonance circuit includes a fourth capacitor provided inside the switch circuit and a third coil provided outside the switch circuit, and one end of the fourth capacitor has one end. One end of the fourth coil and one end of the third coil, which are connected to the other of the resonance circuit connecting switch elements connected to one of the input / output terminals,
3. The switch semiconductor according to claim 1, wherein the switch circuit is connected to each other through an external element connection terminal provided in the switch circuit, and the other end of the third coil is connected to the ground. Integrated circuit. 4. A series resonance circuit comprises a fourth capacitor and a third coil provided in a switch circuit, and one end of the fourth capacitor is a resonance whose one end is connected to one input / output terminal. It is connected to the other of the circuit connection switch elements, the other end of the fourth capacitor and the one end of the third coil are connected to each other, and the other end of the third coil is external to the switch circuit. 3. The switch semiconductor integrated circuit according to claim 1, wherein the switch semiconductor integrated circuit is connected to the ground via an element connection terminal.