JP2003163556A - Signal intensity detection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent ambient temperature dependence from arising in a signal intensity detected value in a device for detecting an intensity of a signal inputted to saturation amplifiers connected in a cascade. <P>SOLUTION: Four-stage saturation amplifiers 101-104 connected in a cascade respectively have two gain control terminals Vc1 and Vc2. The gain control terminal Vc1 applies such a bias as varies no gain of the saturation amplifiers according to a temperature. Outputs of the saturation amplifiers are subject to full-wave rectification by commutators 111-114 and are smoothed by LPFs 121-124. The smoothed intensity signal of each saturation amplifier is inputted to an adder circuit 141 and used to form an RSSI total output. The smoothed intensity signal of each saturation amplifier is inputted to amplitude control bias generators 131-134, and is converted into a signal for the gain control terminal Vc2. By a signal inputted from the gain control terminal Vc2, the saturation amplifier is controlled lest its saturation level exceed a fixed value. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal strength detection circuit, and more particularly to an amplifier device having a function of detecting the strength of a carrier signal such as a received signal or a transmitted signal in a communication device such as a television, a radio, a CATV and a radio. It is about.

[0002]

2. Description of the Related Art A signal strength detector (Received-Signal Stren
gth Indicator) RSSI measures and displays the strength (power) of the received signal, but it is not only displayed, but also based on the signal strength obtained, it is fed back to the amplifier circuit of the receiver and automatic gain control is performed. It is used for, and is used when requesting the output according to strength from the sender. The transmitter is also used when the signal strength of the transmitter is evaluated by RSSI and the control is performed so as to obtain a desired output. in this way
RSSI is an important functional block often used inside the transceiver of a wireless system.

Due to recent advances in mobile communication technology, mobile radio has come into widespread use, but RSSI is also used in these devices. In mobile devices, it is necessary to cope with fluctuations in power supply voltage due to dry cell operation and fluctuations in ambient temperature. Further, in portable devices, it is general to use a saturated amplifier capable of linear operation with high efficiency for the purpose of reducing current consumption. Traditional RSSI
FIG. 10 shows an example of the calculation circuit of. In this mode, the saturation amplifiers 1001 to 1004 are cascade-connected, an input signal IN such as an intermediate frequency signal is input from an input terminal, and an output signal OUT is obtained from an output terminal. Saturation amplifier of each stage 1001-1
004 is a constant g so that it is amplified with a constant amplification degree regardless of temperature.
It is driven by the bias generated by the m-bias generation unit 1051. Then, the output of the saturation amplifier of each stage is rectified by the rectifier 1011-
After full-wave rectification at 1014 and smoothing at low-pass filters 1021 to 1024, the addition circuit 1041 adds them to obtain an RSSI total output. By the way, when the saturation amplifier is saturated, the DC output of the full-wave rectifier is also saturated. RSSI when simply detecting saturation
Assuming that 1 is output at the output of
It can be seen that the output relationship is as follows. If the gains of the saturation amplifiers in FIG. 10 are all the same, the output increases with the exponent such that the second stage is the square of the gain of the first stage, the third stage is the third power and the fourth stage is the fourth power. When the fourth stage, which is the last stage in FIG. 10, finally has an input power that is saturated, 1 is output as the RSSI output only after amplification by the fourth power gain of the first stage. Since the input power of the second saturation level from the final stage is saturated through the amplification circuit of three stages, RSSI output of 1 is output from the third stage in addition to the RSSI output of the final stage. Last stage RSSI
Combined with output 1, RSSI total output is output as 2. Similarly, at a large input power level where the first stage is saturated, the gain of the first stage saturates all stages of the saturation amplifier, so the total RSSI output is
It turns out to be 4. As described above, since the RSSI output of each stage is weighted by the nth power of the gain, the sum R
The SSI total output changes linearly with the input signal power. If the number of stages is increased and the gain per stage is decreased, the input power will increase linearly approximately in dBm (solid line in FIG. 9).

The relationship between the total output of the RSSI and the input power (dbm) shown in FIG. 9 varies depending on the gain of the saturation amplifier and the saturation power. For example, when the gain of the saturation amplifier becomes smaller than the characteristic shown by the solid line in FIG. 9, the gain shifts to the right as shown by the dotted line. Further, as the saturation power of the saturation amplifier increases, the slope becomes steep as shown by the broken line. As mentioned earlier, the portable device is required to stably maintain the same output value for the RSSI output even when the power supply voltage fluctuates and the environmental temperature fluctuates. Needs to stay the same. The operation of causing the gain fluctuation due to the temperature fluctuation and shifting the RSSI output as shown by the dotted line in FIG. 9 can be prevented by performing gain control so as to compensate for the temperature change of the gain of the saturation amplifier. Realization is easy. When a differential circuit of bipolar transistors is used as a saturation amplifier, a transistor for flowing a tail current may be biased with a constant current source proportional to absolute temperature (for example, Japanese Patent Laid-Open No. 2001-7654). Specifically, for example, as shown in FIG. 11 for only one stage, in a circuit having a logarithmic amplification unit 1101 and an amplitude detection unit 1102, the logarithmic amplification unit 11
When the differential amplifier of 01 is operated with a constant gain, the transistor Q1 for flowing the tail current may be biased by the constant current source 1103 proportional to the absolute temperature. In addition, the MOS shown in FIG.
When using a differential circuit composed of FETs as a saturation amplifier, a transistor that supplies tail current is constantly
gm bias method (for example, "Design of Analog CMOS Integra
ted Circuit "by Behzad Razavi, MacGraw-Hill, pp. 392.
-393). The principle will be briefly described with reference to FIG. In the constant gm bias generation circuit 411, M30 and M40 are pMOSFETs forming a current mirror. M10 and M20 are nMOSFETs, and the gate width of M20 is K times larger than that of M10. In the saturation amplifier 401, these MO
SFETs are operating in the current saturation region, and it is assumed that they have a gate voltage-drain current characteristic having a square characteristic. In the constant gm bias generation circuit 411, when Cox is the gate oxide film capacity per unit area, μ _n is the effective carrier mobility, and the gate width / gate ratio of M10 is (L / W), M30
And M40, Iout = Iref holds, and Iout and Iref are given by equation 1.

[0005]

[Equation 1] If the tail current of the differential circuit that flows through M50 is copied from Iref in a one-to-one manner, gm of the differential circuit is given by equation 2.

[0006]

[Equation 2] Therefore, gm has only temperature dependence of RS. In reality, the temperature dependence of RS remains, but if the temperature coefficient of RS is known, it is possible to cancel the temperature dependence by combining it with a bandgap reference circuit, etc. The gm of the differential circuit can be compensated for and the gm of the differential circuit can be kept constant.

[0007]

However, if the load resistance of the differential amplifier hardly changes with temperature, the product of the load resistance and the tail current becomes the output amplitude voltage, so the output amplitude at saturation becomes larger at higher temperatures. Will end up. When the saturated output changes, the full-wave rectified output also changes, so RS changes due to temperature changes.
SI output also fluctuates. As a result, in FIG. 9, when the low temperature is represented by a solid line, the characteristic shown by the alternate long and short dash line is obtained at a high temperature, and there is a problem that the characteristic at a low temperature is distant particularly from a large signal input. As a solution to this, there is a method of correcting the output of RSSI by a calculator by using the characteristic of a temperature dependent element such as a thermistor externally.
Since external parts are required, the device cannot be integrated into one chip, which causes problems in cost and size reduction. An object of the present invention is to solve the above-mentioned problems of the prior art, and firstly, to provide an RSSI output that faithfully reproduces the input signal strength even if the temperature changes. Secondly, this can be achieved without using external parts.

[0008]

In order to achieve the above object, according to the present invention, a plurality of cascaded saturation amplifiers and output signals of the respective saturation amplifiers provided at the output of each saturation amplifier are provided. A rectifying / smoothing means for outputting a DC voltage or a DC current proportional to the strength, and an adding circuit for adding the output signals of the respective rectifying / smoothing means and outputting a signal strength detection signal,
In the signal strength detection circuit having
A first gain control terminal to which a first control signal for controlling gain so that the gain of the saturation amplifier does not change due to temperature is applied, and output from the rectifying / smoothing means attached to the output section of the saturation amplifier. And a second gain control terminal to which a second control signal for controlling the gain so that the saturation amplitude value of the saturation amplifier does not exceed a certain amplitude, which is generated from the direct current signal, is applied. A signal strength detection circuit is provided.

In order to achieve the above-mentioned object, according to the present invention, a plurality of cascaded saturation amplifiers, a first stage saturation amplifier input section, and a first stage saturation amplifier output section are respectively provided. Rectifying / smoothing means for outputting a DC voltage or DC current proportional to the strength of the input signal of each saturation amplifier and the output signal of each saturation amplifier, and the output signal of each rectifying / smoothing means are added to output a signal strength detection signal. And a first gain control terminal to which a first control signal for gain control is applied to each saturation amplifier so that the gain of the saturation amplifier does not change due to temperature, Gain control is performed such that the saturation amplitude value of the saturation amplifier generated from the DC signal output from the rectifying / smoothing means attached to the input portion of the saturation amplifier does not exceed a certain amplitude. The signal strength detection circuit, characterized in that the control signal has a second gain control terminal which is applied, the, is provided.

In order to achieve the above object, according to the present invention, a plurality of cascaded saturation amplifiers, which are controlled so that the gain does not change with temperature, and an output section of each saturation amplifier are provided. A rectifying / smoothing means for outputting a DC voltage or a DC current proportional to the intensity of the output signal of each saturation amplifier provided, and an adder circuit for adding the output signals of the rectifying / smoothing means and outputting a strength sum signal, A signal strength detection circuit having a division circuit for calculating a ratio between a value proportional to the maximum output amplitude of the saturation amplifier at a certain temperature and a value proportional to the maximum output amplitude of the saturation amplifier at a reference temperature; A signal strength detection circuit, further comprising: a multiplication circuit that multiplies the intensity sum signal by the ratio calculated by the division circuit and outputs a signal strength detection signal.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing a first embodiment of the present invention, showing an example in which saturation amplifiers are connected in four stages. That is, four-stage saturation amplifier 1
01 to 104 are connected in cascade, the input signal IN is input from the input terminal, and the output signal OUT is output from the output terminal. The output of the saturation amplifier of each stage is full-wave rectified by the rectifiers 111 to 114,
Further smoothed by the low pass filters 121 to 124, the RSSI
In addition to being input to the adder circuit 141 to obtain the total output, the amplitude control bias generation units 131 to 134 provided for each stage are also provided.
Entered in. Each saturation amplifier has two gain control terminals Vc
1, Vc2 are provided. A bias signal generated by the constant gm bias generation unit 151 is input to the gain control terminal Vc1 so that the saturation amplifiers 101 to 104 in each stage amplify with a constant amplification degree regardless of temperature. The output of the rectifier indicating the DC signal strength of the saturation amplifier is the amplitude control bias generators 131 to 134.
After being converted into a bias signal at, it is input to the gain control terminal Vc2. This signal drives each amplifier circuit so that its output does not exceed a certain amplitude value.

FIG. 2 is a circuit diagram showing a specific circuit configuration of the first embodiment of the present invention (however, since the circuit configurations of the respective stages are the same, the circuits of the second and third stages are the same). Is omitted, and the same applies to FIG. 6), and FIG.
It is a circuit diagram showing a circuit configuration for one stage of a cascade connection circuit. As shown in FIG. 2, the saturation amplifiers 201-204 are connected in cascade. The output signals of the saturation amplifiers 201 to 204 are input to the rectification / smoothing units 211 to 214 provided for each stage and used to calculate the RSSI output. The RSSI output of each of the rectifying / smoothing units 211 to 214 is input to the adder OP5 and used to form the RSSI total output. In addition, the RSSI output calculated by the rectifying / smoothing units 211 to 214 is the comparator.
Returned to the saturation amplifiers 201 to 204 via OP4
Used for amplitude control of ~ 204. As shown in Figure 3,
Each stage is composed of a saturation amplifier 301 having FETs M1 and M2 forming a differential pair and a rectifying / smoothing unit 311 for calculating the RSSI output of each stage. Between FET M1 and M2 and load resistance R1 and R2, a pair of FET M3 and M4 for switching the current of this differential pair, and FET
A pair of M5 and M6 is provided. A constant gm bias is applied to the gate of the FET that supplies tail current to the differential pair of FETs M1 and M2. The circuit shown in FIG. 4 is used as the circuit for generating the constant gm bias. Input signal In is input
Input bias is applied to the gates of FETs M1 and M2 pM
A bias voltage formed by the OSFET and the resistor is applied. The gates of the FETs M4 and M5 are input with a bias determined by the voltage division ratio of the resistance, and the gates of the FETs M3 and M6 are input with the bias determined by the parallel circuit of the resistance and the FET M7 and the voltage division ratio of the resistance. Therefore, FET M3 and M5 are
1 forms a differential pair using the tail current supply transistor, and FETs M4 and M6 form a differential pair using the FET M2 as the tail current supply transistor. The principle of gain control of this saturation amplifier will be briefly described. For example, M4 on the M3 (M6) side
If a sufficiently high gate voltage is applied from the (M5) side, M3 turns on, M4 turns off (M6 turns on, M5 turns off at the same time), and the FETs M1 and M2 that make up the differential pair directly Since it is equivalent to connecting to the loads R1 and R2 of, the condition for maximum gain is obtained. When the gate potential of M3 (M6) decreases, current also starts flowing in M4 (M5), the current flowing in M1 is shunted to the load R2 side, and the current flowing in M2 is shunted to the load R1 side. The gain decreases. When the gate potential of M3 (M6) further decreases and becomes equal to the gate potential of M4 (M5), half of each current of FETs M1 and M2 that make up the differential pair flows to loads R1 and R2. , And the signals that cancel each other out of phase are no longer output (amplification factor
0). That is, it is possible to control the gain of this saturation amplifier by adjusting the gate potentials of M3 (M6) and M4 (M5). In the present embodiment, this gain control function is used to limit the amplitude.

The rectifying / smoothing unit 311 includes a differential pair of FETs, respectively.
A rectifier F1 having a FET that supplies a tail current to the differential pair FET and a reference potential generator D1 are provided. The FET that supplies the tail current is driven with a constant current by applying a constant current bias that does not depend on the temperature to the gate. A bias voltage is applied to the gates of the two differential pair FETs, which input voltage is determined by the voltage dividing ratio between the pMOSFET and the resistor whose input bias is input to the gates. The output signal of the saturation amplifier 301 is detected by the potential of the source couple of the differential pair of the rectifier F1. The reference potential generation unit D1 having the same circuit configuration as the rectification unit F1 is in DC steady operation, and the output signal of the saturation amplifier is obtained by detecting the difference between the DC potential of the source couple and the output of the rectification unit F1 (PE Allen, D.
R. Holberg, "CMOS Analog Circuit Design", p.
pp. 616-619). In the circuit of the present embodiment, the active filter OP that detects the difference and drops the high frequency component
1 is used to obtain the smoothed rectified output signal. The smoothed rectified output is inverted by the inverting amplifier OP2, and RSS
Used as I output. The output signal of the inverting amplifier OP2 is further subtracted by the subtraction circuit OP3 for the offset of the output of the rectification unit F1, and is compared with the reference reference voltage by the comparator OP4.

The maximum output amplitude Vo of the saturation amplifier is given by Vo = I × R (I is the tail current of the differential circuit, and R is the load resistance of the differential circuit). On the other hand, in a differential amplifier in which a tail current is supplied by a constant gm bias, the tail current is increased in order to compensate for the gm of the MOSFET, which deteriorates as the temperature rises. Therefore, the minimum output amplitude is obtained at the lowest temperature used,
The maximum output amplitude increases with temperature. Therefore, when limiting the amplitude in order to reduce the temperature dependence of the amplitude,
It is desirable to reference the minimum amplitude at the lowest operating temperature. In the rectifying / smoothing unit 311, the rectified output indicated by the saturation amplifier at the lowest operating temperature is used as a reference reference voltage in the comparator OP4
When the saturation amplifier is controlled by using OP4 so that the output of the subtraction circuit OP3 becomes the reference reference voltage, the amplitude is controlled so as not to exceed the amplitude value of the minimum operating temperature at the temperature higher than the minimum operating temperature. That is, when the output of the subtraction circuit OP3 is equal to or lower than the reference reference voltage, "1" is output from the comparator OP4 to turn on the FET M7 and turn on M3 and M6.
4, M5 is off, the saturation amplifier operates at maximum gain, and
Driven by m bias. When the output of OP3 becomes higher than the reference voltage, the output of comparator OP4 becomes “0”, FET M7 is turned off, M4 and M5 are turned on with M3 and M6 turned on, and the gain of the saturation amplifier decreases. The increase in amplitude is suppressed. By using a bandgap reference circuit as the reference reference voltage, it is easy to generate a reference voltage that does not depend on the temperature or the power supply voltage.

FIG. 5 (b) shows that the temperature of the conventional circuit is 25.degree.
It is the simulation result of RSSI at ℃, and there is a big difference between both. On the other hand, FIG. 5 (a) shows a simulation result of RSSI of a circuit in which the circuit shown in FIG. The solid line, dotted line, and broken line show the results under the conditions of temperature of -20 ° C, 80 ° C, power supply voltage of 3 V, and -20 ° C, 3.3 V, respectively. It can be seen that the effects of voltage fluctuations have been sufficiently removed.

FIG. 6 is a circuit diagram showing a second embodiment of the present invention. In FIG. 6, the same parts as those of the first embodiment shown in FIG. 2 are designated by common reference numerals in the last two digits, and therefore, duplicated description will be omitted. In the present embodiment, the differential circuit of the saturation amplifier is configured.
FE driven by a constant gm bias to the common source of FET M1 and M2
T and a FET driven by a constant current bias are connected in parallel. The gate of the FET that supplies this tail current is the FET M to which the output signal of the comparator OP7 is input.
8, shunted by M9.

The comparator OP7 is provided with two output terminals. When the output of the subtraction circuit (OP3) is equal to or lower than the reference reference voltage, one of the output terminals (the terminal on the right side of the figure) is " 1 "and" 0 "are output from the other output terminal. When the reference reference voltage is exceeded, "0" is output from one output terminal (the terminal on the right side of the figure) and "1" is output from the other output terminal. Now, assuming that the amplitude of the saturation amplifier is small and the output of the subtraction circuit (OP3) is equal to or lower than the reference reference voltage, FET M8 is turned on and FET M9 is turned off. M2 is driven in a constant gm state (maximum gain state) by being supplied with a tail current by a constant gm bias driven FET. When the output of the subtraction circuit (OP3) becomes higher than the reference voltage, the comparator O
The output of P7 is inverted, FET M8 is turned off, FET M9 is turned on, and FETs M1 and M2 that make up the differential circuit of the saturation amplifier are supplied with tail current by the FET driven by constant current bias. Therefore, the gain of the saturation amplifier is reduced and the increase of the amplitude is suppressed.

FIG. 7 is a block diagram showing a third embodiment of the present invention. In FIG. 7, the same parts as the parts of the first embodiment shown in FIG. 1 are designated by common reference numerals in the last two digits, and therefore, duplicated description will be omitted.
The difference from the first embodiment shown in FIG. 1 of the present embodiment is that the input signal IN and the signal detected by the rectification / smoothing unit of the output of the saturation amplifier are used for gain control of the next-stage saturation amplifier. Used. Specific circuit configurations such as a saturation amplifier and a rectifying / smoothing unit are the same as those in the first embodiment shown in FIGS. 2 and 3, and when the amplitude value is equal to or less than a certain value, the first embodiment is used. Similar to the configuration, the saturation amplifier is biased by a bias method in which the gain does not depend on temperature, and when the amplitude value exceeds a specified value, a limiter is applied and the RSSI output does not affect temperature. In this embodiment, the circuit configurations of the saturation amplifier and the rectifying / smoothing unit are the same as those of the first embodiment, but instead of this, the circuit configurations of the second to third embodiments are adopted. You may do it.

FIG. 8 is a block diagram showing a fourth embodiment of the present invention. In FIG. 8, portions equivalent to those of the first embodiment shown in FIG. 1 are denoted by reference numerals having the same last two digits, and therefore, duplicated description will be omitted.
In the method according to the present embodiment, each saturation amplifier is biased so that the gain is constant regardless of temperature, and the total output of RSSI is corrected from the bias current value that changes depending on the temperature. Where the saturation amplifier 80
Assume 1-804 as a constant gm biased saturated amplifier shown in FIG. The tail current bias current at the lowest temperature used is I0. At higher temperatures, the tail bias current is used to compensate for the gain reduction of the differential saturation amplifier.
I1 will be greater than I0. The saturation output Vo is R0 and the tail bias current is I, and Vo = RI, so that the saturation output Vo is proportional to the tail current. Therefore, at the temperature where the tail current is I1, the saturation voltage is I1 / I0 times as high as when the tail current is I0. Therefore, I
The temperature dependence of RSSI can be compensated by multiplying the coefficient of 0 / I1. Specifically, the constant gm bias generator 85 of FIG.
In 1, the above I1 is generated, in the reference temperature bias generating unit 861, I0 is generated, and the division operation circuit unit 871 calculates I0 / I1.
Then, the multiplication operation circuit unit 881 calculates the corrected RSSI total output by multiplying the sum signal of the RSSI outputs output from the adder 841 by I0 / I1. The current I0 at the reference temperature bias can be easily generated by a bias circuit that does not depend on the power supply voltage and the temperature, such as a bandgap reference circuit. Further, the arithmetic circuit section can be configured by an analog circuit, or can be A / D converted and digitally processed.

The preferred embodiments have been described above, but the present invention is not limited to these embodiments, and appropriate modifications can be made without departing from the gist of the present invention. For example, the FET used
The conductivity types may all be reversed. Further, the present invention can be applied to a saturation amplifier using a bipolar transistor. Further, the number of saturation amplifiers connected in cascade is not limited to that of the embodiment, and may be more or less, or may be only one.

[0021]

As described above, the present invention drives a saturation amplifier with a constant gm bias and limits the amplitude of the saturation amplifier based on the amplitude of the saturation amplifier detected by the rectifying / smoothing unit. Therefore, according to the present invention, it is possible to accurately detect the signal strength of the received signal without being affected by the temperature change. In addition, since all can be configured with semiconductor devices, they can be integrated into one chip and there is no need to use external parts.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is a circuit diagram of a circuit for one stage of the circuit shown in FIG.

FIG. 4 is a circuit diagram of a constant gm bias circuit and a constant gm biased differential amplifier.

FIG. 5 is a simulation result [(a)] of the circuit according to the first embodiment of the present invention and a simulation result [(b)] of the conventional circuit.

FIG. 6 is a circuit diagram showing a second embodiment of the present invention.

FIG. 7 is a block diagram showing a third embodiment of the present invention.

FIG. 8 is a block diagram showing a fourth embodiment of the present invention.

FIG. 9 is a diagram for qualitatively explaining characteristics of a signal strength detection circuit.

FIG. 10 is a block diagram of a conventional example.

FIG. 11 is a partial circuit diagram of another conventional example.

[Explanation of symbols]

101-104, 201-204, 301, 401, 601-604, 701-704,
801 to 804, 1001 to 1004 Saturation amplifier 111 to 114, 711 to 715, 811 to 814, 1011 to 1014 Rectifier 121 to 124, 721 to 725, 821 to 824, 1021 to 1024 Low pass filter 131 to 134, 731 to 734 Amplitude Control bias generator 141, 741, 841, 1041 Adder circuit 151, 751, 851, 1051 Constant gm bias generator 211-214, 311, 611-614 Rectifying / smoothing unit 411 Constant gm bias generator 861 Reference temperature bias generator Section 871 division calculation circuit 881 multiplication calculation circuit 1101 logarithmic amplification section 1102 amplitude detection section 1103 constant current source proportional to absolute temperature F1 rectification section D1 reference potential generation section IN input signal OUT output signal OP1 active filter OP2 inverting amplifier OP3 subtraction circuit OP4 , OP6, OP7 Comparator OP5 Adder Vc1, Vc2 Gain control pin

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5J090 AA01 CA02 CA91 CN01 FA10                       FA17 FN06 FN10 HA10 HA17                       HA19 HA25 HA29 KA00 KA01                       KA02 KA04 KA05 KA06 KA09                       KA11 KA12 KA17 KA26 KA42                       KA51 MA08 MA11 MA21 SA15                       TA01 TA02                 5J100 JA01 LA00 LA02 QA01 QA04                       SA01 SA02 SA03                 5J500 AA01 AC02 AC91 AF10 AF17                       AH10 AH17 AH19 AH25 AH29                       AK00 AK01 AK02 AK04 AK05                       AK06 AK09 AK11 AK12 AK17                       AK26 AK42 AK51 AM08 AM11                       AM21 AS15 AT01 AT02 NC01                       NF06 NF10                 5K061 CC25 DD04 JJ02

Claims (11)

[Claims] 1. A signal strength detection circuit having a saturation amplifier and a rectifying / smoothing means which is provided at an output portion of the saturation amplifier and outputs a DC voltage or a DC current proportional to the strength of an output signal of the saturation amplifier. In the saturation amplifier, a first gain control terminal to which a first control signal for controlling gain so that the gain of the saturation amplifier does not change depending on temperature is applied, and a DC signal output from the rectifying / smoothing means. And a second gain control terminal to which a second control signal for controlling gain so that the saturation amplitude value of the saturation amplifier does not exceed a certain amplitude is applied. Strength detection circuit. 2. A plurality of cascaded saturation amplifiers, and a rectifying / smoothing means for outputting a DC voltage or a DC current proportional to the intensity of the output signal of each saturation amplifier, which is provided in the output section of each saturation amplifier. In a signal strength detection circuit having an adder circuit for adding the output signals of the respective rectifying / smoothing means and outputting a signal strength detection signal, each saturation amplifier has a gain control so that the gain of the saturation amplifier does not change with temperature. The first gain control terminal to which the first control signal is applied, and the saturation amplitude of the saturation amplifier generated from the DC signal output from the rectifying / smoothing means attached to the output section of the saturation amplifier. And a second gain control terminal to which a second control signal for controlling the gain so that the value does not exceed a certain amplitude is applied. 3. A saturation amplifier, and a DC voltage or a DC voltage proportional to the intensities of the input signal of the saturation amplifier and the output signal of the saturation amplifier, which are provided in the input section of the saturation amplifier and the output section of the saturation amplifier, respectively. A signal strength detection circuit having a rectifying / smoothing means for outputting a current and an adding circuit for adding a signal output from each rectifying / smoothing means to output a signal strength detection signal, wherein the saturation amplifier is From a first gain control terminal to which a first control signal for gain control is applied so that the gain of the amplifier does not change, and a DC signal output from the rectifying / smoothing means attached to the input part of the saturation amplifier. A second gain control terminal to which a second control signal is applied, which is generated so that the saturation amplitude value of the saturation amplifier does not exceed a certain amplitude. The signal strength detection circuit. 4. A plurality of cascaded saturation amplifiers, and an input signal of the first stage saturation amplifier and an output signal of each saturation amplifier, which are respectively provided in the input section of the first stage saturation amplifier and the output section of each saturation amplifier. A signal strength detection circuit having a rectifying / smoothing means for outputting a DC voltage or a DC current proportional to the strength, and an adding circuit for adding the output signals of the respective rectifying / smoothing means to output a signal strength detection signal, The saturation amplifier has a first gain control terminal to which a first control signal for controlling gain so that the gain of the saturation amplifier does not change due to temperature is applied, and the rectification / smoothing connected to the input part of the saturation amplifier. A second gain control terminal, to which a second control signal, which is generated from the DC signal output from the means, is applied to control the gain so that the saturation amplitude value of the saturation amplifier does not exceed a certain amplitude; The signal strength detection circuit, characterized in that it has. 5. The reference value for determining the maximum value of the saturation amplitude value of the saturation amplifier is a reference value determined from the saturation amplitude value of the saturation amplifier at the lowest temperature of the device for detecting the signal strength. Item 5. The signal strength detection circuit according to any one of items 1 to 4. 6. The second control signal is output by a comparator to which the DC signal output from the rectifying / smoothing means used to form the second control signal and the reference value are input. The signal strength detection circuit according to claim 5, wherein the signal strength detection circuit is formed. 7. The saturation amplifier includes a first differential circuit, and the first control signal is input to a transistor that supplies a tail current of the first differential circuit to supply the tail current. 7. The signal strength detection circuit according to claim 1, wherein the transistor is constantly gm biased. 8. Each transistor of the first differential circuit is connected to a second differential circuit using the transistor as a tail current supply transistor, and one input terminal of the second differential circuit. The signal strength detection circuit according to claim 7, wherein a constant voltage is input to the second input signal, and the second control signal is input to the other input terminal. 9. The saturation amplifier includes a first transistor to which a constant gm bias signal which is the first control signal is input and a second transistor to which a constant current bias signal is input, each being a tail current supply transistor. 7. A differential circuit having the same in parallel is provided, and the first transistor and the second transistor are turned on / off based on the second control signal. The signal strength detection circuit according to any one of 1. 10. A plurality of cascaded saturation amplifiers, which are controlled so that their gain does not change with temperature, and proportional to the output signal strength of each saturation amplifier provided at the output of each saturation amplifier. A signal strength detection circuit having a rectifying / smoothing means for outputting a DC voltage or a DC current, and an adding circuit for adding an output signal of each rectifying / smoothing means to output a strength sum signal, At a division circuit for calculating the ratio of the value proportional to the maximum output amplitude at the reference temperature of the saturation amplifier, and the intensity sum signal multiplied by the ratio calculated by the division circuit. And a multiplication circuit that outputs a signal strength detection signal. 11. The saturation amplifier is a differential circuit in which gain control is performed by a tail current, and a transistor for supplying the tail current is constantly gm-biased. Signal strength detection circuit.