JP2003163355A - Thin-film semiconductor device and electronic apparatus - Google Patents
Thin-film semiconductor device and electronic apparatusInfo
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- JP2003163355A JP2003163355A JP2002245869A JP2002245869A JP2003163355A JP 2003163355 A JP2003163355 A JP 2003163355A JP 2002245869 A JP2002245869 A JP 2002245869A JP 2002245869 A JP2002245869 A JP 2002245869A JP 2003163355 A JP2003163355 A JP 2003163355A
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- thin film
- tantalum
- manufacturing
- hydrogen
- semiconductor device
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- Liquid Crystal (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明はアクティブマトリッ
クス液晶ディスプレイ等に適応される薄膜半導体装置及
びその製造方法並びに絶縁性物質上に形成された電気配
線を有する電子機器及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device adapted to an active matrix liquid crystal display and the like, a manufacturing method thereof, an electronic device having electric wiring formed on an insulating material, and a manufacturing method thereof.
【0002】[0002]
【従来の技術】近年、液晶ディスプレイ(LCD)の大
画面化、高解像度化に伴い、その駆動方式は単純マトリ
ックス方式からアクティブマトリックス方式へ移行し、
大容量の情報を表示出来るように成りつつ有る。アクテ
ィブマトリックス方式は数十万を越える画素を有する液
晶ディスプレイが可能で有り、各画素毎にスイッチング
トランジスタを形成するもので有る。各種液晶ディスプ
レイの基板としては、透過型ディスプレイを可能ならし
める溶融石英板やガラスなどの透明絶縁基板が使用され
ている。薄膜トランジスタ(TFT)の能動層として
は、通常アモルファスシリコンや多結晶シリコンなどの
半導体膜が用いられるが、駆動回路まで一体化して薄膜
トランジスタで形成しようとする場合には動作速度の速
い多結晶シリコンが有利である。多結晶シリコン膜を能
動層とする場合は溶融石英板を基板として用い、通常は
工程最高温度が1000℃を越える高温プロセスと呼ば
れる製造方法にてTFTが作成されている。一方アモル
ファスシリコン膜を能動層とする場合には通常のガラス
基板が用いられている。LCDの表示画面の拡大化や低
価格化を進める場合にはこの様に絶縁基板として安価な
通常ガラスを使用するのが必要不可欠で有る。しかしな
がら、前述の如くアモルファスシリコン膜は電気特性が
多結晶シリコン膜に比べ著しく劣り動作速度が遅い等の
問題を内有している。又、高温プロセスの多結晶シリコ
ンTFTは溶融石英板を用いて居る為、LCDの大型化
や低価格化が困難との問題を有して居る。結局、通常の
ガラス基板上に多結晶シリコン膜等の半導体膜を能動層
とする薄膜半導体装置を作成する技術が強く求められて
いるのである。然るに量産性に富む大型の通常ガラス基
板を用いる際には、基板の変形を避けるべく工程最高温
度を約570℃程度以下とする大きな制約が有る。即ち
斯様な制約下にて液晶ディスプレイを動作し得る薄膜ト
ランジスタと、駆動回路を高速作動し得る薄膜トランジ
スタの能動層を形成する技術が望まれて居る。これらは
現在低温プロセスpoly−Si TFTと称されてい
る。2. Description of the Related Art In recent years, with the increase in screen size and resolution of liquid crystal displays (LCDs), the drive system has changed from a simple matrix system to an active matrix system,
It is becoming possible to display a large amount of information. The active matrix method enables a liquid crystal display having more than several hundred thousand pixels, and forms a switching transistor for each pixel. As a substrate for various liquid crystal displays, a transparent insulating substrate such as a fused silica plate or glass that enables a transmissive display is used. A semiconductor film such as amorphous silicon or polycrystalline silicon is usually used as an active layer of a thin film transistor (TFT), but polycrystalline silicon, which has a high operating speed, is advantageous when a thin film transistor is to be integrated with a driving circuit. Is. When a polycrystalline silicon film is used as an active layer, a fused silica plate is used as a substrate, and a TFT is usually manufactured by a manufacturing method called a high temperature process in which the maximum process temperature exceeds 1000 ° C. On the other hand, when an amorphous silicon film is used as an active layer, a normal glass substrate is used. In order to expand the display screen of the LCD and reduce the price, it is essential to use inexpensive ordinary glass as the insulating substrate. However, as described above, the amorphous silicon film has a problem that the electrical characteristics are significantly inferior to the polycrystalline silicon film and the operation speed is slow. Further, since the polycrystalline silicon TFT in the high temperature process uses the fused quartz plate, there is a problem that it is difficult to increase the size and cost of the LCD. After all, there is a strong demand for a technique for producing a thin film semiconductor device having a semiconductor film such as a polycrystalline silicon film as an active layer on a normal glass substrate. However, when using a large-sized ordinary glass substrate that is highly mass-producible, there is a great restriction that the maximum process temperature is about 570 ° C. or less in order to avoid substrate deformation. That is, there is a demand for a technique of forming a thin film transistor capable of operating a liquid crystal display under such restrictions and an active layer of the thin film transistor capable of operating a driving circuit at high speed. These are currently referred to as low temperature process poly-Si TFTs.
【0003】従来の低温プロセスpoly−Si TF
TはSID(Society for Informa
tion Display)’93ダイジェストP.3
87(1993)に示されている。それによると、まず
LPCVD法で原料気体としてモノシランを(Si
H4)を用い、堆積温度550℃にて50nmのアモル
ファスシリコン(a−Si)膜を堆積し、このa−Si
膜にレ−ザ−照射を施し、a−Si膜をpoly−Si
膜へと改質する。poly−Si膜のパターニング後、
ゲート絶縁膜で有るSiO2膜をECR−PECVD法
で基板温度を100℃として堆積する。ゲート絶縁膜上
にタンタル(Ta)にてゲート電極を形成した後、ゲー
ト電極をマスクとしてドナー又はアクセプター不純物を
シリコン膜にイオン注入してトランジスタのソース・ド
レインを自己整合的(セルフ・アライン)に形成する。
この時イオン注入はイオン・ドーピング法と呼ばれる質
量非分離型の注入装置を用い、水素希釈されたフォスフ
ィン(PH3)やジボラン(B2H6)を原料気体として
用いている。注入イオンの活性化は300℃で有る。そ
の後層間絶縁膜を堆積し、インジウム錫酸化物(IT
O)やアルミニウム(Al)で電極や配線を作成し、薄
膜半導体装置は完成する。Conventional low temperature process poly-Si TF
T is SID (Society for Information)
Diction P.t. Three
87 (1993). According to it, first, by the LPCVD method, monosilane (Si
H 4 ) is used to deposit a 50 nm amorphous silicon (a-Si) film at a deposition temperature of 550 ° C.
The film is irradiated with laser and the a-Si film is poly-Si.
Reform into a film. After patterning the poly-Si film,
A SiO 2 film, which is a gate insulating film, is deposited by ECR-PECVD at a substrate temperature of 100 ° C. After forming a gate electrode with tantalum (Ta) on the gate insulating film, donor or acceptor impurities are ion-implanted into the silicon film using the gate electrode as a mask to make the source / drain of the transistor self-aligned (self-aligned). Form.
At this time, ion implantation uses a mass non-separation type implanter called an ion doping method, and phosphine (PH 3 ) or diborane (B 2 H 6 ) diluted with hydrogen is used as a source gas. Activation of implanted ions is at 300 ° C. After that, an interlayer insulating film is deposited, and indium tin oxide (IT
The thin film semiconductor device is completed by forming electrodes and wiring with O) or aluminum (Al).
【0004】[0004]
【発明が解決しようとする課題】しかしながら、前述の
従来技術に則る低温プロセスpoly−Si TFTに
は次の様な問題が内在しており、これらが量産化の阻害
要因となっている。即ち、
課題1).ゲート電極及び走査配線に使用される導伝体
材料の抵抗値が高い。その為走査信号波形の鈍りが生
じ、各画素に設けられたスウィッチング用TFTの正常
動作が妨げられる。即ち液晶表示装置(LCD)を高精
細化や大型化を行い得ない。However, the following problems are inherent in the low temperature process poly-Si TFT according to the above-mentioned prior art, and these are obstacles to mass production. That is, Problem 1). The resistance value of the conductor material used for the gate electrode and the scanning wiring is high. Therefore, the waveform of the scanning signal becomes dull, which prevents the normal operation of the switching TFT provided in each pixel. That is, the liquid crystal display (LCD) cannot be made finer or larger.
【0005】課題2).ゲート電極に対してイオン注入
法に依りソース・ドレイン領域を自己整合させるセルフ
・アラインTFT(S/A TFT)を作成する場合、
ゲート電極には注入イオンをチャンネル領域と成る半導
体膜やその直上に設けられたゲート絶縁膜に進入させ得
ぬ阻止能力が求められる。しかしながらゲート電極が金
属で有ると或る確率を持って注入イオンが金属結晶格子
間をすり抜けて仕舞う。即ちゲート電極のイオン阻止能
力が劣っており、S/A TFTの安定的な生産を行い
得ない。Problem 2). When making a self-aligned TFT (S / A TFT) in which the source / drain regions are self-aligned with the gate electrode by the ion implantation method,
The gate electrode is required to have a blocking ability that prevents implanted ions from entering the semiconductor film which will be the channel region and the gate insulating film provided immediately above the semiconductor film. However, if the gate electrode is made of metal, the implanted ions pass through the metal crystal lattice with a certain probability and end up. That is, the ion blocking ability of the gate electrode is inferior, and stable production of S / A TFTs cannot be performed.
【0006】課題3).大型LCDに代表される長い配
線を伴う電子機器では配線材の内部ストレスや温度変化
に伴う熱伸縮により断線が発生し易い。この事情はS/
ATFTの走査線の様に配線が段差(S/A TFTの
場合は半導体膜の段差)を乗り越える必要が有る時によ
り深刻と化す。この為電子機器の製造歩留りが著しく低
下するとの問題が生ずる。Problem 3). In an electronic device with long wiring, which is represented by a large LCD, disconnection is likely to occur due to internal stress of the wiring material and thermal expansion and contraction due to temperature change. This situation is S /
This becomes more serious when it is necessary to overcome the step difference (step difference of the semiconductor film in the case of the S / ATFT) of the wiring like the scanning line of the ATFT. For this reason, there arises a problem that the manufacturing yield of electronic devices is significantly reduced.
【0007】そこで本発明は上述の様な諸課題の解決を
目指し、その目的は良好な薄膜半導体装置や電子機器を
現実的な簡便な手段で、安定的に製造する方法を提供す
る事にある。Therefore, the present invention aims to solve the above-mentioned various problems, and an object thereof is to provide a method for stably manufacturing a good thin film semiconductor device or an electronic device by a practical and simple means. .
【0008】[0008]
【課題を解決するための手段】本発明は絶縁性物質上に
島状に形成された半導体層と、該半導体層上に形成され
たゲート絶縁層と、該ゲート絶縁層上に形成されたゲー
ト電極とを具備する薄膜半導体装置に於いて、少なくと
も該ゲート電極の一部は水素を含有するα構造のタンタ
ルで有る事を特徴とする。According to the present invention, a semiconductor layer is formed on an insulating material in an island shape, a gate insulating layer is formed on the semiconductor layer, and a gate is formed on the gate insulating layer. A thin film semiconductor device including an electrode is characterized in that at least a part of the gate electrode is hydrogen-containing α-structure tantalum.
【0009】又本発明は絶縁性物質上に島状に形成され
た半導体層と、該半導体層上に形成されたゲート絶縁層
と、該ゲート絶縁層上に形成されたゲート電極とを具備
する薄膜半導体装置に於いて、該ゲート電極が窒素と水
素を含有するタンタルで有る事を特徴とする。Further, the present invention comprises a semiconductor layer formed in an island shape on an insulating material, a gate insulating layer formed on the semiconductor layer, and a gate electrode formed on the gate insulating layer. A thin film semiconductor device is characterized in that the gate electrode is tantalum containing nitrogen and hydrogen.
【0010】又本発明は絶縁性物質上に形成された薄膜
半導体装置の製造方法に於いて、少なくとも水素と窒素
とアルゴンを含有する雰囲気下にてスパッター堆積法に
よりタンタルを主成分とする薄膜を形成する工程を含む
事を特徴とする。The present invention also provides a method of manufacturing a thin film semiconductor device formed on an insulating material, wherein a thin film containing tantalum as a main component is formed by a sputter deposition method in an atmosphere containing at least hydrogen, nitrogen and argon. It is characterized by including a step of forming.
【0011】又本発明は下側導伝層とα構造タンタルを
主成分とする上側導伝層から成る導伝層を含む薄膜半導
体装置の製造方法に於いて、下側導伝層を形成する第一
工程と、少なくとも水素とアルゴンを含有する雰囲気下
にてスパッター堆積法によりα構造タンタルを主成分と
する薄膜を形成する第二工程とを含む事を特徴とする。Further, the present invention is a method for manufacturing a thin film semiconductor device including a lower conductive layer and a conductive layer composed of an upper conductive layer whose main component is α-structure tantalum, in which the lower conductive layer is formed. It is characterized by including a first step and a second step of forming a thin film containing α-structure tantalum as a main component by a sputter deposition method in an atmosphere containing at least hydrogen and argon.
【0012】又本発明は絶縁性物質上に形成された薄膜
半導体装置の製造方法に於いて、少なくとも窒素とアル
ゴンを含有する雰囲気下にてスパッター堆積法によりタ
ンタルを主成分とする薄膜を形成する第一工程と、該薄
膜に水素化処理を施す第二工程とを含む事を特徴とす
る。この時前記第二工程が水素イオンの注入工程で有る
事をも特徴とする。The present invention also relates to a method of manufacturing a thin film semiconductor device formed on an insulating material, wherein a thin film containing tantalum as a main component is formed by a sputter deposition method in an atmosphere containing at least nitrogen and argon. It is characterized by including a first step and a second step of subjecting the thin film to hydrogenation treatment. At this time, the second step is also a step of implanting hydrogen ions.
【0013】又本発明は絶縁性物質上に形成された薄膜
半導体装置の製造方法に於いて、α構造タンタルを主成
分とする薄膜を形成する第一工程と、該薄膜に水素化処
理を施す第二工程とを含む事を特徴とする。この時前記
第二工程が水素イオンの注入工程で有る事をも特徴とす
る。The present invention also relates to a method of manufacturing a thin film semiconductor device formed on an insulating material, wherein a first step of forming a thin film containing α-structure tantalum as a main component, and the thin film is subjected to hydrogenation treatment. It is characterized by including a second step. At this time, the second step is also a step of implanting hydrogen ions.
【0014】又本発明は絶縁性物質上に形成された配線
を備える電子機器に於いて、少なくとも該配線の一部は
水素を含有するα構造のタンタルで有る事を特徴とす
る。Further, the present invention is characterized in that in an electronic device provided with wiring formed on an insulating material, at least a part of the wiring is tantalum having an α structure containing hydrogen.
【0015】又本発明は絶縁性物質上に形成された配線
を備える電子機器に於いて、該配線が窒素と水素を含有
するタンタルで有る事を特徴とする。Further, the present invention is characterized in that in an electronic device provided with a wiring formed on an insulating material, the wiring is tantalum containing nitrogen and hydrogen.
【0016】又本発明は絶縁性物質上に形成された配線
を備える電子機器の製造方法に於いて、少なくとも水素
と窒素とアルゴンを含有する雰囲気下にてスパッター堆
積法によりタンタルを主成分とする薄膜を形成する工程
を含む事を特徴とする。Further, the present invention is a method of manufacturing an electronic device having wiring formed on an insulating material, wherein tantalum is the main component by a sputter deposition method in an atmosphere containing at least hydrogen, nitrogen and argon. It is characterized by including a step of forming a thin film.
【0017】又本発明は下側導伝層とα構造タンタルを
主成分とする上側導伝層から成る導伝層を含む電子機器
の製造方法に於いて、下側導伝層を形成する第一工程
と、少なくとも水素とアルゴンを含有する雰囲気下にて
スパッター堆積法によりα構造タンタルを主成分とする
薄膜を形成する第二工程とを含む事を特徴とする。The present invention also provides a method of manufacturing an electronic device including a lower conductive layer and an upper conductive layer having an α-structure tantalum as a main component, wherein the lower conductive layer is formed. It is characterized by including one step and a second step of forming a thin film containing α-structure tantalum as a main component by a sputter deposition method in an atmosphere containing at least hydrogen and argon.
【0018】又本発明は絶縁性物質上に形成された配線
を備える電子機器の製造方法に於いて、少なくとも窒素
とアルゴンを含有する雰囲気下にてスパッター堆積法に
よりタンタルを主成分とする薄膜を形成する第一工程
と、該薄膜に水素化処理を施す第二工程とを含む事を特
徴とする。この時前記第二工程が水素イオンの注入工程
で有る事をも特徴とする。The present invention also provides a method of manufacturing an electronic device having wiring formed on an insulating material, wherein a thin film containing tantalum as a main component is formed by a sputter deposition method in an atmosphere containing at least nitrogen and argon. It is characterized by including a first step of forming and a second step of subjecting the thin film to hydrogenation treatment. At this time, the second step is also a step of implanting hydrogen ions.
【0019】又本発明は絶縁性物質上に形成された電子
機器の製造方法に於いて、α構造タンタルを主成分とす
る薄膜を形成する第一工程と、該薄膜に水素化処理を施
す第二工程とを含む事を特徴とする。この時前記第二工
程が水素イオンの注入工程で有る事をも特徴とする。The present invention also relates to a method of manufacturing an electronic device formed on an insulating material, comprising a first step of forming a thin film containing α-structure tantalum as a main component, and a hydrogenation treatment of the thin film. It is characterized by including two steps. At this time, the second step is also a step of implanting hydrogen ions.
【0020】[0020]
【発明の実施の形態】以下図面を参照しながら本発明の
基礎原理及び作用を説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The basic principle and operation of the present invention will be described below with reference to the drawings.
【0021】(第1章、本願発明の電子機器とその製造
方法)本願発明の電子機器は絶縁性物質上に形成された
電気伝導性配線を備える物で有る。これらの電子機器と
しては例えば薄膜半導体装置(TFT)や金属−絶縁体
−金属型非線形素子(MIM)、太陽電池、或いは半導
体装置(LSI)やプリント配線基板などが上げられ
る。この電気伝導性配線の少なくとも一部分は水素を含
有するα構造のタンタル(Ta)が用いられて居る。α
構造のタンタルは立方晶の結晶系をなし、その結晶構造
は体心立方(bcc)で有る。又このα構造タンタルの
比抵抗は凡20μΩcm程度から60μΩcm程度で有る。
こうしたα構造タンタルはα構造タンタル単体の膜中に
水素を含んで居る場合の他、膜中に水素と共に少量の窒
素を含んで居る場合や、導伝層が下側導伝層とその直上
に形成されてる上側導伝層から成り、その上側導伝層が
水素を含むα構造タンタルを主成分として居る場合など
が有る。いずれの場合にせよ主成分はタンタルで有る。
下側導伝層の直上にα構造タンタルを主成分とする上側
導伝層を形成する場合、下側導伝層は20nm程度から
200nm程度の薄いニオブ(Nb)やタングステン
(W)、窒化タンタル(TaN)等から成る。これらの
材質の特徴は上側導伝層のタンタルをα構造化させ得る
導伝材料という点に認められる。(Chapter 1, Electronic Device of the Present Invention and Manufacturing Method Thereof) The electronic device of the present invention comprises an electrically conductive wiring formed on an insulating material. Examples of these electronic devices include thin film semiconductor devices (TFT), metal-insulator-metal nonlinear elements (MIM), solar cells, semiconductor devices (LSI), and printed wiring boards. At least a part of this electrically conductive wiring uses tantalum (Ta) having an α structure containing hydrogen. α
Structural tantalum has a cubic crystal system, and its crystal structure is body-centered cubic (bcc). The specific resistance of this α-structure tantalum is about 20 μΩcm to 60 μΩcm.
Such α-structure tantalum contains hydrogen in the film of α-structure tantalum simple substance, contains a small amount of nitrogen together with hydrogen in the film, and the conduction layer is located on the lower conduction layer and directly above it. In some cases, the upper conductive layer is formed, and the upper conductive layer mainly contains α-structure tantalum containing hydrogen. In any case, the main component is tantalum.
When the upper conductive layer containing tantalum as a main component is formed directly on the lower conductive layer, the lower conductive layer is made of thin niobium (Nb), tungsten (W), tantalum nitride having a thickness of about 20 nm to 200 nm. (TaN) and the like. The characteristic of these materials is recognized in that it is a conductive material capable of making the tantalum of the upper conductive layer into an α structure.
【0022】さて従来のα構造タンタル(特に窒素を含
有したα構造タンタル)はスッパター法等のPVD法に
て堆積形成すると内部応力が非常に強いのが一般で有
る。然るに本願発明のα構造タンタルは水素を微量含有
して居る為、内部応力は著しく緩和されて居る。タンタ
ル薄膜中に於ける水素含有量は10atm ppm(1
atm ppmはタンタル原子106個に対して水素原
子1個)程度から5000atm ppm程度で有る。
水素含有量が5000atm ppm程度よりも遥かに
大きいとタンタルは脆性を呈して絶縁性物質で被われた
基板から剥離したり、或いは断線を生じて仕舞うが、5
000atm ppm程度以下で有れば内部応力は充分
小さく成り且つα構造タンタルは延性を有する様に成
る。即ち基板との熱膨張係数が著しく違った系に於いて
もその相違に起因するストレスや熱伸縮に対する耐性が
増するので有る。反対に水素含有量が10atm pp
m程度以下との極微量で有ると水素含有の効果は現れ
ず、従来のα構造タンタルと同様強い内部応力を有して
仕舞う。結局本願発明の電子機器で用いられる水素含有
α構造タンタルは従来のβ構造タンタルに比較して10
分の1程度から4分の1程度の低い比抵抗を有し、且つ
内部応力も充分緩和され、膜は延性を呈して居るので有
る。斯くした特典はタンタル薄膜が形成される基板がガ
ラスやプラスチックと云った熱膨張係数が金属と大きく
異なって居る物質で有ったり、或いは基板の変形や歪み
が容易に発生する様な物質で有る時に取り分け明瞭に認
められる。Generally, conventional α-structure tantalum (particularly nitrogen-containing α-structure tantalum) has very strong internal stress when deposited and formed by a PVD method such as a sputter method. However, since the α-structure tantalum of the present invention contains a small amount of hydrogen, the internal stress is remarkably relaxed. The hydrogen content in the tantalum thin film is 10 atm ppm (1
The atm ppm is from about 1 hydrogen atom to 10 6 tantalum atoms) to about 5000 atm ppm.
When the hydrogen content is much higher than about 5000 atm ppm, tantalum exhibits brittleness and peels off from the substrate covered with the insulating material, or the wire breaks.
If it is about 000 atm ppm or less, the internal stress becomes sufficiently small and the α-structure tantalum becomes ductile. That is, even in a system in which the coefficient of thermal expansion is significantly different from that of the substrate, the resistance to stress and thermal expansion and contraction due to the difference is increased. On the contrary, the hydrogen content is 10 atm pp
If it is a very small amount of about m or less, the effect of hydrogen content does not appear, and it has a strong internal stress like conventional α-structure tantalum and ends up. After all, the hydrogen-containing α-structure tantalum used in the electronic device of the present invention is 10 times as compared with the conventional β-structure tantalum.
It has a low specific resistance of about 1/4 to 1/4, the internal stress is sufficiently relaxed, and the film exhibits ductility. Such a privilege is that the substrate on which the tantalum thin film is formed is a substance such as glass or plastic whose coefficient of thermal expansion is greatly different from that of a metal, or a substance which easily causes deformation or distortion of the substrate. It is sometimes clearly recognized.
【0023】斯様な本願発明の水素含有α構造タンタル
は以下の如き製造方法にて作成される。まず第一の製造
方法は少なくとも水素と窒素とアルゴンを含有する雰囲
気下にてスパッター堆積法によりタンタルを主成分とす
る薄膜を形成する物で有る。通常のスパッター法ではア
ルゴンを成膜室に導入してプラズマを立て、このアルゴ
ンプラズマを利用して薄膜を堆積して居た。これに対し
本願発明では主構成ガスのアルゴンは変わらぬものの、
更に少量の窒素と水素を添加してアルゴン窒素水素の混
合プラズマを立て、これを利用してタンタルを主成分と
する薄膜をスッパター堆積するので有る。アルゴン中の
窒素含有量は5.0%程度から8.5%程度が最適で有
る。この範囲内で成膜すると比抵抗が小さく且つ内部応
力も比較的弱いα構造タンタルが成膜される。これはス
ッパター堆積されたタンタル薄膜中にα構造の窒化タン
タル(TaN)領域が僅かに発生し、この窒化タンタル
領域を種として主成分タンタルがα構造化するからで有
る。窒化タンタルそれ自身はα構造で有るが、これは比
抵抗が大きくしかも内部応力が窮めて強い。それが為成
膜中の窒素含有量が高すぎるとタンタル薄膜中に於ける
窒化タンタルの割合が増大し、その結果堆積薄膜は比抵
抗が大きく且つ内部応力も強く成って仕舞う。反対に窒
素含有量が少な過ぎるとタンタル薄膜はα構造化せずβ
構造で有る為比抵抗は200μΩcm程度と高く、更に窒
素が添加された分だけ内部応力も強く成って仕舞うので
有る。アルゴン中の水素含有量はタンタル薄膜の堆積速
度の応じて前述した10atm ppm程度から500
0atm ppm程度に成る様に調整する必要が有る
が、その標準的な値は0.1%程度から10%程度で有
る。結局アルゴン中の窒素含有量が5.0%程度から
8.5%程度の雰囲気下でタンタル薄膜を堆積すると比
較的内部応力が小さくα構造の低抵抗膜が成膜され、更
にこの膜に10atm ppm程度から5000atm
ppm程度の水素を添加すると内部応力は一段と減少
し、同時に膜の延性が増すので有る。Such hydrogen-containing α-structure tantalum of the present invention is prepared by the following manufacturing method. The first manufacturing method is to form a thin film containing tantalum as a main component by a sputter deposition method in an atmosphere containing at least hydrogen, nitrogen and argon. In the usual sputtering method, argon was introduced into the film forming chamber to generate plasma, and the thin film was deposited using this argon plasma. On the other hand, in the present invention, although the main constituent gas argon is unchanged,
Furthermore, a small amount of nitrogen and hydrogen are added to form a mixed plasma of argon nitrogen hydrogen, and this is used to sputter deposit a thin film containing tantalum as a main component. The optimum nitrogen content in argon is about 5.0% to 8.5%. When the film is formed within this range, α-structure tantalum having a small specific resistance and a relatively weak internal stress is formed. This is because a small amount of α-structure tantalum nitride (TaN) region is generated in the sputter-deposited tantalum thin film, and the main component tantalum is α-structured using this tantalum nitride region as a seed. Tantalum nitride itself has an α structure, but this has a large specific resistance and internal stress is tight and strong. Therefore, if the nitrogen content during film formation is too high, the proportion of tantalum nitride in the tantalum thin film increases, and as a result, the deposited thin film has a large specific resistance and strong internal stress. On the other hand, if the nitrogen content is too low, the tantalum thin film does not become α structured and β
Since it has a structure, the specific resistance is as high as about 200 μΩcm, and the internal stress also becomes stronger due to the addition of nitrogen, and the storage is completed. The hydrogen content in argon varies from about 10 atm ppm to 500 depending on the deposition rate of the tantalum thin film.
It is necessary to adjust it to be about 0 atm ppm, but its standard value is about 0.1% to 10%. After all, when a tantalum thin film is deposited in an atmosphere in which the nitrogen content in argon is about 5.0% to 8.5%, a low resistance film having an α structure with relatively small internal stress is formed, and 10 atm is further formed on this film. From about ppm to 5000 atm
When hydrogen of about ppm is added, the internal stress is further reduced, and at the same time, the ductility of the film is increased.
【0024】第二の製造方法は電子機器が下側導伝層と
その直上に形成されたα構造タンタルを主成分とする上
側導伝層から成る導伝層を含む際に適応される。まず第
一工程として下側導伝層を形成する。この導伝層は先に
述べた様に後に形成される上側導伝層のタンタルをα構
造化し得る材質で有る。この薄膜を通常のスッパター法
や蒸着法などのPVD法、或いはCVD法などで堆積す
る。第二工程では上側導伝層のタンタルをスッパター法
で形成するので第一工程の下側導伝層も同じスッパター
で堆積しておけば第一工程と第二工程を真空を破らず連
続で処理出来る。こうする事により単に生産性が向上す
るにのみならず、下側導伝層の結晶構造を上側導伝層が
容易に引き継ぐ事と成り、それが故上側タンタル薄膜が
確実にα構造化するので有る。引き続く第二工程では少
なくとも水素とアルゴンを含有する雰囲気下にてスパッ
ター堆積法によりα構造タンタルを主成分とする薄膜を
形成する。アルゴン中に於ける水素含有量は先と同様
に、成膜されたα構造タンタルが10atm ppm程
度から5000atm ppm程度の水素を含む様に調
整する。従ってその値は凡0.1%程度から10%程度
で有る。The second manufacturing method is applied when the electronic device includes a lower conductive layer and an upper conductive layer which is formed immediately above and has an α-structure tantalum as a main component. First, as a first step, a lower conductive layer is formed. This conductive layer is a material capable of α-structuring the tantalum of the upper conductive layer formed later as described above. This thin film is deposited by a PVD method such as an ordinary sputter method or vapor deposition method, or a CVD method. In the second step, tantalum in the upper conductive layer is formed by the sputter method, so if the lower conductive layer in the first step is also deposited with the same sputter, the first and second steps can be processed continuously without breaking the vacuum. I can. This not only improves productivity, but also allows the upper conductive layer to easily take over the crystal structure of the lower conductive layer, which ensures that the upper tantalum thin film is α-structured. There is. In the subsequent second step, a thin film containing α-structure tantalum as a main component is formed by a sputter deposition method in an atmosphere containing at least hydrogen and argon. As in the previous case, the hydrogen content in argon is adjusted so that the formed α-structure tantalum contains hydrogen at about 10 atm ppm to about 5000 atm ppm. Therefore, the value is about 0.1% to about 10%.
【0025】第三の製造方法は第一工程でまずα構造タ
ンタルを主成分とする薄膜を形成した後、第二工程にて
この薄膜に水素化処理を施して薄膜に所望量の水素を添
加する。この第一工程で形成されたタンタル薄膜は通常
強い内部応力を有して居る。この為薄膜が大きな温度変
化を被ると、内部応力に基づくひび割れや膜の剥がれが
生じて仕舞う。従って出来る限り冷却や加熱と云った熱
環境を変化させずに第二工程の水素化処理を施す事が理
想で有る。第一工程が終了してから第二工程を行う迄の
工程温度は少なくとも第一工程の基板処理温度と同等も
しくはそれ以下で有る事が望まれる。但しこの制約は基
板との兼ね合いでタンタル薄膜に前述した問題が生じな
ければ緩める事も可能で有る。第一工程でα構造のタン
タルを主成分とする薄膜を成膜するには先にも述べた通
り、少なくとも窒素とアルゴンを含有する雰囲気下にて
スパッター堆積法を行えば良い。スッパター堆積時のア
ルゴン中の窒素含有量は矢張り5.0%程度から8.5
%程度の間で有る。α構造タンタルを主成分とする薄膜
の別の形成方法は下側導伝膜の直上にタンタル薄膜をス
ッパター形成する物で有る。これは第二の製造方法で水
素を添加しないものに相当して居る。即ちニオブやタン
グステン、窒化タンタルと云った上層タンタルをα構造
化させ得る下側導伝膜を形成した後、この膜の直上にタ
ンタルをスッパター堆積させる方法で有る。この様に第
一工程で様々な方法にてα構造のタンタルを主成分とす
る薄膜を形成した後、剥離やひび割れと云った現象が生
ずる様な大きな温度変化を薄膜が被る前に、第二工程で
水素を添加し薄膜の応力緩和を図るので有る。第二工程
の水素化処理は水素イオン注入や水素プラズマ処理、或
いは水素含有雰囲気下での熱処理などで行い得る。二番
目の水素プラズマ処理はそれを第一工程でタンタル薄膜
を堆積したスッパター装置にて連続処理とすればタンタ
ル膜表面に酸化膜や汚染等が存在しない為水素添加効率
が上がり、同時に第一工程と第二工程との間に余分な工
程が入らない為薄膜に熱ストレスが掛かる前に内部応力
の緩和が可能と成る。無論この時生産性は改善されて居
る。水素化処理を水素イオン注入で行えば薄膜への水素
添加量を厳密に調整出来る。換言すればタンタル薄膜物
性を自由に変え得る訳で有る。この方法は後述する上ゲ
ート型薄膜半導体装置のゲート電極に本願発明の水素含
有α構造タンタルをを用いる時に殊の外有用で有る。第
一工程でゲート電極と成るα構造タンタルを成膜した
後、ゲート電極をマスクにソース・ドレイン領域形成の
イオン注入工程時に水素添加の第二工程を兼用させる事
が出来るからで有る。こうすると水素化処理の為の特別
な工程を増やす事無く、本願発明がその儘達成されるの
で有る。In the third manufacturing method, a thin film containing α-structure tantalum as a main component is first formed in the first step, and then the thin film is subjected to hydrogenation treatment in the second step to add a desired amount of hydrogen to the thin film. To do. The tantalum thin film formed in this first step usually has a strong internal stress. For this reason, when the thin film undergoes a large temperature change, cracks and peeling of the film due to internal stress occur and end up. Therefore, it is ideal to perform the hydrogenation treatment in the second step without changing the thermal environment such as cooling and heating as much as possible. It is desired that the process temperature from the completion of the first process to the second process is at least equal to or lower than the substrate processing temperature of the first process. However, this restriction can be relaxed if the tantalum thin film does not cause the above-mentioned problems in consideration of the substrate. As described above, the sputter deposition method may be performed in an atmosphere containing at least nitrogen and argon in order to form a thin film mainly containing tantalum of α structure in the first step. Nitrogen content in argon during sputter deposition is from about 5.0% to 8.5.
%. Another method for forming a thin film containing α-structured tantalum as a main component is to form a tantalum thin film on the lower conductive film by sputtering. This corresponds to the second manufacturing method in which hydrogen is not added. That is, it is a method of forming a lower conductive film capable of forming an α structure of upper tantalum such as niobium, tungsten, or tantalum nitride, and then sputter depositing tantalum directly on this film. In this way, after forming a thin film consisting mainly of α-structured tantalum by various methods in the first step, before the thin film undergoes a large temperature change that causes phenomena such as peeling and cracking, This is because hydrogen is added in the process to reduce the stress of the thin film. The hydrogenation treatment in the second step can be performed by hydrogen ion implantation, hydrogen plasma treatment, heat treatment in a hydrogen-containing atmosphere, or the like. If the second hydrogen plasma treatment is a continuous treatment with a sputter device in which a tantalum thin film is deposited in the first step, the hydrogenation efficiency will increase because there is no oxide film or contamination on the tantalum film surface, and at the same time the first step Since no extra step is inserted between the second step and the second step, the internal stress can be relaxed before the thin film is subjected to thermal stress. Of course, productivity is improving at this time. If hydrogenation is performed by hydrogen ion implantation, the amount of hydrogen added to the thin film can be adjusted precisely. In other words, the physical properties of the tantalum thin film can be changed freely. This method is particularly useful when the hydrogen-containing α-structure tantalum of the present invention is used for the gate electrode of the upper gate type thin film semiconductor device described later. This is because, after the α-structure tantalum to be the gate electrode is formed in the first step, the second step of hydrogen addition can also be used in the ion implantation step of forming the source / drain regions by using the gate electrode as a mask. In this way, the present invention can be achieved without increasing the number of special steps for hydrotreating.
【0026】(第2章、本願発明の薄膜半導体装置とそ
の製造方法の概略)次に第1章で説明した電子機器の内
で本願発明が取り分け効果的で有る薄膜半導体装置とそ
の製造方法を説明する。図1(a)〜(d)はMIS型
電界効果トランジスタを形成する薄膜半導体装置の製造
工程を断面で示した大概図で有る。この図が示す様に本
願発明が殊の外有益で有る薄膜半導体装置は所謂上ゲー
ト型TFTで有る。即ち本願発明の薄膜半導体装置は絶
縁性物質上に島状に形成された半導体層と、その半導体
層上に形成されたゲート絶縁層と、更にそのゲート絶縁
層上に形成されたゲート電極とを具備して居る。この図
を用いて本願発明が低温プロセスpoly−Si TF
Tに適応される際の予備知識を提供する。(Chapter 2, Outline of Thin Film Semiconductor Device of the Present Invention and Method of Manufacturing the Same) Next, among the electronic devices described in Chapter 1, the thin film semiconductor device and the method of manufacturing the thin film semiconductor device according to the present invention will be described. explain. 1A to 1D are schematic cross-sectional views showing a manufacturing process of a thin film semiconductor device for forming a MIS field effect transistor. As shown in this figure, the thin film semiconductor device to which the present invention is particularly useful is a so-called upper gate type TFT. That is, the thin film semiconductor device of the present invention comprises a semiconductor layer formed in an island shape on an insulating material, a gate insulating layer formed on the semiconductor layer, and a gate electrode formed on the gate insulating layer. I have it. The present invention is applied to the low temperature process poly-Si TF using this figure.
Provides prior knowledge when applied to T.
【0027】本発明では基板101の一例として汎用無
アルカリガラスを用いる。まず基板101上に常圧化学
気相堆積法(APCVD法)やPECVD法或いはスパ
ッター法などで絶縁性物質で有る下地保護膜102を形
成する。次に後に薄膜半導体装置の能動層と化す真性シ
リコン膜等の半導体膜を堆積する。半導体膜はLPCV
D法やPECVD法、APCVD法等の化学気相堆積法
(CVD法)、或いはスパッター法や蒸着法などの物理
気相堆積法(PVD法)に依って形成される。こうして
得られた半導体膜にレーザー光等の光学エネルギー又は
電磁波エネルギーを短時間照射して結晶化を進める。最
初に堆積した半導体膜が非晶質で有ったり、非晶質と微
結晶が混在する混晶質で有れば、この工程は結晶化と呼
ばれる。一方、最初に堆積した半導体膜が多結晶質で有
れば、この工程は再結晶化と呼ばれる。本明細書では特
に断らない限り両者をまとめて単に結晶化と称する。レ
ーザー光等のエネルギー強度が高ければ、結晶化の際に
半導体膜は一度熔融し冷却固化過程を経て結晶化する。
これを本願では熔融結晶化法と称する。これに対し半導
体膜の結晶化を熔融せずに固相にて進める方法を固相成
長法(SPC法)と称する。固相成長法は550℃程度
から650℃程度の温度で数時間から数十時間掛けて結
晶化を進める熱処理法(Furnace−SPC法)
と、一秒未満から一分程度の短時間で700℃から10
00℃との高温で結晶化を進める急速熱処理法(RTA
法)、及びレーザー光等のエネルギー強度が低い時に生
ずる極短時間固相成長法(VST−SPC法)の三者に
主として分類される。本願発明はこれら何れの結晶化方
法をも適応可能で有るが、大型基板を高い生産性で製造
するとの視点に則ると熔融結晶化法やRTA法、VST
−SPC法が取り分け適して居る。これらの結晶化方法
では照射時間が非常な短時間で有り且つ照射領域も基板
全体に対して局所的で有る為、半導体膜の結晶化に際し
て基板全体が熱せられる事は無く、故に基板の熱に依る
変形や割れ等も生じないからで有る。その後この半導体
膜をパターニングし、後にトランジスタの能動層となる
半導体膜103を作成する。(図1(a))
半導体膜形成後、CVD法やPVD法などでゲート絶縁
膜104を形成する。絶縁膜形成に当たり様々な製造方
法が考えられるが、絶縁膜形成温度は350℃以下が好
ましい。これはMOS界面やゲート絶縁膜の熱劣化を防
ぐ為に重要で有る。同じ事は以下の総ての工程に対して
も適用される。ゲート絶縁膜形成後の総ての工程温度は
350℃以下に押さえられねばならない。こうする事に
より高性能な薄膜半導体装置を容易に、且つ安定的に製
造出来るからで有る。In the present invention, general-purpose non-alkali glass is used as an example of the substrate 101. First, a base protective film 102, which is an insulating material, is formed on a substrate 101 by atmospheric pressure chemical vapor deposition (APCVD method), PECVD method, sputtering method, or the like. Next, a semiconductor film such as an intrinsic silicon film that will later become an active layer of the thin film semiconductor device is deposited. The semiconductor film is LPCV
It is formed by a chemical vapor deposition method (CVD method) such as D method, PECVD method, APCVD method or a physical vapor deposition method (PVD method) such as sputtering method or vapor deposition method. The semiconductor film thus obtained is irradiated with optical energy such as laser light or electromagnetic wave energy for a short time to proceed with crystallization. If the initially deposited semiconductor film is amorphous or has a mixed crystal quality in which amorphous and microcrystal are mixed, this process is called crystallization. On the other hand, if the initially deposited semiconductor film is polycrystalline, this process is called recrystallization. In the present specification, both are simply referred to as crystallization unless otherwise specified. If the energy intensity of laser light or the like is high, the semiconductor film is once melted during crystallization and then crystallized through a cooling and solidifying process.
This is referred to as a melt crystallization method in the present application. On the other hand, a method of advancing crystallization of a semiconductor film in a solid phase without melting is called a solid phase growth method (SPC method). The solid-phase growth method is a heat treatment method (Furnace-SPC method) for promoting crystallization at a temperature of about 550 ° C. to 650 ° C. for several hours to several tens of hours.
Then, from 700 ° C to 10 minutes in less than 1 second to 1 minute.
Rapid heat treatment method (RTA) that promotes crystallization at a high temperature of 00 ° C
Method) and a very short time solid phase growth method (VST-SPC method) which occurs when the energy intensity of laser light or the like is low. The present invention can be applied to any of these crystallization methods, but in view of manufacturing a large substrate with high productivity, the melt crystallization method, the RTA method, the VST method, and the like.
-The SPC method is particularly suitable. In these crystallization methods, the irradiation time is extremely short and the irradiation area is local to the entire substrate, so the entire substrate is not heated during crystallization of the semiconductor film, and therefore the heat of the substrate is not applied. This is because the resulting deformation and cracks do not occur. After that, this semiconductor film is patterned to form a semiconductor film 103 which becomes an active layer of a transistor later. (FIG. 1A) After forming the semiconductor film, the gate insulating film 104 is formed by a CVD method, a PVD method, or the like. Although various manufacturing methods can be considered for forming the insulating film, the insulating film forming temperature is preferably 350 ° C. or lower. This is important for preventing thermal deterioration of the MOS interface and the gate insulating film. The same applies to all steps below. All process temperatures after forming the gate insulating film must be kept below 350 ° C. By doing so, a high-performance thin film semiconductor device can be easily and stably manufactured.
【0028】引き続いてゲート電極105となる薄膜を
PVD法或いはCVD法などで堆積する。通常はゲート
電極とゲート配線は同一材料にて同一工程で作られる
為、この材質は電気抵抗が低く、350℃程度の熱工程
に対して安定で有る事が望まれる。ゲート電極となる薄
膜を堆積後パターニングを行い、引き続いて半導体膜に
不純物イオン注入106を行ってソース・ドレイン領域
107及びチャンネル領域108を形成する。(図1
(c))この時ゲート電極がイオン注入のマスクと成っ
て居るが故、チャンネルはゲート電極下のみに形成され
る自己整合構造と成る。不純物イオン注入は質量非分離
型イオン注入装置を用いて注入不純物元素の水素化物と
水素を注入するイオン・ドーピング法と質量分離型イオ
ン注入装置を用いて所望の不純物元素のみを注入するイ
オン打ち込み法の二種類が適応され得る。イオン・ドー
ピング法の原料ガスとしては水素中に希釈された濃度
0.1%程度から10%程度のホスフィン(PH3)や
ジボラン(B2H6)等の注入不純物元素の水素化物を用
いる。イオン打ち込み法では所望の不純物元素のみを注
入した後に引き続いて水素イオン(プロトンや水素分子
イオン)を注入する。前述の如くMOS界面やゲート絶
縁膜を安定に保つ為には、イオン・ドーピング法にしろ
イオン打ち込み法にしろイオン注入時の基板温度は35
0℃以下でなければならない。一方注入不純物の活性化
を350℃以下の低温にて常に安定的に行うには、イオ
ン注入時の基板温度は200℃以上で有る事が望まし
い。トランジスタのしきい値電圧を調整する為にチャン
ネル・ドープ行うとか、或いはLDD構造を作成すると
云った様に低濃度に注入された不純物イオンを低温で確
実に活性化するには、イオン注入時の基板温度は250
℃以上で有る事が必要と成る。この様に基板温度が高い
状態でイオン注入を行うと、半導体膜のイオン注入に伴
う結晶壊破の際に再結晶化も同時に生じ、結果としてイ
オン注入部の非晶質化を防ぐ事が出来るので有る。即ち
イオン注入された領域は注入後も依然として結晶質とし
て残り、その後の活性化温度が350℃程度以下と低温
で有っても注入イオンの活性化が可能に成る訳で有る。
CMOS TFTを作成する時はポリイミド樹脂等の適
当なマスク材を用いてNMOS又はPMOSの一方を交
互にマスクで覆い、上述の方法にてそれぞれのイオン注
入を行う。イオン注入時の基板温度が300℃程度以下
で有れば、ポリイミド樹脂に代わって安価で保存等の取
扱いが易しい汎用フォト・レジストをイオン注入に対す
るマスクとして使用する事が可能と成る。Subsequently, a thin film to be the gate electrode 105 is deposited by the PVD method or the CVD method. Normally, the gate electrode and the gate wiring are made of the same material in the same process, and therefore it is desired that this material has a low electric resistance and is stable against a heat process of about 350 ° C. After depositing a thin film to be a gate electrode, patterning is performed, and then impurity ion implantation 106 is performed on the semiconductor film to form a source / drain region 107 and a channel region 108. (Fig. 1
(C) Since the gate electrode serves as a mask for ion implantation at this time, the channel has a self-aligned structure formed only under the gate electrode. Impurity ion implantation is an ion doping method in which a hydride of an impurity element and hydrogen are implanted using a mass non-separation type ion implantation apparatus, and an ion implantation method in which only a desired impurity element is implanted using a mass separation type ion implantation apparatus. Two types of can be applied. As a source gas for the ion doping method, a hydride of an implanted impurity element such as phosphine (PH 3 ) or diborane (B 2 H 6 ) diluted in hydrogen at a concentration of about 0.1% to 10% is used. In the ion implantation method, hydrogen ions (protons and hydrogen molecule ions) are subsequently implanted after only the desired impurity element is implanted. As described above, in order to keep the MOS interface and the gate insulating film stable, the substrate temperature at the time of ion implantation is 35, whether it is the ion doping method or the ion implantation method.
Must be below 0 ° C. On the other hand, in order to always stably activate the implanted impurities at a low temperature of 350 ° C. or lower, it is desirable that the substrate temperature at the time of ion implantation is 200 ° C. or higher. In order to surely activate the impurity ions implanted at a low concentration at a low temperature such as performing channel doping to adjust the threshold voltage of the transistor or creating an LDD structure, it is necessary to Substrate temperature is 250
It must be above ℃. When the ion implantation is performed at such a high substrate temperature, recrystallization also occurs at the time of crystal breakage accompanying the ion implantation of the semiconductor film, and as a result, the ion implantation portion can be prevented from becoming amorphous. Because it is. That is, the ion-implanted region remains crystalline after the implantation, and the implanted ions can be activated even if the activation temperature thereafter is as low as about 350 ° C. or lower.
When forming a CMOS TFT, one of NMOS and PMOS is alternately covered with a mask using a suitable mask material such as polyimide resin, and the respective ions are implanted by the above-mentioned method. If the substrate temperature at the time of ion implantation is about 300 ° C. or less, it becomes possible to use a general-purpose photoresist which is cheap and easy to handle such as storage instead of the polyimide resin as a mask for the ion implantation.
【0029】次に層間絶縁膜109をCVD法或いはP
VD法で形成する。イオン注入と層間絶縁膜形成後、3
50℃程度以下の適当な熱環境下にて数十分から数時間
の熱処理を施して注入イオンの活性化及び層間絶縁膜の
焼き締めを行う。この熱処理温度は注入イオンを確実に
活性化する為にも250℃程度以上が好ましい。又層間
絶縁膜を効能的に焼き締めるには300℃以上の温度が
好ましい。通常ゲート絶縁膜と層間絶縁膜とではその膜
品質が異なって居る。その為に層間絶縁膜形成後二つの
絶縁膜にコンタクトホールを開ける際、絶縁膜のエッチ
ング速度が違って居るのが普通で有る。斯様な条件下で
はコンタクトホールの形状が下方程広い逆テーパー状に
成ったり或いは庇が発生して仕舞い、その後電極形成し
た時に電気的な導通がうまく取れない所謂接触不良の原
因と成る。層間絶縁膜を効能的に焼き締めるとこうした
接触不良の発生を最小限に止められるので有る。層間絶
縁膜形成後ソース・ドレイン上にコンタクトホールを開
孔し、ソース・ドレイン取り出し電極110とこれらの
配線をPVD法やCVD法などで形成して薄膜半導体装
置が完成する。(図1(d))
(第3章、本願発明の薄膜半導体装置とその製造方法に
関する詳細説明)第1章で説明した水素含有α構造タン
タルは様々な電子機器に適応出来る。しかしながらこの
導伝材料の最大の特徴は比抵抗が低い事と内部応力が小
さい事、及び延性を呈して居る事に有る。斯様な特徴は
長配線を有する電子機器や基板物性と配線物性が著しく
異なる電子機器、或いは配線の厚みに対して無視し得な
い段差を乗り越える必要が有る電子機器、又は配線の内
部応力がその性能に影響を及ぼす電子機器などで良く活
かされる。この条件を満たす電子機器の一例としては太
陽電池や液晶表示装置に利用されるガラス基板上に形成
された薄膜半導体装置が有る。これらの電子機器の配線
長は数cm程度から数十cm程度にも及び、更に基板の
熱物性と配線材料の熱物性は大きく異なって居るのが普
通だからで有る。従って本願発明の電子機器の内でも太
陽電池や液晶表示装置に用いられる薄膜半導体装置は特
にその得られる効果が大きいと言える。第2章で説明し
た様に薄膜半導体装置にはゲート電極・配線とソース電
極・配線、及びドレイン電極・配線の三種類の電気導伝
性材料が絶縁性物質上に形成されて居る。水素含有α構
造タンタルはこれら三種類の電気導伝性材料のいずれに
も適応し得る。配線の厚みに対して無視し得ない段差を
乗り越えるとの観点に則ると下ゲート型TFTのソース
電極・配線やドレイン電極・配線、或いは上ゲート型T
FTの各種電極・配線に適応されると段差部での断線が
抑制されるとの別な効果が加えられる。更に配線の内部
応力がトランジスタ特性に悪影響を及ぼさず、製造工程
も簡単との効果は水素含有α構造タンタルを上ゲートT
FTのゲート電極・配線に用いた時に加えられる。以下
この事を説明する。Next, the interlayer insulating film 109 is formed by the CVD method or P
It is formed by the VD method. After ion implantation and interlayer insulating film formation, 3
Heat treatment is carried out for several tens of minutes to several hours in an appropriate thermal environment of about 50 ° C. or less to activate implanted ions and bake the interlayer insulating film. This heat treatment temperature is preferably about 250 ° C. or higher in order to surely activate the implanted ions. Further, a temperature of 300 ° C. or higher is preferable to effectively bake the interlayer insulating film. Generally, the film quality of the gate insulating film is different from that of the interlayer insulating film. Therefore, when the contact holes are formed in the two insulating films after the interlayer insulating film is formed, the etching rates of the insulating films are usually different. Under such a condition, the shape of the contact hole becomes wider toward the lower side in the shape of an inverse taper or an eaves is generated, which ends up causing a so-called contact failure in which electrical continuity cannot be established when an electrode is formed thereafter. Effectively baking the interlayer insulating film can minimize the occurrence of such contact failure. After forming the interlayer insulating film, contact holes are opened on the source / drain, and the source / drain extraction electrode 110 and these wirings are formed by the PVD method or the CVD method to complete the thin film semiconductor device. (FIG. 1 (d)) (Chapter 3, Detailed Description of Thin Film Semiconductor Device and Manufacturing Method Thereof of the Present Invention) The hydrogen-containing α-structure tantalum described in Chapter 1 can be applied to various electronic devices. However, the most important features of this conductive material are low specific resistance, low internal stress, and ductility. Such features include electronic devices with long wiring, electronic devices whose wiring physical properties are significantly different from those of the wiring, electronic devices that need to overcome a step that cannot be ignored with respect to the thickness of the wiring, or internal stress of the wiring It is often used in electronic devices that affect performance. An example of electronic equipment that satisfies this condition is a thin film semiconductor device formed on a glass substrate used for a solar cell or a liquid crystal display device. This is because the wiring length of these electronic devices extends from several cm to several tens of cm, and the thermophysical properties of the substrate and the wiring material are usually greatly different. Therefore, it can be said that the thin film semiconductor device used for a solar cell or a liquid crystal display device has a particularly large effect among the electronic devices of the present invention. As described in Chapter 2, in the thin film semiconductor device, three kinds of electrically conductive materials, that is, a gate electrode / wiring, a source electrode / wiring, and a drain electrode / wiring are formed on an insulating substance. Hydrogen-containing α-structure tantalum can be applied to any of these three types of electrically conductive materials. From the viewpoint of overcoming a step that cannot be ignored with respect to the thickness of the wiring, the source electrode / wiring or drain electrode / wiring of the lower gate type TFT or the upper gate type T
When applied to various electrodes and wirings of FT, another effect of suppressing disconnection at the step portion is added. Furthermore, the internal stress of the wiring does not adversely affect the transistor characteristics and the manufacturing process is simple.
It is added when used for the gate electrode and wiring of FT. This will be explained below.
【0030】第2章で説明した上ゲート型TFTのゲー
ト電極・配線に第1章で説明した水素含有α構造タンタ
ルを適応する。即ちゲート電極の少なくとも一部は水素
を含有するα構造のタンタルで有る。無論ゲート電極が
窒素と水素を含有するタンタルで有っても良い。このゲ
ート電極は第1章で述べた各製造方法により作成され
る。ゲート電極形成後にソース・ドレイン領域形成の為
のイオン注入工程が控えて居る訳で有るが、水素や窒素
を含有して居るαタンタルの場合これらの原子の幾つか
は必ずタンタル結晶の格子間に入って居る。その為ゲー
ト電極をマスクとしたイオン注入の際に仮令少数の注入
イオンがタンタル結晶の格子間をすり抜けたとしても、
そのイオンは格子間に存在する水素原子や窒素原子と衝
突して運動方向を変える事に成る。斯様に散乱された注
入イオンはもはや格子間をすり抜ける事が出来ず、その
結果ゲート電極は注入イオンに対する完全な阻止能力を
獲得するに至る。斯くして本願発明の薄膜半導体装置で
はゲート電極が導伝性結晶体で有っても、チャンネル形
成半導体領域とその直上に位置するゲート絶縁膜にはソ
ース・ドレイン形成の為のP型もしくはN型のイオンは
全く導入されず、信頼性の優れた高性能TFTが安定的
に製造され得るのである。又前述の如く窒素を含む等の
α構造タンタルを主成分とする薄膜を形成する第一工程
終了後にこの薄膜をゲート電極・配線に加工し、その後
第二工程の水素化処理をソース・ドレイン領域形成のイ
オン注入工程で兼用させれば特別な工程を増やす事無く
本願発明が達成される。例えばソース・ドレイン領域を
イオン・ドーピング法で行う場合にはホスフィン(PH
3)やジボラン(B2H6)と云った注入不純物元素の水
素化物を希釈する水素の濃度を調整した上でイオン注入
工程を行えば、自動的に所望量の水素を含有したα構造
タンタルが得られる。注入不純物元素の水素化物と水素
の濃度はヘリウム、ネオン、アルゴン、クリプトンなど
の第二の希釈媒体を用いる事で容易に調整される。又質
量分離を伴うイオン打ち込み法でソース・ドレイン形成
を行う場合には所望の不純物元素を注入した後に引き続
いて水素イオン(プロトンや水素分子イオン)を注入し
て居る。この水素注入はソース・ドレイン領域に打ち込
まれた不純物を350℃程度以下の低温で活性化させる
事を本来の目的として居るが、当然ゲート電極への水素
添加と兼用される。従ってイオン打ち込み法に於いても
特別な工程を増やす事無く本願発明を達成出来る訳で有
る。The hydrogen-containing α-structure tantalum described in Chapter 1 is applied to the gate electrode / wiring of the upper gate type TFT described in Chapter 2. That is, at least part of the gate electrode is α-structured tantalum containing hydrogen. Of course, the gate electrode may be tantalum containing nitrogen and hydrogen. This gate electrode is formed by each manufacturing method described in Chapter 1. Although the ion implantation process for forming the source / drain regions is being refrained from after forming the gate electrode, in the case of α-tantalum containing hydrogen and nitrogen, some of these atoms must be in the lattice of the tantalum crystal. I'm in. Therefore, even if a small number of tentatively implanted ions pass through the lattice of the tantalum crystal during ion implantation with the gate electrode as a mask,
The ions collide with hydrogen atoms and nitrogen atoms existing between the lattices to change the moving direction. The thus-implanted implanted ions can no longer pass through the interstitial spaces, resulting in the gate electrode acquiring a complete blocking ability for the implanted ions. Thus, in the thin-film semiconductor device of the present invention, even if the gate electrode is a conductive crystal, the channel forming semiconductor region and the gate insulating film located immediately above the P-type or N-type for forming the source / drain. No type ions are introduced, and a highly reliable high performance TFT can be stably manufactured. Further, as described above, after the first step of forming a thin film mainly containing α-structure tantalum such as containing nitrogen, this thin film is processed into a gate electrode / wiring, and then a second step of hydrogenation treatment is performed on the source / drain regions. If the ion implantation step for forming is also used, the present invention can be achieved without increasing a special step. For example, when the source / drain regions are formed by ion doping, phosphine (PH
3 ) or diborane (B 2 H 6 ), if the ion implantation step is performed after adjusting the concentration of hydrogen that dilutes the hydride of the implanted impurity element, α-structure tantalum containing the desired amount of hydrogen automatically Is obtained. The hydride and hydrogen concentrations of the implanted impurity element are easily adjusted by using a second diluent medium such as helium, neon, argon, krypton. Further, in the case of forming the source / drain by the ion implantation method with mass separation, hydrogen ions (protons and hydrogen molecule ions) are subsequently injected after the desired impurity element is injected. The purpose of this hydrogen implantation is to activate the impurities implanted in the source / drain regions at a low temperature of about 350 ° C. or lower, but of course it is also used to add hydrogen to the gate electrode. Therefore, even in the ion implantation method, the present invention can be achieved without increasing the number of special steps.
【0031】さて能動層半導体膜が多結晶状態に有る電
界効果型薄膜半導体装置ではゲート電極の内部応力の有
無がトランジスタ特性の善し悪しに影響を及ぼす。第1
章で説明した様に本願発明の水素含有αタンタルはその
内部応力が非常に弱い為、これをゲート電極に用いると
良好な特性を示す薄膜半導体装置と成るので有る。In the field effect thin film semiconductor device in which the active layer semiconductor film is in a polycrystalline state, the presence or absence of internal stress in the gate electrode affects the quality of the transistor. First
As described in the section, since the hydrogen-containing α-tantalum of the present invention has a very weak internal stress, when it is used for the gate electrode, it becomes a thin film semiconductor device showing good characteristics.
【0032】(実施例1)図1(a)〜(d)はMIS
型電界効果トランジスタを形成する薄膜半導体装置の製
造工程を断面で示した図で有る。(Embodiment 1) FIGS. 1A to 1D show MIS.
FIG. 6 is a cross-sectional view showing a manufacturing process of a thin film semiconductor device for forming a field effect transistor.
【0033】本実施例1では基板101として235mm
□の無アルカリガラス(日本電気硝子社OAー2)を用
いたが、工程最高温度に耐え得る基板で有るならば、基
板の種類や大きさは無論問われない。まず基板101上
に常圧化学気相堆積法(APCVD法)やPECVD法
或いはスパッター法などで下地保護膜となる二酸化珪素
膜(SiO2膜)102を形成する。APCVD法では
基板温度250℃から450℃程度でモノシラン(Si
H4)や酸素を原料としてSiO2膜を堆積できる。PE
CVD法やスパッター法では基板温度を室温から400
℃とする事が出来る。本実施例1ではAPCVD法でS
iH4とO2を原料ガスとして300℃で2000ÅのS
iO2膜を堆積した。In the first embodiment, the substrate 101 is 235 mm.
□ Alkali-free glass (OA-2 from Nippon Electric Glass Co., Ltd.) was used, but of course the type and size of the substrate are not limited as long as the substrate can withstand the maximum process temperature. First, a silicon dioxide film (SiO 2 film) 102 serving as a base protection film is formed on a substrate 101 by atmospheric pressure chemical vapor deposition (APCVD method), PECVD method, sputtering method, or the like. In the APCVD method, monosilane (Si
A SiO 2 film can be deposited using H 4 ) or oxygen as a raw material. PE
In the CVD method and the sputtering method, the substrate temperature is from room temperature to 400.
It can be set to ℃. In the first embodiment, S is formed by the APCVD method.
2000 Å S at 300 ° C using iH 4 and O 2 as source gases
An iO 2 film was deposited.
【0034】次に後に薄膜半導体装置の能動層と化す真
性シリコン膜を500Å程度堆積した。真性シリコン膜
は高真空型LPCVD装置にて、原料ガスで有るジシラ
ン(Si2H6)を200SCCM流し堆積温度425℃で5
8分間堆積した。本実施例1にて使用した高真空型LP
CVD装置は184.5lの容積を有する。17枚の基
板は表側を下向きとして、250℃に保たれた反応室に
挿入された。基板挿入後、ターボ分子ポンプの運転を開
始し、定常回転に達した後、漏洩検査を2分間施した。
この時の脱ガス等の漏洩速度は3.1×10-5torr/min
で有った。その後挿入温度の250℃から堆積温度の4
25℃迄一時間費やして昇温した。昇温の最初の10分
間は反応室にガスを全く導入せず、真空中で昇温した。
昇温開始後10分後の反応室到達最低背景圧力は5.2
×10-7torrで有った。又残り50分間の昇温期間には
純度99.9999%以上の窒素ガスを300SCCM流し
続けた。この時の反応室内平衡圧力は3.0×10-3to
rrで有った。堆積温度到達後、原料ガスで有るSi2H6
を200SCCMと純度99.9999%以上の希釈用
ヘリウム(He)を1000SCCM流し、シリコン膜
を58分間堆積した。Si2H6等のガスを反応室に導入
した直後の圧力は767mtorrで有り、これら原料
ガス等を導入してから57分後の圧力は951mtor
rで有った。こうして得られたシリコン膜の膜厚は50
1Åで有り、基板の周辺部7mmを除いた221mm□
の正方形領域内での膜厚変動は±5Å未満で有った。本
実施例1では斯様にLPCVD法にてシリコン膜を形成
したが、形成方法はこれに限らず、PECVD法やスパ
ッター法によっても良い。PECVD法やスパッター法
ではシリコン膜形成温度を室温から350℃程度とする
事が可能である。Then, an intrinsic silicon film to be an active layer of the thin film semiconductor device is deposited to about 500 Å. For the intrinsic silicon film, disilane (Si 2 H 6 ) which is a raw material gas is caused to flow in a high vacuum LPCVD apparatus at a flow rate of 200 SCCM and a deposition temperature of 425 ° C.
Deposited for 8 minutes. High vacuum type LP used in the first embodiment
The CVD device has a volume of 184.5 l. The 17 substrates were inserted into the reaction chamber kept at 250 ° C. with the front side facing down. After inserting the substrate, the turbo molecular pump was started to operate, and after reaching a steady rotation, a leak test was performed for 2 minutes.
The leak rate of degassing at this time is 3.1 × 10 -5 torr / min
It was. After that, the insertion temperature of 250 ° C to the deposition temperature of 4
The temperature was raised to 25 ° C. for one hour. During the first 10 minutes of heating, no gas was introduced into the reaction chamber and the temperature was raised in vacuum.
The minimum background pressure reached to the reaction chamber 10 minutes after the start of heating was 5.2.
It was × 10 -7 torr. During the remaining 50 minutes of temperature rising period, 300 SCCM of nitrogen gas having a purity of 99.9999% or higher was kept flowing. At this time, the equilibrium pressure in the reaction chamber is 3.0 × 10 −3 to
It was rr. After reaching the deposition temperature, Si 2 H 6 which is the source gas
200 SCCM and helium (He) for dilution having a purity of 99.9999% or more was flowed at 1000 SCCM to deposit a silicon film for 58 minutes. The pressure immediately after introducing a gas such as Si 2 H 6 into the reaction chamber is 767 mtorr, and the pressure 57 minutes after introducing these source gases is 951 mtorr.
It was r. The thickness of the silicon film thus obtained is 50
1Å, 221mm □ excluding 7mm around the board
The film thickness variation within the square region was less than ± 5Å. Although the silicon film is formed by the LPCVD method in the first embodiment, the forming method is not limited to this and may be a PECVD method or a sputtering method. In the PECVD method and the sputtering method, the silicon film formation temperature can be set to room temperature to about 350 ° C.
【0035】こうして得られたシリコン膜は高純度のa
−Si膜で有る。次にこのa−Si膜に光学エネルギー
又は電磁波エネルギーを短時間照射してa−Siを結晶
化し、多結晶シリコン(poly−Si)へと改質す
る。本実施例1ではキセノン・クロライド(XeCl)
のエキシマ・レーザー(波長308nm)を照射した。
レーザーパルスの強度半値幅は45nsである。照射時
間が斯様に非常な短時間で有る為、a−Siのpoly
−Siへの結晶化に際して基板が熱せられる事は無く、
故に基板の変形等も生じない。レーザー照射は基板を室
温(25℃)とし、空気中で行った。レーザー照射の一
回の照射面積は8mm□の正方形で有り、各照射毎に4
mmずらして行く。最初に水平方向(Y方向)に走査し
た後、次に垂直方向(X方向)にも4mmずらせて、再
び水平方向に4mmずつずらせて走査し、以後この走査
を繰り返して基板全面に第一回目のレーザー照射を行
う。この第一回目のレーザー照射エネルギー密度は16
0mJ/cm2で有った。第一回目のレーザー照射が終
了した後、エネルギー密度を275mJ/cm2として
第二回目のレーザー照射を全面に行う。走査方法は第一
回目のレーザー照射と同じで8mm□の正方形の照射領
域をY方向とX方向に4mmずらせて走査する。この二
段階レーザー照射に依り基板全体がa−Siからpol
y−Siへと均一に結晶化される。本実施例1では光学
エネルギー又は電磁波エネルギーとしてXeClエキシ
マ・レーザーを用いたが、エネルギー照射時間が数十秒
以内で有ればそのエネルギー源には囚らわれない。例え
ばArFエキシマ・レーザーや、XeFエキシマ・レー
ザー、KrFエキシマ・レーザー、YAGレーザー、炭
酸ガスレーザー、Arレーザー、色素レーザー等の各種
レーザー、或いはアークランプやタングステンランプ等
のランプ光を照射しても良い。アークランプ照射を行う
場合ランプ出力を1kW/cm2程度以上とし、照射時
間を45秒程度とする事でa−Siからpoly−Si
への膜質改変が進む。この結晶化に際してもエネルギー
照射時間は短時間なので、基板の熱による変形や割れは
生じない。次にこのシリコン膜をパターニングし、トラ
ンジスタの能動層となるチャンネル部半導体膜103を
作成した。(図1(a))
その後ECR−PECVD法やPECVD法などでゲー
ト絶縁膜104を形成する。本実施例1ではゲート絶縁
膜としてSiO2膜を用い、PECVD法で1200Å
の膜厚に堆積した。(図1(b))基板をPECVD装
置に設置する直前には、基板を1.67%のフッ化水素
酸水溶液に20秒間浸して半導体膜表面の自然酸化膜を
取り除いた。酸化膜除去から基板をPECVD装置のロ
ードロック室に入れる迄の時間は約15分程度で有っ
た。この時間は出来る限り短い事がMOS界面清浄化の
視点より望まれ、最長でも30分程度以内が好ましい。
PECVD法では原料ガスとしてモノシラン(Si
H4)と笑気ガス(N2O)を用いて基板温度300℃に
て形成した。プラズマは13.56MHzのrf波によ
り、出力900W、真空度1.50torrとの条件で
立てられた。SiH4の流量は250SCCMでN2Oの
流量は7000SCCMであった。SiO2膜の成膜速
度は48.3Å/sで有った。SiO2をこれらの条件
で成膜する直前と直後にはシリコン膜及び形成酸化膜に
酸素プラズマを照射して、MOS界面及び酸化膜の改善
をおこなった。本実施例1では原料ガスとしてモノシラ
ンと笑気ガスを用いたが、これらに限らずTEOS(S
i−(O−CH2−CH3)4)等の有機シランと酸素等
の酸化性気体を用いても良い。更にここでは汎用性の高
いPECVD装置を利用したが、無論ECR−PECV
D装置によって絶縁膜を形成しても良い。どの様なCV
D装置や原料ガスを用いる場合であっても、絶縁膜形成
温度は350℃以下が好ましい。これはMOS界面やゲ
ート絶縁膜の熱劣化を防ぐ為に重要で有る。同じことは
以下の総ての工程に対しても適用される。ゲート絶縁膜
形成後の総ての工程温度は350℃以下に押さえられね
ばならない。こうする事により高性能な薄膜半導体装置
を容易に、且つ安定的に製造出来るからで有る。The silicon film thus obtained has a high purity a.
-Si film. Next, this a-Si film is irradiated with optical energy or electromagnetic wave energy for a short time to crystallize a-Si and modify it into polycrystalline silicon (poly-Si). In Example 1, xenon chloride (XeCl)
Excimer laser (wavelength 308 nm) was irradiated.
The full width at half maximum intensity of the laser pulse is 45 ns. Since the irradiation time is such a very short time, the poly of a-Si
-The substrate is not heated during crystallization into -Si,
Therefore, the substrate is not deformed. Laser irradiation was performed in air with the substrate at room temperature (25 ° C.). The irradiation area for each laser irradiation is a square of 8 mm □, 4 for each irradiation.
Shift by mm. After first scanning in the horizontal direction (Y direction), then also shifting in the vertical direction (X direction) by 4 mm, again by shifting by 4 mm in the horizontal direction, and then scanning is repeated. Laser irradiation. This first laser irradiation energy density is 16
It was 0 mJ / cm 2 . After the first laser irradiation is completed, the energy density is set to 275 mJ / cm 2 and the second laser irradiation is performed on the entire surface. The scanning method is the same as the first laser irradiation, and scanning is performed by shifting the irradiation area of a square of 8 mm square by 4 mm in the Y direction and the X direction. Due to this two-stage laser irradiation, the entire substrate is a-Si to pol.
It is crystallized uniformly into y-Si. In Example 1, the XeCl excimer laser was used as the optical energy or the electromagnetic wave energy, but if the energy irradiation time is within several tens of seconds, it is not restricted by the energy source. For example, various lasers such as ArF excimer laser, XeF excimer laser, KrF excimer laser, YAG laser, carbon dioxide laser, Ar laser, dye laser, or lamp light such as arc lamp or tungsten lamp may be irradiated. . When performing arc lamp irradiation, the lamp output is set to about 1 kW / cm 2 or more, and the irradiation time is set to about 45 seconds.
Modification of the membrane quality to Even during this crystallization, the energy irradiation time is short, so that the substrate is not deformed or cracked due to heat. Next, this silicon film was patterned to form a channel portion semiconductor film 103 to be an active layer of the transistor. (FIG. 1A) After that, the gate insulating film 104 is formed by an ECR-PECVD method or a PECVD method. In the first embodiment, a SiO 2 film is used as a gate insulating film, and 1200 Å by PECVD method.
Deposited to a film thickness of. (FIG. 1B) Immediately before installing the substrate in the PECVD apparatus, the substrate was immersed in a 1.67% hydrofluoric acid aqueous solution for 20 seconds to remove the natural oxide film on the surface of the semiconductor film. The time from removing the oxide film to putting the substrate in the load lock chamber of the PECVD apparatus was about 15 minutes. This time is desired to be as short as possible from the viewpoint of cleaning the MOS interface, and it is preferably about 30 minutes at the longest.
In the PECVD method, monosilane (Si
H 4 ) and laughing gas (N 2 O) were used at a substrate temperature of 300 ° C. The plasma was set up with an rf wave of 13.56 MHz, an output of 900 W, and a vacuum degree of 1.50 torr. The flow rate of SiH 4 was 250 SCCM and the flow rate of N 2 O was 7000 SCCM. The deposition rate of the SiO 2 film was 48.3 Å / s. Immediately before and immediately after forming SiO 2 under these conditions, the silicon film and the formed oxide film were irradiated with oxygen plasma to improve the MOS interface and the oxide film. In the first embodiment, monosilane and laughing gas were used as the raw material gas, but TEOS (S
i- (O-CH 2 -CH 3 ) 4) may be used organic silane and an oxidizing gas such as oxygen or the like. Furthermore, although a PECVD apparatus with high versatility was used here, of course, ECR-PECV
The insulating film may be formed by a D device. What kind of CV
Even when the D apparatus or the source gas is used, the insulating film formation temperature is preferably 350 ° C. or lower. This is important for preventing thermal deterioration of the MOS interface and the gate insulating film. The same applies to all the following steps. All process temperatures after forming the gate insulating film must be kept below 350 ° C. By doing so, a high-performance thin film semiconductor device can be easily and stably manufactured.
【0036】引き続いてゲート電極105となる薄膜を
スパッター法蒸着法或いはCVD法などで堆積する。本
実施例1ではゲート電極材料としてタンタル(Ta)を
選択し、スパッター法で500nm堆積した。スパッタ
ー時の基板温度は180℃でスパッターガスとしては窒
素(N2)を6.7%含んだアルゴン(Ar)を用い
た。アルゴン中の窒素含有量は5.0%から8.5%が
最適で有る。こうした条件にて得られたタンタル膜の結
晶構造は主としてα構造となっており、その比抵抗は4
0μΩcmで有る。従って本実施例1に於けるゲート電極
のシート抵抗は0.8Ω/□で有る。Subsequently, a thin film to be the gate electrode 105 is deposited by the sputtering method vapor deposition method or the CVD method. In Example 1, tantalum (Ta) was selected as the gate electrode material and was deposited to a thickness of 500 nm by the sputtering method. The substrate temperature at the time of sputtering was 180 ° C., and argon (Ar) containing 6.7% of nitrogen (N 2 ) was used as the sputtering gas. The optimum nitrogen content in argon is 5.0% to 8.5%. The crystal structure of the tantalum film obtained under these conditions is mainly α structure, and its specific resistance is 4
It is 0 μΩcm. Therefore, the sheet resistance of the gate electrode in Example 1 is 0.8Ω / □.
【0037】ゲート電極となる薄膜を堆積後通常のフォ
トリソグラフィー法によりパターニングを行う。フォト
レジストの露光前の熱処理は90℃で現像後の熱処理は
130℃で有った。従ってαタンタル形成からイオン注
入迄の工程最高温度は130℃で有る。引き続いて真性
シリコン膜にバケット型質量非分離型のイオン注入装置
(イオン・ドーピング法)を用いて燐元素等の不純物イ
オン注入106を行い、ソース・ドレイン領域107及
びチャンネル領域108を形成した。(図1(c))本
実施例1ではNMOS TFTの作成を目指した為、原
料ガスとしては水素中に希釈された濃度5%のホスフィ
ン(PH3)を用い、高周波出力38W、加速電圧80
kVで5×10151/cm2の濃度に打ち込んだ。この時
同時に水素がゲート電極にも注入され、ゲート電極は水
素を含有するα構造タンタルと成る。タンタルに対する
水素の割合は凡2000atm ppmで有る。高周波
出力は20Wから150W程度の適便たる値が用いられ
る。PMOS TFTを作成する場合は、原料ガスとし
て水素中に希釈された濃度5%のジボラン(B2H6)を
用い、高周波出力を20Wから150Wとし、加速電圧
60kVで5×10 151/cm2程度の濃度に打ち込む。
又、CMOS TFTを作成する時はポリイミド樹脂等
の適当なマスク材を用いてNMOS又はPMOSの一方
を交互にマスクで覆い、上述の方法にてそれぞれのイオ
ン注入を行う。After depositing a thin film to be a gate electrode, a normal photo film is formed.
Patterning is performed by a lithographic method. photo
The heat treatment of the resist before exposure is 90 ° C, and the heat treatment after development is
It was at 130 ° C. Therefore, from the formation of α tantalum to ion implantation
The maximum process temperature until turning on is 130 ° C. Continued authenticity
Bucket type non-mass separated ion implanter for silicon film
(Ion doping method) is used to remove impurities such as phosphorus.
The ON implantation 106 is performed, and the source / drain regions 107 and
And the channel region 108 are formed. (Fig. 1 (c)) Book
In Example 1, the aim was to create an NMOS TFT, so
As the source gas, phosphine with a concentration of 5% diluted in hydrogen was used.
(PH3), High frequency output 38W, acceleration voltage 80
5 × 10 at kV151 / cm2Driven to the concentration of. At this time
At the same time, hydrogen is also injected into the gate electrode,
It becomes α-structure tantalum containing element. Against tantalum
The proportion of hydrogen is about 2000 atm ppm. high frequency
The output is a convenient value of about 20W to 150W.
It When creating a PMOS TFT, use the source gas
5% diborane (B2H6)
High frequency output from 20W to 150W, acceleration voltage
5 × 10 at 60kV 151 / cm2Drive to a moderate concentration.
Also, when making CMOS TFTs, polyimide resin, etc.
Either NMOS or PMOS using the appropriate mask material
Alternately, cover each with a mask, and
Injection.
【0038】次に層間絶縁膜109を5000Å堆積す
る。本実施例1では層間絶縁膜としてSiO2をPEC
VD法にて形成した。PECVD法では原料ガスとして
TEOS(Si−(O−CH2−CH3)4)と酸素
(O2)を用いて基板温度300℃にて形成した。プラ
ズマは13.56MHzのrf波により、出力800
W、真空度8.0torrとの条件で立てられた。TE
OSの流量は200SCCMでO2の流量は8000S
CCMであった。この時SiO2膜の成膜速度は12n
m/sで有った。こうしたイオン注入と層間絶縁膜形成
後、酸素雰囲気下300℃で1時間熱処理を施して注入
イオンの活性化及び層間絶縁膜の焼き締めを行った。こ
の熱処理温度は300℃から350℃が好ましい。その
後、コンタクトホールを開け、ソース・ドレイン取り出
し電極110をスパッター法などで形成し、薄膜半導体
装置が完成する。(図1(d))ソース・ドレイン取り
出し電極としてはインジウム錫酸化物(ITO)やアル
ミニウム(Al)が用いられる。これらの導電体スパッ
ター時の基板温度は100℃から250℃程度で有る。Next, an interlayer insulating film 109 is deposited by 5000 Å. In the first embodiment, PEC is made of SiO 2 as an interlayer insulating film.
It was formed by the VD method. In the PECVD method, TEOS (Si— (O—CH 2 —CH 3 ) 4 ) and oxygen (O 2 ) were used as source gases at a substrate temperature of 300 ° C. Plasma is output 800 by rf wave of 13.56MHz
It was set up under the conditions of W and a vacuum degree of 8.0 torr. TE
The OS flow rate is 200 SCCM and the O 2 flow rate is 8000S.
It was CCM. At this time, the deposition rate of the SiO 2 film is 12 n
It was m / s. After such ion implantation and formation of the interlayer insulating film, heat treatment was performed in an oxygen atmosphere at 300 ° C. for 1 hour to activate the implanted ions and to bake the interlayer insulating film. The heat treatment temperature is preferably 300 ° C to 350 ° C. After that, the contact hole is opened, and the source / drain extraction electrode 110 is formed by the sputtering method or the like to complete the thin film semiconductor device. (FIG. 1D) Indium tin oxide (ITO) or aluminum (Al) is used for the source / drain extraction electrodes. The substrate temperature during the sputtering of these conductors is about 100 ° C to 250 ° C.
【0039】この様にして試作した薄膜半導体装置のト
ランジスタ特性を測定したところ、ソース・ドレイン電
圧Vds=4V,ゲート電圧Vgs=10Vでトランジ
スタをオンさせた時のソース・ドレイン電流Idsをオ
ン電流IONと定義して、95%の信頼係数でION=(2
3.3+1.73、−1.51)×10-6Aで有った。
又、Vds=4V、Vgs=0Vでトランジスタをオフ
させた時のオフ電流はIOFF=(1.16+0.38、
−0.29)×10-12Aで有った。ここで測定は温度
25℃の元で、チャンネル部の長さL=10μm、幅W
=10μmのトランジスタに対してなされた。飽和電流
領域から求めた有効電子移動度(J.Levinson
et al.J,Appl,Phys.53,119
3’82)は、μ=50.92±3.26cm2/v.s
ecで有った。一方従来技術の低温プロセスpoly−
Si TFTに於いてはION=(18.7+2.24、
−2.09)×10-6A、IOFF=(4.85+3.8
8、−3.27)×10-12Aで有った。この様に本発
明に依り高移動度を有し、ゲート電圧の10Vの変調に
対してIdsが7桁以上も変化し、更にばらつきが小さ
く窮めて優良で均一な薄膜半導体装置を製造し得た。従
ってLCDに本発明の薄膜半導体装置を適応した場合、
LCD画面全体に渡り均一な高画質が得られる事と成
る。The transistor characteristics of the thin-film semiconductor device thus prototyped were measured, and the source-drain current Ids when the transistor was turned on at the source-drain voltage Vds = 4V and the gate voltage Vgs = 10V was determined to be the on-current ION. Is defined as ION = (2
It was 3.3 + 1.73, −1.51) × 10 −6 A.
The off-current when the transistor is turned off at Vds = 4V and Vgs = 0V is IOFF = (1.16 + 0.38,
It was −0.29) × 10 −12 A. Here, the measurement is performed at a temperature of 25 ° C., the length L of the channel portion is 10 μm, and the width W is
= 10 μm transistor. Effective electron mobility (J. Levinson) determined from the saturation current region
et al. J, Appl, Phys. 53, 119
3'82), μ = 50.92 ± 3.26 cm 2 / v. s
It was ec. On the other hand, the conventional low temperature process poly-
In Si TFT, ION = (18.7 + 2.24,
−2.09) × 10 −6 A, IOFF = (4.85 + 3.8)
8, −3.27) × 10 −12 A. Thus, according to the present invention, it is possible to manufacture an excellent and uniform thin film semiconductor device having high mobility, Ids changing by 7 digits or more with respect to the modulation of the gate voltage of 10 V, and having a small variation. It was Therefore, when the thin film semiconductor device of the present invention is applied to an LCD,
It is possible to obtain uniform high image quality over the entire LCD screen.
【0040】[0040]
【発明の効果】以上詳述して来た様に本願発明の電子機
器ではそれに用いられて居る水素含有αタンタルは比抵
抗が低く、内部応力が弱く、且つ延性を呈して居る。そ
れ故以下の如き効果が認められる。As described above in detail, in the electronic device of the present invention, the hydrogen-containing α-tantalum used in the electronic device has a low specific resistance, weak internal stress, and ductility. Therefore, the following effects are recognized.
【0041】(1) 大型電子機器で配線が長くとも比
抵抗が低い為、配線内の電位降下が小さい。即ち電気エ
ネルギーを輸送する際にはその輸送に伴うエネルギー損
失が小さく、又電気信号を伝送する際には正確な信号を
伝送出来る。従って例えば太陽電池に本願発明を適応す
るとエネルギーの変換効率が上がり、又例えば液晶表示
装置に用いると大きな画面全体に渡り美しい表示が得ら
れる事と成る。(1) In a large electronic device, even if the wiring is long, the specific resistance is low, so that the potential drop in the wiring is small. That is, when the electric energy is transported, the energy loss accompanying the transportation is small, and when transmitting the electric signal, an accurate signal can be transmitted. Therefore, when the present invention is applied to, for example, a solar cell, energy conversion efficiency is improved, and when it is used in, for example, a liquid crystal display device, a beautiful display can be obtained over a large screen.
【0042】(2) 電子機器の基板がガラスやセラミ
ックス、プラスッチクと云ったその物性が金属と著しく
異なった物質で有っても断線などが生じにくい。加えて
広い温度範囲でこれらの電子機器の使用が可能と成る。(2) Even if the substrate of the electronic device is a substance such as glass, ceramics, or plastic whose physical properties are remarkably different from that of the metal, disconnection is unlikely to occur. In addition, these electronic devices can be used in a wide temperature range.
【0043】(3) 配線材が延性を呈して居る為、配
線材の膜厚に比して無視し得ぬ段差が有っても容易にこ
れを乗り越えられる。従ってLSIの多層配線やプリン
ト配線基板などに適応すると、配線部位に多少の凹凸が
有ろうとも信頼性の高い配線が得られる。(3) Since the wiring material exhibits ductility, even if there is a step that cannot be ignored compared with the film thickness of the wiring material, it can be easily overcome. Therefore, when it is applied to a multilayer wiring of an LSI, a printed wiring board, or the like, highly reliable wiring can be obtained even if there are some irregularities in the wiring portion.
【0044】(4) イオン注入に於けるイオン阻止能
力に優れて居る。従って上ゲート型TFTのゲート電極
に用いた時、高性能で信頼性の高い薄膜半導体装置と成
る。(4) The ion blocking ability in the ion implantation is excellent. Therefore, when used for the gate electrode of the upper gate type TFT, the thin film semiconductor device has high performance and high reliability.
【0045】(5) 上ゲート型の低温プロセス po
ly−Si TFTに応用した時、従来の製造工程に対
して特別な工程を付加する必要がない。(5) Upper gate type low temperature process po
When applied to the ly-Si TFT, it is not necessary to add a special process to the conventional manufacturing process.
【0046】(6) 上ゲート型の低温プロセス po
ly−Si TFTに応用した時、トランジスタの電気
特性が良い。(6) Upper gate type low temperature process po
When applied to a ly-Si TFT, the electrical characteristics of the transistor are good.
【図1】本発明の一例を示す薄膜半導体装置製造の各工
程に於ける素子断面図。FIG. 1 is a sectional view of an element in each step of manufacturing a thin film semiconductor device showing an example of the present invention.
101…基板 102…下地保護膜 103…半導体膜 104…ゲート絶縁膜 105…ゲート電極 106…イオン注入 107…ソース・ドレイン領域 108…チャンネル領域 109…層間絶縁膜 110…ソース・ドレイン取り出し電極 101 ... Substrate 102 ... Base protection film 103 ... Semiconductor film 104 ... Gate insulating film 105 ... Gate electrode 106 ... Ion implantation 107 ... Source / drain regions 108 ... Channel area 109 ... Interlayer insulating film 110 ... Source / drain extraction electrodes
【手続補正書】[Procedure amendment]
【提出日】平成14年9月9日(2002.9.9)[Submission date] September 9, 2002 (2002.9.9)
【手続補正1】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】発明の名称[Name of item to be amended] Title of invention
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【発明の名称】 薄膜半導体装置及び電子機器Title: Thin film semiconductor device and electronic equipment
【手続補正2】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】特許請求の範囲[Name of item to be amended] Claims
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【特許請求の範囲】[Claims]
【手続補正3】[Procedure 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】0008[Correction target item name] 0008
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【0008】[0008]
【課題を解決するための手段】本発明の薄膜半導体装置
は、基板上に形成された薄膜半導体装置において、基板
上に形成された半導体層と、該半導体層上に形成された
ゲート絶縁層と、該ゲート絶縁層上に形成されたゲート
電極とを有し、該ゲート電極は、10〜5000atm pp
mの濃度の水素を含有するα構造のタンタルで有る事を
特徴とする。さらに、前記基板上に前記半導体層が島状
に形成されている事を特徴とする。また、本発明の薄膜
半導体装置は、基板上に形成された薄膜半導体装置にお
いて、基板上に形成された半導体層と、該半導体層上に
形成されたゲート絶縁層と、該ゲート絶縁層上に形成さ
れたゲート電極とを有し、該ゲート電極は、窒素と10
〜5000atm ppmの濃度の水素を含有するタンタルで
有る事を特徴とする。さらに、前記基板上に前記半導体
層が島状に形成されている事を特徴とする。また、本発
明の電子機器は、基板上に形成された電子機器に於い
て、基板上に形成された配線が10〜5000atm ppm
の濃度の水素を含有するα構造のタンタルで有る事を特
徴とする。また、本発明の電子機器は、基板上に形成さ
れた電子機器に於いて、基板上に形成された配線が、窒
素と10〜5000atm ppmの濃度の水素を含有するタ
ンタルで有る事を特徴とする。本発明は絶縁性物質上に
島状に形成された半導体層と、該半導体層上に形成され
たゲート絶縁層と、該ゲート絶縁層上に形成されたゲー
ト電極とを具備する薄膜半導体装置に於いて、少なくと
も該ゲート電極の一部は水素を含有するα構造のタンタ
ルで有る事を特徴とする。A thin film semiconductor device of the present invention is a thin film semiconductor device formed on a substrate, comprising: a semiconductor layer formed on the substrate; and a gate insulating layer formed on the semiconductor layer. A gate electrode formed on the gate insulating layer, the gate electrode having a thickness of 10 to 5000 atm pp.
It is characterized by being a α-structure tantalum containing hydrogen at a concentration of m. Further, the semiconductor layer is formed in an island shape on the substrate. Further, the thin film semiconductor device of the present invention is a thin film semiconductor device formed on a substrate, wherein a semiconductor layer formed on the substrate, a gate insulating layer formed on the semiconductor layer, and a gate insulating layer formed on the gate insulating layer. A formed gate electrode, the gate electrode comprising nitrogen and 10
It is characterized by being tantalum containing hydrogen at a concentration of up to 5000 atm ppm. Further, the semiconductor layer is formed in an island shape on the substrate. The electronic device of the present invention is an electronic device formed on a substrate, wherein the wiring formed on the substrate is 10 to 5000 atm ppm.
It is characterized by being an α-structure tantalum containing hydrogen at a concentration of. Further, the electronic device of the present invention is characterized in that, in the electronic device formed on the substrate, the wiring formed on the substrate is tantalum containing nitrogen and hydrogen at a concentration of 10 to 5000 atm ppm. To do. The present invention provides a thin film semiconductor device including a semiconductor layer formed in an island shape on an insulating material, a gate insulating layer formed on the semiconductor layer, and a gate electrode formed on the gate insulating layer. At least a part of the gate electrode is made of tantalum having an α structure containing hydrogen.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 29/78 617J 21/88 M Fターム(参考) 2H092 JA25 JA37 KA18 MA05 MA07 MA27 NA15 NA27 NA28 NA29 4M104 AA09 BB17 BB37 DD41 DD43 5F033 HH17 HH19 HH21 HH32 LL01 LL06 NN03 PP06 PP15 PP16 QQ59 QQ61 RR04 SS04 SS15 VV06 VV15 5F052 AA02 AA24 BB01 BB02 BB06 BB07 DA02 DB01 DB02 DB03 DB04 DB07 FA19 HA01 JA01 5F110 AA03 AA26 BB01 BB04 CC02 DD01 DD02 DD13 EE04 EE11 EE44 EE45 EE47 EE48 FF02 FF28 FF30 FF31 GG02 GG13 GG25 GG35 GG42 GG43 GG45 GG47 HJ01 HJ04 HJ12 HJ13 HJ23 HL03 HL07 HL23 HL24 HM03 HM15 NN02 NN23 NN34 NN35 NN40 PP03 PP05 PP10 QQ11 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 29/78 617J 21/88 MF term (reference) 2H092 JA25 JA37 KA18 MA05 MA07 MA27 NA15 NA27 NA28 NA29 4M104 AA09 BB17 BB37 DD41 DD43 5F033 HH17 HH19 HH21 HH32 LL01 LL06 NN03 PP06 PP15 PP16 QQ59 QQ61 RR04 SS04 SS15 VV06 VV15 5F052 AA02 AA24 BB01 EE02 BB02 BB02 BB01 BB06 BB06 BB06 BB06 BB06 BB06 BB06 BB06 BB06 BB06 BB06 BB06 BB06 BB06 BB06 BB01 BB06 BB01 EE45 EE47 EE48 FF02 FF28 FF30 FF31 GG02 GG13 GG25 GG35 GG42 GG43 GG45 GG47 HJ01 HJ04 HJ12 HJ13 HJ23 HL03 HL07 HL23 HL24 HM03 HM15 NN02 NN23 NN34 NN35 NN40 PP03 PP05
Claims (16)
層と、該半導体層上に形成されたゲート絶縁層と、該ゲ
ート絶縁層上に形成されたゲート電極とを具備する薄膜
半導体装置に於いて、 少なくとも該ゲート電極の一部は水素を含有するα構造
のタンタルで有る事を特徴とする薄膜半導体装置。1. A thin film semiconductor including an island-shaped semiconductor layer formed on an insulating material, a gate insulating layer formed on the semiconductor layer, and a gate electrode formed on the gate insulating layer. In the device, at least a part of the gate electrode is tantalum having an α structure containing hydrogen, and a thin film semiconductor device.
層と、該半導体層上に形成されたゲート絶縁層と、該ゲ
ート絶縁層上に形成されたゲート電極とを具備する薄膜
半導体装置に於いて、 該ゲート電極が窒素と水素を含有するタンタルで有る事
を特徴とする薄膜半導体装置。2. A thin film semiconductor comprising an island-shaped semiconductor layer formed on an insulating material, a gate insulating layer formed on the semiconductor layer, and a gate electrode formed on the gate insulating layer. A thin film semiconductor device, wherein the gate electrode is tantalum containing nitrogen and hydrogen.
置の製造方法に於いて、少なくとも水素と窒素とアルゴ
ンを含有する雰囲気下にてスパッター堆積法によりタン
タルを主成分とする薄膜を形成する工程を含む事を特徴
とする薄膜半導体装置の製造方法。3. A method of manufacturing a thin film semiconductor device formed on an insulating material, wherein a thin film containing tantalum as a main component is formed by a sputter deposition method in an atmosphere containing at least hydrogen, nitrogen and argon. A method of manufacturing a thin film semiconductor device, comprising the steps of:
する上側導伝層から成る導伝層を含む薄膜半導体装置の
製造方法に於いて、 下側導伝層を形成する第一工程と、 少なくとも水素とアルゴンを含有する雰囲気下にてスパ
ッター堆積法によりα構造タンタルを主成分とする薄膜
を形成する第二工程とを含む事を特徴とする薄膜半導体
装置の製造方法。4. A method for manufacturing a thin film semiconductor device including a lower conductive layer and an upper conductive layer mainly composed of α-structured tantalum, wherein a lower conductive layer is formed. A method of manufacturing a thin film semiconductor device, comprising: a step; and a second step of forming a thin film containing α-structure tantalum as a main component by a sputter deposition method in an atmosphere containing at least hydrogen and argon.
置の製造方法に於いて、少なくとも窒素とアルゴンを含
有する雰囲気下にてスパッター堆積法によりタンタルを
主成分とする薄膜を形成する第一工程と、 該薄膜に水素化処理を施す第二工程とを含む事を特徴と
する薄膜半導体装置の製造方法。5. A method of manufacturing a thin film semiconductor device formed on an insulating material, wherein a thin film containing tantalum as a main component is formed by a sputter deposition method in an atmosphere containing at least nitrogen and argon. A method of manufacturing a thin film semiconductor device, comprising: a step; and a second step of subjecting the thin film to a hydrogenation treatment.
有る事を特徴とする請求項5記載の薄膜半導体装置の製
造方法。6. The method of manufacturing a thin film semiconductor device according to claim 5, wherein the second step is a hydrogen ion implantation step.
置の製造方法に於いて、 α構造タンタルを主成分とする薄膜を形成する第一工程
と、 該薄膜に水素化処理を施す第二工程とを含む事を特徴と
する薄膜半導体装置の製造方法。7. A method of manufacturing a thin film semiconductor device formed on an insulating material, comprising: a first step of forming a thin film containing α-structure tantalum as a main component; and a second step of subjecting the thin film to hydrogenation treatment. A method of manufacturing a thin film semiconductor device, comprising:
有る事を特徴とする請求項7記載の薄膜半導体装置の製
造方法。8. The method of manufacturing a thin film semiconductor device according to claim 7, wherein the second step is a hydrogen ion implantation step.
電子機器に於いて、 少なくとも該配線の一部は水素を含有するα構造のタン
タルで有る事を特徴とする電子機器。9. An electronic device provided with wiring formed on an insulating material, wherein at least a part of the wiring is tantalum having an α structure containing hydrogen.
る電子機器に於いて、 該配線が窒素と水素を含有するタンタルで有る事を特徴
とする電子機器。10. An electronic device provided with wiring formed on an insulating material, wherein the wiring is tantalum containing nitrogen and hydrogen.
る電子機器の製造方法に於いて、 少なくとも水素と窒素とアルゴンを含有する雰囲気下に
てスパッター堆積法によりタンタルを主成分とする薄膜
を形成する工程を含む事を特徴とする電子機器の製造方
法。11. A method of manufacturing an electronic device having wiring formed on an insulating material, comprising: forming a thin film containing tantalum as a main component by a sputter deposition method in an atmosphere containing at least hydrogen, nitrogen and argon. A method of manufacturing an electronic device, comprising the step of forming.
とする上側導伝層から成る導伝層を含む電子機器の製造
方法に於いて、 下側導伝層を形成する第一工程と、 少なくとも水素とアルゴンを含有する雰囲気下にてスパ
ッター堆積法によりα構造タンタルを主成分とする薄膜
を形成する第二工程とを含む事を特徴とする電子機器の
製造方法。12. A method of manufacturing an electronic device including a conductive layer composed of a lower conductive layer and an upper conductive layer mainly composed of α-structure tantalum, the first step of forming the lower conductive layer. And a second step of forming a thin film containing α-structure tantalum as a main component by a sputter deposition method in an atmosphere containing at least hydrogen and argon.
る電子機器の製造方法に於いて、 少なくとも窒素とアルゴンを含有する雰囲気下にてスパ
ッター堆積法によりタンタルを主成分とする薄膜を形成
する第一工程と、 該薄膜に水素化処理を施す第二工程とを含む事を特徴と
する電子機器の製造方法。13. A method of manufacturing an electronic device having wiring formed on an insulating material, wherein a thin film containing tantalum as a main component is formed by a sputter deposition method in an atmosphere containing at least nitrogen and argon. A method of manufacturing an electronic device, comprising: a first step; and a second step of subjecting the thin film to a hydrogenation treatment.
で有る事を特徴とする請求項13記載の電子機器の製造
方法。14. The method of manufacturing an electronic device according to claim 13, wherein the second step is a hydrogen ion implantation step.
製造方法に於いて、 α構造タンタルを主成分とする薄膜を形成する第一工程
と、 該薄膜に水素化処理を施す第二工程とを含む事を特徴と
する電子機器の製造方法。15. A method of manufacturing an electronic device formed on an insulating material, comprising: a first step of forming a thin film containing α-structure tantalum as a main component; and a second step of subjecting the thin film to hydrogenation treatment. A method for manufacturing an electronic device, comprising:
で有る事を特徴とする請求項15記載の薄膜半導体装置
の製造方法。16. The method of manufacturing a thin film semiconductor device according to claim 15, wherein the second step is a hydrogen ion implantation step.
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