JP2003153086A - Solid-state image pickup device and its drive method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device capable of thinning out a signal electric charge at an arbitrary location and number without changing a position of a drain or a control gain. SOLUTION: A solid-state image pickup device has a plurality of photodiodes 1 formed in a matrix shape on a semiconductor substrate; a vertical register 3 which controls the number of steps at a vertical transfer clock to transfer a signal electric charge read out from this photodiode in a column direction; and a horizontal register 4 which controls the signal electric charge transferred by this vertical register 3 by a horizontal transfer electrode arrayed by repeating alternately electrodes 10a, 10b, 10c, 10d of a first phase and a second phase to transfer in a horizontal direction. A combination of timings of the vertical transfer clock and a horizontal transfer clock is changed, and the signal electric charges from the photodiode 1 at a position in an arbitrary line and an arbitrary column transferred in the vertical register 3 are discharged into a drain 6. The residual signal electric charges are read out through the horizontal register 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device used as an image pickup device such as a digital still camera and a digital video camera, and a driving method thereof.

[0002]

2. Description of the Related Art In recent years, image quality of digital still cameras has been rapidly advanced, and solid-state image pickup devices having a pixel number of 1 million pixels or more, particularly CCD image sensors, have been widely used. These CCD image sensors are generally used in three driving methods of a still mode, a monitoring mode, and an autofocus mode. The still mode is a drive mode in which a still image is obtained by reading out the signal charges of all pixels independently, the monitoring mode is a drive mode in which a moving image is displayed on a liquid crystal monitor, etc., and the autofocus mode is a part of the signal of the CCD image sensor. This is a drive mode in which auto focus and exposure control are performed using the same.

To drive in the monitoring mode, a frame rate of about 30 frames per second is required. However, when the signal charges from all the photodiodes are displayed on the monitor liquid crystal, the CCD image sensor, which has a large number of pixels, has a limitation on the driving frequency, and there is a demand for low power consumption. Therefore, the frame rate in the monitoring mode decreases. To do. Therefore, in general, in a CCD image sensor having a pixel number of 1 million pixels or more, not only all the rows but only the signal charges from the photodiodes on a specific row are read out and the number of lines is thinned out to display a frame. The rate is improving. In driving in the autofocus mode, the signal charge from the photodiode in the central portion is mainly used for control processing, and quick response is required. Therefore, as in the case of the monitoring mode, high-speed processing is achieved by reading out only the signal charges from the photodiodes on the specific row in the central portion.

FIG. 12 is a schematic diagram showing a conventional example of a driving method of a CCD image sensor. This CCD image sensor adopts a progressive scan method having a four-phase driving vertical register, is equipped with a photodiode 51, a transfer gate 52, a vertical register 53 and a horizontal register 54, and is connected to a charge discharging section 57 to eliminate unnecessary charges. The drain 56 for discharging each row and the control gate 55 for controlling the discharge of electric charges,
3 is provided at the boundary between the horizontal register 54 and the horizontal register 54 to improve the frame rate. In addition, 58 is a horizontal register 5
4 is a charge detection unit that detects the signal charge output from 4. As another conventional example, a CCD image sensor having the drain 56 and the control gate 55 provided adjacent to the lower edge of the horizontal register 54, and a drain and a control gate for discharging unnecessary charges are provided at a specific vertical column end. There is a CCD image sensor that is provided between the vertical section and the horizontal register, prohibits the transfer of signal charges from the vertical register to the horizontal register, and thins out pixels in column units to improve the frame rate.

[0005]

In the conventional driving method of the CCD image sensor described above, the signal charges from the photodiodes 51, 51, ... Arranged in a matrix can be thinned out in a high degree of freedom in units of rows. However, if the signal charges from the photodiodes are to be thinned out in columns, a drain for discharging unnecessary charges and a control gate for controlling the discharge of charges are provided at the lower end of the photodiode column corresponding to the signal charges to be thinned out. There is a need. In other words, it is necessary to change and provide the electrode forming pattern for the drain for discharging the unnecessary charges and the control gate in accordance with the position of the column to be thinned out. It must be done early in the sensor manufacturing process. Therefore, when the columns to be thinned out are different, a dedicated CCD image sensor provided with a drain and a control gate is required according to the position of the column, and conversely, in the dedicated CCD image sensor, the columns to be thinned out are fixed. There is a problem that it can not be changed.

Therefore, an object of the present invention is to change the positions of the drain and the control gate according to the method of thinning out the signal charge, and to change an arbitrary position and an arbitrary position by only slightly changing the process and changing the driving timing. It is an object of the present invention to provide a solid-state imaging device capable of thinning out signal charges by the number of, and capable of performing a variety of reading modes and frame rates and performing reading with a high degree of freedom, and a driving method thereof.

[0007]

In order to achieve the above object, a solid-state image pickup device according to the present invention comprises a plurality of light receiving portions formed in a matrix on a semiconductor substrate, and signal charges read from the light receiving portions. A plurality of vertical registers for transferring the signal charges in the vertical direction and a horizontal direction in which the electrodes of the first phase and the second phase are alternately arranged in order to transfer the signal charges transferred by the plurality of vertical registers in the horizontal direction. In a solid-state imaging device having a register, a charge discharging unit capable of discharging the signal charges transferred in the plurality of vertical registers in row units and column units, and the signal discharging unit discharges the signal charges in column units. It is characterized in that it is provided with a charge reading means for reading out the signal charges in the remaining columns other than the columns from which the signal charges have been discharged in the row discharged in step 1. With this configuration, the position and number of rows and columns to be read can be arbitrarily changed without changing the positions of the drain and the control gate according to the thinning method, and only by changing the drive timing. Various frame rates can be realized, and thinning readout with a high degree of freedom becomes possible.
In one embodiment, the charge discharging means is composed of a drain and a gate that are arranged adjacent to each other near the end of the vertical register, and the second phase electrode of the horizontal register is connected to the gate. Further, in one embodiment, the charge reading means is a horizontal register formed of electrodes of the first phase. Further, in one embodiment, the charge discharging unit and the charge reading unit function according to the voltage of the electrodes of the first phase and the second phase of the horizontal register. Further, in one embodiment, the first and second phase electrodes of the horizontal register are set as one set, and a plurality of sets of electrodes are provided, and the plurality of sets of electrodes are wired so as to be independently drivable. There is. With this configuration, the position and number of rows and columns to be read can be arbitrarily changed without changing the positions of the drain and the control gate according to the thinning method, and only by changing the drive timing. Various frame rates can be realized, and thinning readout with a high degree of freedom becomes possible.

In one embodiment, the positions of the electrodes of the first phase and the second phase of the plurality of sets are arbitrarily changed in the horizontal register by changing the formation position of the contact connecting the electrode and the wiring. it can. As a result, it is possible to realize a CCD image sensor capable of thinning out any column unit with only a slight change in the process depending on the thinning method.

A solid-state image pickup device driving method according to the present invention is the solid-state image pickup device driving method, wherein the first horizontal register is provided while the signal charges are transferred in the vertical register.
When the electrode of the first phase is at the high level and the electrode of the second phase is at the low level in the phase and the second phase electrodes, the signal charges are read out to the horizontal register row by row, and the first phase When the electrode of 1 is at the low level and the electrode of the second phase is at the high level, the signal charges are discharged to the drain of the charge discharging means in units of rows. Further, in the driving method according to the embodiment, the signal charges are discharged in a predetermined column unit by independently driving the electrodes of the first phase and the second phase of the plurality of sets of horizontal registers. With such a driving method, it is possible to change the location and the number of rows and columns to be read by only changing the driving timing without changing the positions of the drain and the control gate according to the thinning method.
Various readout modes and various frame rates can be realized, and thinning readout with a high degree of freedom becomes possible.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a schematic configuration diagram showing a first embodiment of a CCD image sensor as a solid-state imaging device of the present invention. This CCD image sensor is an interline transfer type having a four-phase driving vertical register and adopting a progressive scan system, and photodiodes 1 as light receiving portions arranged in a matrix,
A transfer gate 2 for transmitting the signal charge from the photodiode 1, a vertical register 3 for vertically transferring the signal charge received via the transfer gate 2, and electrodes 10a, b; 10e of the first phases φH1A, φH1B. , f and the second phase φ
H2A (φH1A inversion pulse), φH2B (φH1B inversion pulse) electrodes 10c, d; 10g, h are arranged alternately and repeatedly,
The horizontal register 4 is provided for horizontally transferring the signal charges received from the vertical register 3. In the present embodiment, for the sake of convenience, the photodiodes 1 arranged in 7 rows and 6 columns are
1, ... will be described.

The vertical register 3 has four vertical transfer electrodes 9a to 9d to which the vertical transfer clocks .phi.V1 to .phi.V4 are input.
(See FIG. 2) and the vertical transfer electrode 9a to which the clock φV1 is input also serves as the transfer gate 2. Then, when a read pulse V _H rises in the vertical transfer clock φV1 at time t0 in FIG. 3, signal charges are read out from all the photodiodes 1 to the vertical register 3 via the transfer gates 2, and from time t1 in FIG. When the vertical transfer clocks .phi.V1 to .phi.V4 are input with the waveform and timing shown at t2, the read signal charges are transferred one stage vertically downward in the vertical register 3.

The horizontal register 4 is driven by two terminals by two-phase horizontal transfer clocks φH1 and φH2 (inversion pulse of φH1), which is different from the conventional example shown in FIG. 12, and the two-phase horizontal transfer clocks φH1A and φH2A; Driven by 4 terminals by φH1B and φH2B, and when each horizontal transfer clock is inverted immediately after time t2 in FIG. 3, the signal charges for one row are transferred horizontally to the left, and the transferred signal charges are transferred to the charge detection unit 8 Are sequentially converted into a signal voltage by and output to a signal processing circuit (not shown) or the like. The horizontal transfer electrodes 10a, b; 10e, f to which the horizontal transfer clocks of the first phases φH1A, φH1B are input are defined by claims 1, 3, 4
Of the horizontal transfer electrodes 10a,
b; 10e, f and the horizontal transfer electrodes 10c, d; 10g, h to which the second phases φH2A, φH2B are input are wired as described in claim 5. As described above, the one-stage vertical transfer of signal charges and the horizontal transfer of one row are performed by the photodiode 1 as shown in FIG.
Is repeated for the number of rows (7 times in this embodiment) to obtain a signal voltage for one frame.

Between each vertical register 3 and horizontal register 4, as shown in FIG. 1, a gate 5 as a charge discharging means for discharging the signal charges transferred in the vertical register 3 in units of rows and columns. A charge discharging unit 7 having a drain and a drain 6 is provided. Each gate 5 has a second phase φH2A; φ
Each of the horizontal transfer electrodes 10c, d; 10g, to which H2B;
connected to h; ... The signal charge from the vertical register 3 is
As described in claim 7, the electrodes 10a, b; 10e, f of the first phases φH1A, φH1B are at high level (H level), and the second phase φ
When the electrodes 10c, d; 10g, h of H2A, φH2B are low level (L level), they are transferred to the horizontal register 4, and conversely, the electrodes 10a, b; 10e, f of the first phases φH1A, φH1B are L level. At the level, when the electrodes 10c, d; 10g, h of the second phases φH2A, φH2B are at the H level, they are discharged to the drain 6.

FIG. 2 is a plan view showing a specific structural example of the charge discharging section 7. In FIG. 2, vertical transfer electrodes 9 a to 9 d to which four-phase vertical transfer clocks φV 1 to φV 4 are applied are vertically arranged on the vertical register 3 in a direction orthogonal to the vertical register 3. Vertical transfer clock φV2, φV4
The vertical transfer electrodes 9b and 9d (shown by the alternate long and short dash line in the figure) to which is applied are polysilicon of the first layer, and the vertical transfer clock φV
Vertical transfer electrode 9c to which 3 is applied (shown by a chain double-dashed line in the figure)
Is the second layer of polysilicon, and the vertical transfer electrode 9a (shown by the solid line in the figure) to which the vertical transfer clock φV1 is applied is 3
Each of the layers is made of polysilicon.

On the other hand, the horizontal register 4 is composed of four horizontal transfer electrodes each connected to each vertical register 3, and the vertical register 3 at the left end in the figure has horizontal transfer electrodes 10a, 10b ,.
Horizontal transfer electrodes 10e, 10f, 10g, and 10h are connected to the vertical register 3 on the right, respectively. Further, the horizontal transfer clock φH1A of the first first phase is applied to the horizontal transfer electrodes 10a, 10b (10a, b in FIG. 1), and the horizontal transfer electrodes 10c, 10d (10c, d in FIG. 1) are applied to the horizontal transfer electrodes 10c, 10d. The horizontal transfer clock φH2A of the first and second phases, which is the inverted clock thereof, is supplied to the horizontal transfer electrodes 10e and 10f (10e and f of FIG. 1) by the horizontal transfer clock φH1B of the second first phase. Horizontal transfer electrode 10
The horizontal transfer clock φH2B of the second second phase, which is the inverted clock thereof, is input to g and 10h (10g and h in FIG. 1). Horizontal transfer electrodes 10a, 10c, which are indicated by two-dot chain lines in the figure,
10e and 10g are formed of the second layer of polysilicon, and the channel therebelow is used as an N-type transfer channel, while the horizontal transfer electrodes 10b, 10d, 10f and 10h shown by the solid lines in the figure are used.
Is formed of polysilicon of the third layer, and a channel below it is an N ⁻ type channel, and a step is provided in the potential under the gate of each transfer clock so that two-phase driving can be performed.

The charge discharging section 7 (shown by a broken line in the figure) including the gate 5 and the drain 6 selectively thins and discharges the signal charges transferred in the row direction transferred from each vertical register 3. As shown in FIG. 1, the photodiodes 1 are arranged in a primary color Bayer array which is a general color filter. In the example shown in FIGS. 1 and 2, each vertical register 3
The signal charges arranged in the row direction at the lower end of the
In order to thin out, horizontal transfer electrodes 10a, 10b, 10c, 10 connected to the vertical register 3 in the leftmost column corresponding to the pixels to be left
d is the horizontal transfer clock φH1A for the first and second phases,
Inputting φH2A, the horizontal transfer electrodes 10e, 10f, 10 connected to the adjacent two columns of vertical registers corresponding to the pixels to be discharged.
The horizontal transfer clocks φH1B and φH2B of the second first and second phases are input to g, 10h; Each gate 5 has a vertical transfer electrode 9d as shown in FIG.
Drain 6 by providing an opening (via hole) in
Is connected to the horizontal transfer electrodes 10d, ... Which are integrally formed of the same polysilicon layer and to which the horizontal transfer clock φH2A is input. A voltage VD is applied to each drain 6 so that its potential becomes deeper than the potential of the vertical register 3.

The horizontal transfer clock φH2A (φH2B) is applied to the gate 5 through the horizontal transfer electrode 10d.
When the voltage of the horizontal transfer clock φH2A (φH2B) is “L” level and the voltage of the horizontal transfer clock φH1A (φH1B) applied to the horizontal transfer electrodes 10a and 10b is “H” level, the potential of the gate 5 is a vertical register. Since the potential of the horizontal transfer electrodes 10b and 10f becomes deeper than the potential of the vertical register 3, the signal charge transferred to the vertical register 3 becomes
It is directly transferred to the horizontal register 4. On the other hand, the horizontal transfer clock φH2A applied to the horizontal transfer electrode 10d (10h)
(φH2B) voltage is "H" level, horizontal transfer electrodes 10a, 1
When the voltage of the horizontal transfer clock φH1A (φH1B) applied to 0b is at the “L” level, the potential of the gate 5 becomes deeper than the potential of the vertical register 3, and the potentials of the horizontal transfer electrodes 10b and 10f become vertical. It becomes shallower than the potential of the vertical register 3
Is transferred to the drain 6 having a potential deeper than that of the gate 5.
In this way, the signal charges corresponding to the pixels are vertically arrayed according to the voltage levels “H” and “L” of the first phase horizontal transfer clock φH1A (φH1B) and the second phase horizontal transfer clock φH2A (φH2B). It can be selectively thinned out in units. In the present embodiment, the signal charges arranged in the row direction can be selected for every three columns and transferred to the horizontal register 4, and the remaining two columns can be discharged to the drain 6.

The driving method of the CCD image sensor described with reference to FIGS. 1 and 2 will be described with reference to the timing charts of FIGS. 3 to 5 for two modes of all-pixel reading (still mode) and pixel thinning. In FIG. 3 showing the driving timing of the all-pixels reading mode, when the reading pulse V _H of “H” is applied to the vertical transfer clock φV1 at time t0, the signal charges are read out from the photodiodes 1 of all the pixels to the vertical register 3. Be done. When a series of vertical transfer clocks .phi.V1 to .phi.V4 are applied at times t1 to t2, the signal charges are transferred downward in the vertical register 3 by one stage.
Since the first phases φH1A and φH1B of the horizontal transfer clock are at “H” level and the second phases φH2A and φH2B are at “L” level, the signal charges in the first row are not thinned out in the horizontal direction and the horizontal register 4 Are all transferred to.

Next, when the levels of the first and second phases of the horizontal transfer clock are inverted at times t2 to t3, the signal charges for one row are transferred horizontally and become a signal voltage from the charge detection unit 8. Is output. Further, from time t3 to t4, from time t1 to
Vertical and horizontal transfer signals of the same pattern as t2 φV1 to φV4, φH
By applying 1A to φH2B, the signal charges of the second row are transferred from the vertical register 3 to the horizontal register 4 without being thinned out in the row direction, and at the times t4 to t5, the vertical pattern of the same pattern as the times t2 to t3 is applied. By applying the horizontal transfer signal, the charge detection unit 8
Is output as a signal voltage. By repeating such transfer of signal charges for the number of rows of the photodiode array (7 times in this embodiment), the signal charges of all pixels are read out.

FIG. 4 shows the drive timing in the pixel thinning readout mode, and FIG. 5A shows the pixel color filter array and the horizontal register electrode configuration at that time as shown in FIGS.
(k) shows potential diagrams of the horizontal registers, respectively. In FIG. 4, when a read pulse V _H is applied to the vertical transfer signal φV1 at time t0, signal charges are read out from the photodiodes 1 of all pixels to the vertical register 3.
At time t1 to t2, when a series of vertical transfer clocks φV1 to φV4 having the same pattern as that at time t1 to t2 in FIG. 3 is applied, the signal charges are transferred downward in the vertical register 3 by one stage. Compared to the case of Fig. 3, the horizontal transfer clock φH1A
Is the same at "H" level and φH2A is at "L" level.
Horizontal transfer clock φH1B is “L” level, φH2B is “H”
Inverted to the level. Therefore, among the signal charges in the first row shown in FIG. 5A, R11 and G14 are transferred to the horizontal register 4, but the other signal charges G12, R13, R15 and G16 are discharged to the drain 6.

At time t3 in FIG. 4, φH1A is at "L" level,
When φH2A is inverted to the “H” level, R11 and G14 of the signal charges transferred to the horizontal register 4 are horizontally shifted by half a bit, and the signal charges for one row at the lower end of the vertical register 3 are All are ready to be drained. Next, from time t3 to t4, while maintaining the level of the horizontal transfer clock, a series of vertical transfer clocks φV1 to φV4 having the same pattern as those at times t1 to t2 are applied twice to lower the signal charge in the vertical register. And the signal charges corresponding to the pixels in the second and third rows for two rows are all discharged to the drain 6. When φH1A returns to “H” level and φH2A returns to “L” level at time t4, time t1
At the time t5 when the application of a series of vertical transfer clocks of the same pattern as the times t1 to t2 ends, G41 and B44 of the signal charges in the fourth row are transferred to the horizontal register 4 and other signal charges are transferred. B42, G43, G45 and B46 are discharged to the drain 6.

At time t6, when φH1B is inverted to the “H” level and φH2B is inverted to the “L” level, the signal charges R11 and G14 in the horizontal register 4 are shifted by half a bit as shown in FIG. 5 (e). , At time t7, φH1B returns to “L” level, φH2B returns to “H” level, and φH1Aφ returns to “L” level, H2.
When A is inverted to the "H" level, the signal charges R11, G41, G14, B44 in the horizontal register 4 are further shifted by half a bit as shown in FIG. It is ready to discharge all the signal charges for one row to the drain 6. Below, from time t7 to t11, from time t3 to
The same operation as t7 is performed. First, in the two-stage vertical transfer from time t7 to t8, all the signal charges of the fifth and sixth rows are discharged to the drain 6, and then from time t8 to t11, the seventh row. Only R71 and G74 of the signal charges of FIG. 5 are transferred to the horizontal register 4 and then the signal charges R11, G41, G14 and B44 in the horizontal register 4 are transferred to the horizontal register 4 as shown in FIG. ), The signal charge R11,
G41, R71, G14, B44 and G74 are half-bit shifted as shown in FIG. 5 (j). At time t12 in this series of operations, as shown in FIG. 5 (k), in the horizontal register 4, the number of signal charges arranged in the row direction on the column selected every three columns becomes 3
Six signal charges selected for each pixel are R11, G4
1, R71, G14, B44, G74 are arranged in order, and time t12 to t13
Then, when the vertical and horizontal transfer clocks shown in the figure are applied, the signal charges are transferred by the charge detection unit 8 by horizontal transfer for one row.
Is output to and converted into a voltage signal. After that, the operation of thinning and transferring the signal charges in the vertical and horizontal directions is repeated for each frame, that is, for every 7 rows.

In the pixel thinning-out reading mode described above, pixels are read out at a rate of 1/3 in the row direction and 1/3 in the column direction by pixel thinning, thereby increasing the frame rate to about 9 times that in the all-pixel reading mode. You can According to the configuration of the CCD image sensor of the above embodiment, the all-pixel reading mode and the pixel thinning reading mode can be selected by switching the driving timing of the vertical and horizontal transfer electrodes, and a high frame rate is realized in the pixel thinning reading mode. be able to.

FIG. 6 is a schematic configuration diagram showing a second embodiment of the CCD image sensor of the present invention. In this CCD image sensor, horizontal transfer clocks φH1A and φH2A are applied to one electrode for every five horizontal transfer electrodes arranged in the row direction, and horizontal transfer clocks φH1B and φH2 are applied to the remaining five electrodes.
The point that B is applied is different from the first embodiment described in FIG. In the example of FIG. 6, the horizontal transfer clocks φH1A and φH2A are applied to the left end and the fifth horizontal electrode from the left end.

The drive timing of the all-pixel read mode is exactly the same as that of the first embodiment shown in FIG. 3, and the application of the read pulse V _H at time t0 is followed by the vertical transfer from time t1 to t2. The horizontal transfer from time t2 to t3 is alternately repeated seven times to obtain the signal charge for one frame. FIG. 7 shows the drive timing in the pixel thinning readout mode in the CCD image sensor of FIG.
This drive timing is different from that of the first embodiment described with reference to FIG. 4 in that a series of vertical and horizontal transfer operations of the same pattern as times t4 to t8 in FIG. 4 is repeated at times t12 to t16.
The only difference is that it is increased twice as shown at t16 to t20.
Therefore, in the pixel thinning readout mode of the present embodiment,
By the same operation as described in the first embodiment, pixels are selected at a rate of ⅓ in the column direction and ⅕ in the row direction by thinning and are sent to the charge detection unit 8 as signal charges for one row. , Frame rate is about 1 in all pixel readout mode
It can be increased 5 times. Although not shown, times t3 to t4, t7 to t8, t11 to t12, t15 to t16, t19 to t20.
The number of pulses of each vertical transfer clock φV1 to φV4 in
By changing the number from four to four, pixels can be read out at a rate of ⅕ in the column direction and ⅕ in the row direction by thinning, and the frame rate can be increased to about 25 times that in the all-pixel reading mode.

As described above, by changing the form of application of the horizontal transfer clock to the horizontal transfer electrodes by, for example, changing the contact process during manufacturing of the CCD image sensor, the thinning-out form in the row direction can be freely changed. The thinning mode in the column direction can be freely changed only by changing the combination of the timings of the horizontal transfer clock and the vertical transfer clock to be applied.

FIG. 8 is a schematic configuration diagram showing a third embodiment of the CCD image sensor of the present invention. This CCD image sensor is used when the signal charges are read from only one part such as the central part of the pixel area in the modes of autofocus and exposure control. In the CCD image sensor, horizontal transfer clocks φH1A and φH2A are applied to the center two horizontal transfer electrodes φH1A and φH2A, and horizontal transfer clocks φH1B and φH2B are applied to each two of the two horizontal electrodes. This is the difference from the first embodiment shown in FIG.

Since the driving timing of the all-pixels reading mode is exactly the same as that of the first embodiment shown in FIG. 3, its explanation is omitted. FIG. 9 shows the drive timing of the pixel thinning readout mode in the CCD image sensor of FIG. 8, and FIG. 10 (A) shows the color filter array of the pixels and the electrode structure of the horizontal register at that time as shown in FIGS. (j)
Shows the potential diagrams of the horizontal registers, respectively.
In FIG. 9, when the read pulse V _H is applied to the vertical transfer signal φV1 at time t0, the signal charges are read from the photodiodes 1 of all the pixels to the vertical register 3. At times t1 to t2, when the vertical transfer clocks φV1 to φV4 having the same pattern as at times t1 to t3 in FIG. 3 are applied twice, the signal charges are transferred downward in the vertical register 3 by two stages. Since the horizontal transfer clocks φH2A, φH2B are at “H” level and the horizontal transfer clocks φH1A, φH1B are at “L” level, all the left electrodes of the horizontal transfer electrodes forming a pair in FIG. 8 are at “L” level. All the signal charges of the pixels in the first row and the second row are discharged to the drain 6.

At time t3 in FIG. 9, φH1A is at "H" level,
φH2A is inverted to the “L” level, and from time t3 to t4,
When a series of vertical transfer clocks φV1 to φV4 is applied once, the signal charges in the third row at the lower end of the vertical register 3 are
With respect to the horizontal register 4, the signal charge R33 corresponding to the center two pairs of horizontal transfer electrodes whose left electrode is at "H" level,
Only G34 is transferred as shown in FIG. 10 (a), and the signal charges R31, G32, R35, G36 corresponding to the other horizontal transfer electrode pairs whose left electrodes are at "L" level are all transferred to the drain 6. Is discharged. At times t4 to t6, when the levels of the horizontal transfer clocks φH1A to φH2B shown in FIG. 9 are inverted three times on the horizontal transfer electrodes, the signal charges R33 and G34 in the horizontal register 4 are transferred to the horizontal transfer electrodes shown in FIGS. ), Shifts one bit and a half, and
At 7, φH1A is inverted to "H" level, and φH2A is inverted to "L" level, and from time t7 to t8, a series of vertical clocks φV1 to φV4
Is applied once, among the signal charges in the fourth row, only the signal charges G43 and B44 in the central portion are transferred to the horizontal register 4 as shown in FIG. 10D, and the other signal charges G41 and B42. , G45,
B46 is discharged to the drain 6.

At time t9, when the horizontal transfer clock φH1B is inverted to the “H” level and φH2B is inverted to the “L” level, the signal charges R33 and G34 in the horizontal register 4 move in the horizontal direction as shown in FIG. A half bit shift to, then at time t10
By the time the level of each horizontal transfer clock φH1A to φH2B is inverted three times, the signal charges R33, G34, G in the horizontal register 4 are
43 and B44 are shifted by one and a half bits in the horizontal direction as shown in FIG. Then, at time t11, φH1A is inverted to the “H” level and φH2A is inverted to the “L” level, and when a series of vertical rotation clocks φV1 to φV4 is applied once by time t12, the vertical register 3 is moved down one stage. Of the signal charges on the fifth row transferred to the horizontal register 4, only the central signal charges R53 and G54 are transferred to the horizontal register 4 as shown in FIG.
51, G52, R55 and G56 are discharged to the drain 6. When the horizontal transfer clocks φH1B and φH2B are inverted at time t13, the signal charges R33, G34, G43, in the horizontal register 4 are inverted.
B44 is shifted by half a bit in the horizontal direction as shown in FIG. 10 (h), and each horizontal transfer clock φH1A to
When φH2B repeats inversion three times, the signal charges R33, G34, G43, B44, R53, G54g in the horizontal register 4 become as shown in FIG.
One half bit shift is performed in the horizontal direction as shown in FIG.

Next, at times t14 to t15, when a series of vertical clocks φV1 to φV4 are applied twice, the vertical register 3
The signal charges on the 6th and 7th rows transferred downward by two stages are
The level of the horizontal transfer clocks φH2A to φH2B changes from time t1 to t2.
Therefore, all are discharged to the drain 6. By the above read operation, at time t15, as shown in FIG. 10 (j), the signal charges R33, G34, G43, B44, R53, from the central 3 rows and 2 columns of the pixels of FIG. 8 are stored in the horizontal register 4. G54 is arranged in order. Finally, from time t15 to t16, normal horizontal transfer is performed, and the signal charges of the above-described 3 rows and 2 columns in the central portion of the pixel are output through the charge detection unit 8 within the transfer time of one line. In the thinned-out read mode of this embodiment,
It is possible to output a signal in the central part 3 rows 2 columns of the pixel portion at a frame rate about 7 times as high as that in the all pixel reading mode. Thus, according to the configuration of the CCD image sensor,
Only by switching the drive timing, the all-pixel reading mode or the reading mode of the central portion of the pixel portion can be selected. C
When controlling the autofocus and the exposure by using the signal of the CD image sensor, the charge signal of the central portion of the pixel is mainly used for the processing. Therefore, the readout mode of the central portion of the pixel allows the autofocus and the exposure at a high response speed. Control can be performed.

FIG. 11 is a schematic block diagram showing a fourth embodiment of the CCD image sensor of the present invention. This CCD
The image sensor is a combination of the above-described first and third embodiments, and only by switching the drive timing, it is possible to perform three types of reading, that is, the all-pixel reading mode, the thinning-out reading mode, and the central reading mode. The CCD image sensor has a horizontal transfer clock of φH1C,
It differs from the first embodiment in FIG. 1 in that it is divided into four sets of H2C, φH1D, φH2D, φH1E, φH2E, φH1F, and φH2F.

In the above-mentioned CCD image sensor, the all-pixel reading mode is the horizontal transfer pulse φH1C, φ shown in FIG.
The same drive pulse as the horizontal transfer pulse φH1A of FIG. 3 of the first embodiment is applied to H1D, φH1E, and φH1F, and the same drive pulse as the horizontal transfer pulse φH2A of FIG. 3 is applied to the horizontal transfer pulses φH2C, φH2D, φH2E, and φH2F of FIG. This is done by giving a pulse. In the thinning readout mode, φH1C and φH1E in FIG. 11 have φH1A in FIG. 4, and φH2C and φH2E in FIG. 11 have φH2A in FIG.
, ΦH1D and φH1F in FIG. 11, φH1B in FIG. 4, and φ in FIG.
This is performed by applying the same drive pulse to H2D and φH2F as that of φH2B in FIG. By this, 1 / in the column direction
3, 1/3 pixels can be thinned out in the row direction, and the frame rate can be increased to about 9 times that in the all-pixel reading mode. Further, the central reading mode is φ in FIG.
H1E and φH1F are φH1A shown in FIG. 9, φH2E and φH2F are φH2A shown in FIG. 9, φH1C and φH1D are φH1B shown in FIG.
The same driving pulse as that of φH2B is applied to φH2C and φH2D of FIG.
It is possible to output signals in rows and columns.

According to the CCD image sensor having the above-described structure, by switching the driving timing, it is possible to select three reading modes, that is, all-pixel reading, thinning-out reading, and pixel-center-reading. For example, if these three types of read modes are used in a digital still camera, still mode drive that independently reads the signal charges of all pixels to obtain a still image, monitoring mode drive that displays a moving image on a liquid crystal monitor, autofocus and exposure It is possible to easily select and use the auto focus mode drive for controlling.

In the above embodiment, the present invention has been described with respect to the primary color Bayer array, which is one of the general color filter arrays, but the present invention also applies to filters arranged in a repetition other than 2 rows and 2 columns. Applicable. Further, the present invention is
Progressive scan type interline transfer CCD having the 4-phase drive vertical register described in the above embodiment
Not limited to image sensors, other than 4-phase drive vertical registers,
Alternatively, it can be applied to CCD image sensors other than the interline transfer type. Further, the same effect can be obtained by applying the present invention to each field constituting a frame not only for the progressive scan method but also for the interlaced method CCD image sensor. The present invention is directed to charge discharging means and CCDs other than those described in the above embodiments.
An image sensor driving method can also be applied.

[0036]

As is apparent from the above description, according to the solid-state image pickup device and its driving method of the present invention, the configurations of the drain and the control gate are changed according to the method of thinning out the signal charges from the light receiving portion. Instead, the number of read lines in the column direction, the number of read pixels in the row direction, or the read position can be changed by only a slight change in the manufacturing process and the drive timing, and there is a high degree of freedom in selecting various read modes and frame rates. It is possible to realize a solid-state imaging device.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a CCD image sensor according to a first embodiment of the present invention.

FIG. 2 is a detailed view of the vicinity of a horizontal register of the CCD image sensor of the first embodiment.

FIG. 3 is a drive timing chart in the all-pixel reading mode of the CCD image sensor of the first embodiment.

FIG. 4 is a driving timing chart in a thinning-out reading mode of the CCD image sensor of the first embodiment.

5A and 5B are a schematic configuration diagram and a potential diagram of the CCD image sensor for explaining a thinning-out reading mode of the CCD image sensor of the first embodiment.

FIG. 6 is a schematic configuration diagram showing a CCD image sensor according to a second embodiment of the present invention.

FIG. 7 is a drive timing chart in a thinning-out reading mode of the CCD image sensor of the second embodiment.

FIG. 8 is a schematic configuration diagram showing a CCD image sensor according to a third embodiment of the present invention.

FIG. 9 is a drive timing chart in the central portion readout mode of the CCD image sensor of the third embodiment.

FIG. 10 is a schematic configuration diagram and a potential diagram of a CCD image sensor for explaining a central reading mode of the CCD image sensor of the third embodiment.

FIG. 11 is a schematic configuration diagram showing a CCD image sensor according to a fourth embodiment of the present invention.

FIG. 12 is a schematic configuration diagram showing a conventional CCD image sensor.

[Explanation of symbols]

1 Photodiode 2 transfer gates 3 Vertical register 4 Horizontal register 5 gates 6 drain 7 Charge discharging section 8 Charge detector 9a-9d Vertical transfer electrodes 10a, b-10g, h Horizontal transfer electrode φV1 to φV4 Vertical transfer clock φH1A to φH2B Horizontal transfer clock

Claims (8)

[Claims] 1. A plurality of light receiving portions formed in a matrix on a semiconductor substrate, a plurality of vertical registers for vertically transferring signal charges read from the light receiving portions, and a plurality of vertical registers for transferring the signal charges. In the solid-state imaging device having a horizontal register in which electrodes of the first phase and the electrodes of the second phase are alternately and repeatedly arranged to transfer the generated signal charges in the horizontal direction, the signal charges are transferred through the plurality of vertical registers. Signal charge,
The charge discharging means capable of discharging the row-by-row and the column-by-column units, and the signal charges of the remaining columns other than the columns in which the signal charges are discharged among the rows in which the signal charges are discharged by the charge-discharging means in the unit of column. A solid-state image pickup device comprising a charge reading means for reading. 2. The solid-state imaging device according to claim 1, wherein the charge discharging unit includes a drain and a gate that are arranged adjacent to each other near the end of the vertical register, and the second phase of the horizontal register. The solid-state imaging device, wherein the electrode of the above is connected to the gate. 3. The solid-state imaging device according to claim 1, wherein the charge reading means is a horizontal register formed by the electrodes of the first phase. 4. The solid-state image pickup device according to claim 2, wherein the charge discharging unit and the charge reading unit function according to the voltages of the electrodes of the first phase and the second phase of the horizontal register. A solid-state image pickup device comprising: 5. The solid-state imaging device according to claim 2, further comprising a plurality of sets of electrodes, with one set of electrodes of the first phase and the second phase of the horizontal register. The solid-state imaging device is characterized in that the plurality of sets of electrodes are wired so as to be independently drivable. 6. The solid-state imaging device according to claim 2, wherein the plurality of sets of electrodes of the first phase and the second phase are contact formation points for connecting the electrodes and wirings. A solid-state image pickup device characterized in that the position in the horizontal register can be arbitrarily changed by changing the. 7. The method for driving a solid-state imaging device according to claim 2, wherein the signal charge is transferred in the vertical register.
In the first phase electrode and the second phase electrode of the horizontal register, when the first phase electrode is at a high level and the second phase electrode is at a low level, the signal charges are read out to the horizontal register row by row. When the electrode of the first phase is at the low level and the electrode of the second phase is at the high level, the signal charge is discharged to the drain of the charge discharging means in units of rows, which drives the solid-state imaging device. Method. 8. The method for driving a solid-state imaging device according to claim 5, wherein the signal charges are generated by independently driving the electrodes of the first phase and the second phase of the plurality of sets of horizontal registers. A method for driving a solid-state imaging device, wherein the solid-state imaging device is discharged in a predetermined column unit.