JP2003152693A - Method and device for reducing clock jitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically control jitter which is generated by the influence of waveform distortion or noise in ECL clock transmission, to a minimum. SOLUTION: In a jitter control means 11, an input clock is distributed to (n) transmission lines (21-1 to 21-n) for transmitting the input clock with respective desired delay quantities, and the signal which is outputted together with a capacitive reflection pulse with which the clocks propagated through these (n) transmission lines are reflected on reception side terminals (CL1-CLn) and reflected again on transmitting side terminals (CS1-CSn) of (n) transmission lines and returned to the receiving side terminals, of any one reception side terminal selected by a select signal out of (n) reception side terminals is outputted as an output clock. The jitter control means composed of a frequency dividing circuit 12, phase comparing circuits 14 and 15, counters 15 and 17 and a variable delay circuit 13 updates the select signal until selecting a reception side terminal in which the capacitive reflection pulse is overlapped on the jitter portion of the input clock in the reception side terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock jitter reducing method and a clock jitter reducing apparatus, and more particularly to a clock jitter reducing method and a clock jitter reducing apparatus in an information processing apparatus.

[0002]

2. Description of the Related Art An information processing device, which is an aggregate of integrated circuits typified by a personal computer, has a higher processing speed, and the operating margin of the device becomes smaller as the clock frequency becomes higher, thus suppressing or reducing clock jitter. Is becoming important for improving the performance and reliability of the device.

Therefore, various inventions have been proposed for the clock jitter due to the power supply fluctuation accompanying the switching of the circuit elements.
Inventions have been made (eg 2001-0777685)
Please refer to the bulletin etc.).

However, the clock jitter is not only caused by the fluctuation of the power source due to the switching of the circuit elements described above, but also clock jitter is generated by the oscillation circuit itself.

[0005]

The information processing device, which is an aggregate of integrated circuits represented by a personal computer, further increases in processing speed, and as the clock frequency increases, the operating margin of the device decreases and the clock jitter increases. Suppress
The reduction is becoming important for improving the performance and reliability of the device, and it is desired to suppress / reduce the clock jitter generated in the oscillation circuit itself.

A main object of the present invention is to provide a means for automatically adjusting the jitter generated in ECL clock transmission so as to be minimized.

[0007]

According to a first aspect of the present invention, in a clock jitter reducing method, an input clock is distributed to n transmission lines each transmitting a signal waveform with a desired delay amount. The n number of receptions in which the clock transmitted through the transmission line is reflected at the reception side terminal, is reflected again at the transmission side terminal of the n transmission lines, and is output together with the capacitive reflection pulse returning to the reception side terminal. Of the side terminals,
It is characterized in that the reception side terminal where the capacitive reflection pulse overlaps the jitter part of the input clock is selected and a signal from the selected reception side terminal is used as an output clock.

According to a second invention of the present application, in the first invention, a signal from the reception side terminal selected by selecting the reception side terminal by a selection signal output according to a counter value of a first counter prepared in advance. Is output as an output clock, and the output clock output from the jitter adjusting means is divided by 2 to output TRUE output T2 and CO
A frequency divider circuit for outputting the MPLEMENT output C2 and a variable delay circuit for increasing / decreasing the delay amount of the COMPLEMENT output C2 of the frequency divider circuit according to the value of the second counter and outputting as C2 ′ are provided in advance, and the T2 and the The phases of the falling edges of C2 ′ are compared with each other, and the count value is increased / decreased with respect to the second counter until the falling edges of T2 and C2 ′ match. When the phases match each other, the phases of the rising edges of the T2 and the C2 ′ are compared with each other, and the count value of the first counter is increased or decreased until the phases of the T2 and the C2 ′ match each other. The selection signal is output to the means.

According to a third invention of the present application, in the first invention, the clock transmitted through the n transmission lines is reflected by a capacitive reflection circuit provided at each reception side terminal. To do.

According to a fourth aspect of the present invention, in a clock jitter reducing apparatus, an input clock is distributed to n transmission lines each transmitting with a desired delay amount, and the clock transmitted through the n transmission lines is received. Selected by the selection signal from the n receiving side terminals which are output together with the capacitive reflection pulse which is reflected by the side terminal, is reflected again by the transmitting side terminals of the n transmission lines, and is returned to the receiving side terminal. Jitter adjusting means for outputting the signal of the receiving side terminal as an output clock, and updating the selection signal until selecting the receiving side terminal where the capacitive reflection pulse overlaps the jitter part of the input clock at the receiving side terminal It is characterized in that it is configured to include a jitter adjustment control means for controlling.

According to a fifth invention of the present application, the jitter adjustment control means of the fourth invention comprises a first counter for outputting the selection signal according to a counter value and two output clocks for output by the jitter adjustment means. A frequency dividing circuit for dividing and outputting TRUE output T2 and COMPLEMENT output C2;
A variable delay circuit that increases / decreases the delay amount of the COMPLEMENT output C2 of the frequency divider circuit according to the value of the second counter and outputs as C2 ′ is compared with the phase of the falling edges of T2 and C2 ′. Of the counter, the first phase comparison circuit increases or decreases the count value until the falling edges of the T2 and the C2 'match, and the first phase comparison circuit causes the T2 and the C2' to increase.
When the phases of the falling edges of T2 and C2 'match, the phases of the rising edges of T2 and C2' are compared, and the count value of the first counter is changed until the phases of T2 and C2 'match. It is characterized in that it is configured to include a second phase comparison circuit for increasing / decreasing.

According to a sixth invention of the present application, in the fourth invention, the clock transmitted through the n transmission lines is reflected by a capacitive reflection circuit provided at each reception side terminal. To do.

[Operation] In the present invention, in the ECL clock transmission, the means for detecting the increase or decrease of the jitter generated in the clock generation component and the like, and the means for automatically adjusting the detected jitter to the minimum are provided. Is characterized by.

FIG. 2 shows details of the jitter adjusting means 11 of FIG. In FIG. 2, the ECL transmission IC 20 distributes the input clock CIN to 1: n, and the clocks transmitted through the transmission lines 21-1 to 21-n that transmit the signal waveforms with desired delay amounts are capacitive reflection circuits 22-. At 1 to 22-n, the capacitive reflection pulse is directed downward at the rising edge and upward at the falling edge and reflected to the transmission side terminals CS1 to CSn. At the transmission side terminals CS1 to CSn, the upward reflection is generated at the rising edge of the clock and at the falling edge. It becomes a downward pulse and is reflected again toward the reception side terminals CL1 to CLn,
From the change of the receive clock (rising / falling) to C
Between L1-CS1, between CL2-CS2, ..., CLn-CS
After the signal round trip propagation delay time between n, the receiving side terminals CL1 to C
Since it returns to Ln, the ECL reception IC 23 selects the transmission line in which the capacitive reflection pulse is overlapped with the clock waveform at an appropriate timing among the transmission lines 21-1 to 21-n by the selection signal SEL. Is minimized.

Further, in FIG. 1, the frequency dividing circuit 12 divides the clock COUT into two, and the variable delay circuit 13, the phase comparison circuit 14 and the counter 15 are the TRUE output T2 of the frequency dividing circuit 12 and the variable delay circuit 13. The phases of the falling edges of the output C2 'are matched, and in this state, the phase comparison circuit 1
6 and the counter 17 output TRUE output T of the frequency dividing circuit 12
2 and ECL in the jitter adjusting means 11 so that the phases of the rising edges of the output C2 'of the variable delay circuit 13 match each other.
By adjusting the value of the selection signal SEL of the receiving IC 23, the jitter of COUT is automatically adjusted to be the minimum.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the clock jitter reducing apparatus of the present invention, and FIG. 2 is a block diagram of the jitter adjusting means in FIG.

In FIG. 1, the jitter adjusting means 11 adjusts the jitter amount of the input clock CIN according to the selection signal SEL output from the counter 17, and outputs it as COUT. (Details are shown in FIG. 2.) The frequency dividing circuit 12 divides the frequency of the clock COUT output from the jitter adjusting means 11 by two.

The variable delay circuit 13 is the CO of the frequency dividing circuit 12.
The delay amount of the MPLEMENT output C2 is increased or decreased according to the value of the counter 15 and output as C2 '.

The phase comparison circuit 14 is a TR of the frequency dividing circuit 12.
The UE output T2 and the phase of the falling edges of the output C2 'of the variable delay circuit 13 are compared with each other, and if the falling edge of the output C2' of the variable delay circuit 13 is before the counter 15, the count is incremented by one, and If so, instruct only one countdown.

The counter 15 starts counting up after the reset is released, and after the falling edge of C2 'comes after the falling edge of T2, increases or decreases the count value according to the instruction of the phase comparison circuit 14.

In the phase comparison circuit 16, the falling edge of C2 'is T when the count value of the counter 15 is increased or decreased.
When it becomes equal to the falling edge of 2, the phase comparison circuit 14 activates and compares the phases of the rising edges of the TRUE output T2 of the frequency dividing circuit 12 and the output C2 ′ of the variable delay circuit 13 and T2 and C2 ′. When the phase relationship of is reversed, the counter 17 counts up /
Instruct to switch down.

The counter 17 starts counting up after releasing RESET, increases or decreases the count value according to the instruction of the phase comparison circuit 16, and outputs the selection signal SEL to the jitter adjusting means 11.

Next, the structure and operation of the jitter adjusting means 11 of FIG. 2 will be described.

In this embodiment, the ECL transmission IC 20
Distributes the input clock CIN to 1: n.

The ECL output buffers 20-1 to 20-n in the ECL transmission IC 20 are connected to the reception side terminals from the transmission side terminals CS1 to CSn via the transmission lines 21-1 to 21-n. The clock is sent to CL1 to the reception side terminal CLn.

The transmission lines 21-1 to 21-n are
The signal waveform is transmitted with a desired delay amount.

The capacitive reflection circuit 22-1 to the capacitive reflection circuit 22-n face downward when the reception clock rises,
At the time of the fall, the upward capacitive reflection pulse is reflected toward the transmission side terminal CS1 to the transmission side terminal CSn.

The ECL receiving IC 23 selects a signal waveform passing through the transmission line of a desired delay amount among the transmission lines 21-1 to 21-n by the selection signal SEL and COUT.
Output as.

Termination resistance circuit 2 connected to termination voltage Vt
4-1 to terminating resistor circuit 24-n determines the voltage level of the received ECL signal and changes the signal level.
Converge fluctuations.

The output impedance of the ECL output buffers 20-1 to 20-n is the transmission line 21.
-1 to the transmission line 21-n are smaller than the characteristic impedance, so the capacitive reflection circuit 22-1 to the capacitive reflection circuit 2
The capacitive reflection pulse propagated from 2-n is transmitted to the terminal C on the transmission side.
At S1 to the transmission side terminal CSn, the pulse rises when the clock rises, and when the clock falls, it becomes a downward pulse and is reflected again toward the reception side terminal CL1 to the reception side terminal CLn, and the reception clock changes (rises / falls). To CL1-CS1, CL2-CS2, ..., CLn-
After the signal round-trip propagation delay time between CSn (A in FIG. 5, B in FIG. 6), it returns to the reception side terminal CL1 to the reception side terminal CLn.

Next, the operation of the clock jitter reducing apparatus of the present invention will be described in detail with reference to the timing charts of FIGS. 3 and 4.

In FIG. 3, (a) shows the COUT waveform before the jitter reduction operation, which is t30-t31 and t31.
A long cycle and a short cycle coexist like -t32.

(B) shows the frequency dividing circuit 1 before the jitter reduction operation.
2 is a waveform of the TRUE output T2, and a long upper pulse and a short lower pulse are mixed in a cycle twice as long as COUT like t30-t31 and t31-t32.

(C) shows the frequency divider circuit 1 before the jitter reduction operation.
2 is the waveform of COMPLEMENT output C2, and t3
Like 0-t31 and t31-t32, a long lower pulse and a short upper pulse are mixed in a double cycle of COUT.

(D) is a waveform of the output C2 'of the variable delay circuit 13 before the jitter reduction operation.

The phase comparison circuit 14 compares the phases of the falling edges of T2 and C2 ', and instructs the counter 15 to count up if the falling edge of the output C2' of the variable delay circuit 13 is before, and count down if it is after. Then
Further, since the counter 15 starts counting up after canceling RESET and the falling edge of C2 ′ comes after the falling edge of T2, the count value is increased / decreased according to the instruction of the phase comparison circuit 14. (D)
The phases of the falling edges of C2 ′ of C1 ′ and C2 ′ match at t31. At this time, as for the phase of the rising edge, T2 is t3.
0 and C2 'are t30' and do not match.

(E) shows the frequency dividing circuit 1 after the jitter reduction operation.
2 TRUE output T2 and variable delay circuit 13 output C2 '
Is the waveform of.

(F) is the COUT waveform after the jitter reduction operation.

The phase comparison circuit 16 compares the phases of the rising edges of T2 and C2 'with each other, and when the phase relationship between T2 and C2' is reversed, instructs the counter 17 to switch up / down, and Counter 17
Starts counting up after canceling RESET, increases / decreases the count value according to the instruction of the phase comparison circuit 16 and outputs the selection signal SEL to the jitter adjusting means 11, and further, the jitter adjusting means 11 performs the operation described later to reduce the jitter of COUT. Since it is reduced, the COUT waveform of (f) is t30-t3.
1'and t31'-t32 have repetitive waveforms of substantially the same period, the rising edge phase of T2 and C2 'in (e) is t30, and the falling edge phase is t3.
1'matches.

Even if COUT before jitter reduction is exactly the same as that in (a), the clock jitter reduction apparatus of FIG. 1 operates as shown in FIG. 4 depending on the frequency division start timing of the frequency dividing circuit 12. There is also.

In FIG. 4, (g) is the COUT waveform before the jitter reduction operation, which is exactly the same as (a), and is t40-t.
41 and t41-t42, a short cycle and a long cycle are mixed.

(H) shows the frequency dividing circuit 1 before the jitter reduction operation.
2 is a waveform of the TRUE output T2, and a short upper pulse and a long lower pulse are mixed in a double cycle of COUT like t40-t41 and t41-t42.

(I) shows the frequency dividing circuit 1 before the jitter reduction operation.
2 is the waveform of COMPLEMENT output C2 of t2
Like 0-t41 and t41-t42, a short lower pulse and a long upper pulse coexist in a double cycle of COUT.

(J) is the waveform of the output C2 'of the variable delay circuit 13 before the jitter reduction operation.

The phase comparison circuit 14 compares the phases of the falling edges of T2 and C2 ', and instructs the counter 15 to count up if the falling edge of the output C2' of the variable delay circuit 13 is before, and to count down if it is after. Further, since the counter 15 starts counting up after canceling RESET and the falling edge of C2 ′ comes after the falling edge of T2, the count value is increased / decreased according to the instruction of the phase comparison circuit 14. The phases of the falling edges of T2 and C2 'of (j) match at t41.
At this time, as for the phase of the rising edge, T2 is t40, C
2'becomes t40 'and does not match.

(K) is the frequency dividing circuit 1 after the jitter reduction operation.
2 TRUE output T2 and variable delay circuit 13 output C2 '
Is the waveform of.

(L) is the COUT waveform after the jitter reduction operation.

The phase comparison circuit 16 compares the phases of the rising edges of T2 and C2 ', and instructs the counter 17 to switch up / down when the phase relationship between T2 and C2' is reversed, and Counter 17
Starts counting up after canceling RESET, increases / decreases the count value according to the instruction of the phase comparison circuit 16 and outputs the selection signal SEL to the jitter adjusting means 11, and further, the jitter adjusting means 11 performs the operation described later to reduce the jitter of COUT. Since it is reduced, the COUT waveform of becomes a repetitive waveform of almost the same cycle like t40 ″ -t41 and t41-t42 ″, and the phase of the rising edge of T2 and C2 ′ of (k) is t40 ″ and the falling edge is The phases match at t41.

The jitter reduction operation of the jitter adjusting means of FIG. 2 will be described with reference to the timing charts of FIGS. 5 and 6.

FIG. 5 shows the jitter reduction operation when the signal round-trip propagation delay time between CL and CS is substantially equal to one clock cycle.

(M) is a clock waveform when there is no capacitive reflection circuit 22-1 to capacitive reflection circuit 22-n at the reception side terminal CL1 to reception side terminal CLn, T01
And T12, a short cycle and a long cycle are mixed (there is jitter).

(N) and (o) are drawn for convenience of explanation of the signal round-trip propagation time "A" between CS and CL. The capacitive reflection circuit 22-1 at the reception side terminal CL1 to the reception side terminal CLn is shown. ~ When the capacitive reflection circuit 22-n is added,
It is a waveform of a single rising edge at times t0 and t1, and the capacitive reflection pulse returns after the CS-CL signal round-trip propagation time “A” from the rising edge.

The length of the CS-CL signal round-trip propagation time "A" changes according to the delay amount of the transmission line 21-1 to the transmission line 21-n.

Since the counter 17 in FIG. 1 starts counting up after canceling RESET, the ECL receiving IC 23 first selects the transmission line 21-1, and as the counter 17 counts up, the selected transmission line 21-2 is selected. , 21-
Change to 3 ...

Then, for example, when the transmission line 21-4 is selected, when the length of the CS-CL signal round-trip propagation time "A" is T01 having a short cycle as in the waveforms (m) and (n). Indicates that the capacitive reflection pulse t1 ′ corresponding to the rising edge at time t0 and the next rising edge t1 do not overlap each other, and when the cycle is long T12, the capacitive reflection pulse corresponding to the rising edge at time t1 and the next It is assumed that the rising edge of the pulse overlaps with the rising edge of the pulse at time t2.

At this time, the receiving side terminal C of the transmission line 21-4
The actual waveform at L4 is as shown in (p), and the rising edge (t) that overlaps with the upward capacitive reflection pulse.
0'or t2 ', etc., the phase shifts to the front and does not overlap with the capacitive reflection pulse.
In the waveform (m), the short cycle T01 is expanded to T01 'and the long cycle T12 is contracted to T12', so that the jitter is reduced.

The width of the rising edge (t0 'or t2', etc.) overlapping with the upward capacitive reflection pulse when the phase transitions forward depends on the width of the capacitive reflection pulse. Sometimes, it is necessary to determine the value of the capacitive reflection circuit for producing the capacitive reflection pulse necessary to reduce the amount of jitter based on empirical rules or calculations.

FIG. 6 shows the jitter reduction operation when the signal round-trip propagation delay time between CL and CS is substantially equal to the half cycle of the clock.

(Q) is a clock waveform when there is no capacitive reflection circuit 22-1 to capacitive reflection circuit 22-n at the reception side terminals CL1 to CLn, and T35.
And T57, a long cycle and a short cycle are mixed (there is jitter).

(R) and (s) drawn for convenience of explaining the CS-CL signal round-trip propagation time "B" are the capacitive reflection circuit 22-1 at the receiving side terminal CL1 to the receiving side terminal CLn. ~ When the capacitive reflection circuit 22-n is added,
It is the waveform of a single falling edge at time t4 and time t6, and the capacitive reflection pulse returns after the CS-CL signal round-trip propagation time "B" from the falling edge.

The length of the CS-CL signal round-trip propagation time "B" changes according to the delay amount of the transmission lines 21-1 to 21-n.

Since the counter 17 of FIG. 1 starts counting up after canceling RESET, the ECL receiving IC 23 first selects the transmission line 21-1, and as the counter 17 counts up, the selected transmission line 21-2 is selected. , 21-
Change to 3 ...

Then, for example, when the transmission line 21-4 is selected, the length of the CS-CL signal round-trip propagation time "B" is T35, which has a long cycle like the waveforms (q) and (r). Is the capacitive reflection pulse t5 ′ corresponding to the falling edge of time t4 and the next rising edge t5 do not overlap, and when the period is short T57, the capacitive reflection pulse corresponding to the falling edge of time t6. It is assumed that the next rising edge and the next rising edge overlap at time t7.

At this time, the receiving side terminal C of the transmission line 21-4
The actual waveform at L4 is as shown in (t) and the rising edge (t
3 "or t7", etc., the phase shifts backward, and the rising edge (t5) is not overlapped with the capacitive reflection pulse.
In the waveform (q), the long cycle T35 is reduced to T35 ″, the short cycle T57 is extended to T57 ″, and the jitter is reduced.

[0066]

As described above, in the clock jitter reducing apparatus of the present invention, the input clock CIN is distributed to the transmission line 1: n which transmits the signal waveform with a desired delay amount, and the transmission line 21- The clocks transmitted from 1 to 21-n are capacitive reflection circuits 22 of the reception side terminals CL1 to CLn.
Reflected at -1 to 22-n and folded back at the transmission side terminals CS1 to CSn, the capacitive reflection pulse returning to the reception side terminals CL1 to CLn after the signal round trip propagation delay time is included in the jitter portion of the clock waveform. By making it possible to automatically select the transmission lines on which the capacitive reflection pulses overlap, it is possible to minimize the jitter of COUT.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a clock jitter reduction device of the present invention.

FIG. 2 is a configuration diagram of a jitter adjusting unit in FIG.

FIG. 3 is a timing chart showing the operation of the clock jitter reduction device of the present invention.

FIG. 4 is a timing chart showing another operation of the clock jitter reduction device of the present invention.

5 is a diagram showing a jitter reduction operation when the signal round-trip propagation delay time between CL and CS in FIG. 2 is substantially equal to one clock cycle.

6 is a diagram showing a jitter reduction operation when a signal round-trip propagation delay time between CL and CS in FIG. 2 is substantially equal to a half cycle of a clock.

[Explanation of symbols]

11 Jitter adjustment means 12 frequency divider 13 Variable delay circuit 14 Phase comparison circuit 15 counter 16 Phase comparison circuit 17 counter 20 ECL transmission IC 20-1 ECL output buffer 20-n ECL output buffer 21-1 Transmission line 21-n transmission line 22-1 Capacitive reflection circuit 22-n Capacitive reflection circuit 23 ECL receiver IC 24-1 Termination resistance circuit 24-n termination resistor circuit

Claims (6)

[Claims] 1. A clock jitter reducing method, wherein an input clock is distributed to n transmission lines each transmitting a signal waveform with a desired delay amount, and the clocks transmitted through the n transmission lines are received at terminals. Of the n reception-side terminals that are reflected and then reflected again at the transmission-side terminals of the n transmission lines and returned to the reception-side terminals, the jitter portion of the input clock A method for reducing clock jitter, characterized in that the receiving side terminal on which the capacitive reflected pulses overlap is selected and a signal from the selected receiving side terminal is used as an output clock. 2. Jitter adjusting means for selecting the receiving side terminal by a selection signal output according to a counter value of a first counter prepared in advance and outputting a signal from the selected receiving side terminal as an output clock, A frequency divider circuit that divides the output clock output from the jitter adjusting means by two to output TRUE output T2 and COMPLEMENT output C2, and increases or decreases the delay amount of the COMPLEMENT output C2 of the frequency divider circuit according to the value of the second counter. A variable delay circuit for outputting as C2 ′ is provided in advance, the phases of the falling edges of T2 and C2 ′ are compared, and the falling edges of T2 and C2 ′ match the second counter. Until the count value is increased or decreased until the phases of the falling edges of T2 and C2 'match each other, And the phases of the rising edges of C2 ′ are compared with each other, and the count value of the first counter is increased / decreased until the phases of T2 and C2 ′ match, and the selection signal is output to the jitter adjusting means. The method for reducing clock jitter according to claim 1, wherein the clock jitter is reduced. 3. The clock jitter reduction method according to claim 1, wherein the clock transmitted through the n transmission lines is reflected by a capacitive reflection circuit provided at each reception side terminal. 4. A clock jitter reduction device, wherein an input clock is distributed to n transmission lines each transmitting with a desired delay amount, and the clock transmitted through the n transmission lines is reflected at a receiving side terminal, and Of the n reception-side terminals that are reflected with the transmission-side terminals of the n transmission lines and are output together with the capacitive reflection pulse that returns to the reception-side terminals, the reception-side terminal selected by the selection signal Jitter adjustment means for outputting a signal as an output clock; and jitter adjustment control means for updating the selection signal until the reception side terminal where the capacitive reflection pulse overlaps the jitter part of the input clock at the reception side terminal is selected. A clock jitter reduction device characterized by being configured to include. 5. The jitter adjustment control means divides the output clock output from the jitter adjustment means by a first counter for outputting the selection signal according to a counter value, and divides the output clock by two to generate a TRUE output T2 and a COMPLEMENT output C2. Frequency divider circuit for outputting and COMPLEME of the frequency divider circuit
A variable delay circuit that increases / decreases the delay amount of the NT output C2 according to the value of the second counter and outputs it as C2 ′ is compared with the phase of the falling edges of the T2 and the C2 ′ to compare with the second counter. A first phase comparison circuit that increases or decreases the count value until the falling edges of T2 and C2 'match, and the phase between the falling edges of T2 and C2' in the first phase comparison circuit. When the two coincide with each other, the phases of the rising edges of the T2 and the C2 ′ are compared with each other, and the second phase comparison is performed to increase or decrease the count value of the first counter until the phases of the T2 and the C2 ′ coincide with each other. 5. The clock jitter reduction device according to claim 4, wherein the clock jitter reduction device comprises a circuit. 6. The clock jitter reduction device according to claim 4, wherein the clock transmitted through the n transmission lines is reflected by a capacitive reflection circuit provided at each reception side terminal.