JP2003152080A - Semiconductor integrated circuit device having analog circuit and digital circuit and design method using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the degree of freedom of circuit arrangement when analog digital hybrid system having desired function is constituted. SOLUTION: Variable analog circuit cells (VAMa, VAMb) which can constitute an analog circuit which has an A/D conversion circuit or a D/A conversion circuit and desired characteristic and are made in modules, and variable logic circuit cells (VLM) which can constitute desired logic are aligned at a prescribed ratio in a tile type on a semiconductor chip, variable analog circuit cells are arranged dispersively, wiring regions are arranged between these circuit cells which are formed in modules, and variable wiring switch circuits (DSW, ASW) which can connect parts between desired wirings are arranged at part positions corresponding to crossing parts of the wiring regions and I/O terminals of the respective modules, thus constituting a programable semiconductor integrated circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology effectively applied to an analog / digital mixed semiconductor integrated circuit device and a designing method thereof. For example, a circuit having an arbitrary function including a digital circuit and an analog circuit can be configured. The present invention relates to a technology that can be used for a semiconductor integrated circuit, a test apparatus using the same, and a hardware simulator.

[0002]

2. Description of the Related Art Recent advances in electronic technology have made it possible to configure semiconductor integrated circuit devices in a shorter period of time.
Also, there is an increasing demand for a more complicated structure that enables signal processing of both analog signals and digital signals.

In order to obtain a specific semiconductor device, it generally takes a relatively long period of time to design and manufacture it, but a semiconductor device called a so-called FPGA (field programmable gate array). Is provided in a completed state as a semiconductor device, and its logical function is set by a user or the like, so that a short TAT is possible in obtaining a desired function. FPGA
Such a semiconductor device can also be regarded as a convenient semiconductor device in the case where a semiconductor device is required instead of a semiconductor integrated circuit of a small amount and a large variety of products.

When both digital signal processing and analog signal processing are required in one semiconductor integrated circuit device, it is desirable that the analog circuit system also has a programmable configuration. Note that an invention relating to an integrated circuit in which an analog switch circuit network connected to an analog circuit module is programmable is known (for example, Japanese Patent Laid-Open No. 5-267458 and Japanese Patent Publication No. 11-5).
07478).

Further, in a semiconductor integrated circuit equipped with a known programmable digital circuit module and a programmable analog circuit module,
A user-configurable analog switch is provided for the plurality of analog circuit modules, and an AD conversion circuit and a DA conversion circuit are provided between the analog switch and the plurality of digital circuit modules. In other words, the configuration in which the plurality of analog circuit modules and the plurality of digital circuit modules are set as if they are in a centrally arranged configuration independent of each other and is coupled via the switch and the conversion circuit as described above is adopted. To take.

[0006]

As a result of various studies, the inventor of the present invention has adopted a semiconductor integrated circuit having a structure in which analog circuit modules are arranged substantially in a concentrated manner as in the known technique. We have found that it is difficult to improve the degree of freedom of the circuit when constructing an analog / digital mixed system having a desired function.

As a result of various studies, the analog circuit cell to be programmable can be composed of a relatively small circuit scale, and the digital circuit cell to be coupled to the analog circuit cell by the program can be close to the analog circuit cell. It has become clear that it is more advantageous to arrange them in the above in terms of programming the analog circuit cells and the digital circuit cells. In addition, it is clear that it is more advantageous to configure the analog circuit cell and the digital circuit cell as a substantially integrated unit than to clearly distinguish the entire analog circuit cell from the viewpoint of overall programming. Came. Therefore, the present inventors examined the distributed arrangement of a plurality of analog circuit modules on a chip.

As is well known, it suffices that a digital signal can be discriminated as a digital level such as "0", "1" level or high level, low level, and a relatively large signal level change is allowed. On the other hand, it is desired that the change in the signal level of the analog signal is as small as possible. The signal transmission path for analog signal transmission causes deterioration of the signal to be transmitted due to its parasitic resistance, parasitic capacitance and the like.

Therefore, the present inventors also examined the analog signal transmission configuration. The degradation in an analog signal depends on its length as well as its rate of signal change. Therefore, even if the signal transmission path is the same, the deterioration of the analog signal is small when the signal change speed is small. As described above, when a plurality of analog circuit cells or modules are distributedly arranged, the signal transmission path may be lengthened accordingly. The study structure for the analog signal transmission path is expected to be particularly effective in preventing or suppressing the deterioration of the level of the analog signal when the signal is transmitted and received between the modules which are relatively distant from each other.

An object of the present invention is to provide a programmable semiconductor integrated circuit device capable of forming an analog / digital mixed circuit having an arbitrary function. Another object of the present invention is to provide a programmable semiconductor integrated circuit device capable of improving the degree of freedom of circuit arrangement when an analog / digital mixed system having a desired function is constructed.

Still another object of the present invention is to provide a programmable semiconductor integrated circuit device capable of preventing analog signal level deterioration due to wiring resistance or the like even when signals are transmitted and received between circuits which are relatively distant from each other. It is in providing. Still another object of the present invention is to provide a programmable semiconductor device capable of forming a simple tester capable of performing a test without using an expensive test device and a method of designing an analog / digital mixed system using the programmable semiconductor device. There is to do.

Still another object of the present invention is to provide a hardware simulator capable of verifying whether or not the newly developed analog / digital mixed system operates on Aoki before being manufactured or prototyped as a semiconductor integrated circuit. The present invention provides a programmable semiconductor integrated circuit capable of configuring a. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, the A / D conversion circuit or the D / A
Modular analog circuit cells that have a conversion circuit and can configure an analog circuit having desired characteristics and variable logic circuit cells that can configure a desired logic are arranged and varied on a semiconductor chip at a predetermined ratio. In addition to disposing analog circuit cells in a distributed manner, a wiring region is provided between these circuit cells, and a variable wiring switch circuit capable of connecting desired wirings is arranged at the intersection of the wiring regions so as to be programmable. A semiconductor device is configured.

According to the above-mentioned means, the analog / digital mixed system having a desired function is mounted on the semiconductor chip by arbitrarily setting the configuration of the circuit cell and the connection state of the variable wiring switch circuit in the wiring area. You will be able to build. Moreover, since the variable analog circuits are arranged in a distributed manner, the degree of freedom in arranging the circuits can be improved.

Further, according to the above means, since the variable analog circuit having the desired characteristics can be constructed by using the variable analog circuit cell, the variable analog circuit cell can be used for another circuit cell or another semiconductor device. It is possible to construct an analog test circuit that detects a DC-like characteristic and a digital test circuit that generates a test pattern for inspecting the logic function of another circuit cell or another semiconductor device by using a variable logic circuit cell. Therefore, it is possible to realize a programmable semiconductor device capable of performing a test without using an expensive test device.

Further, by using this programmable semiconductor device, it is possible to verify whether or not the newly developed analog / digital mixed system operates normally before being manufactured or prototyped as a semiconductor integrated circuit. -A simulator can be configured.

Further, desirably, in the wiring region, the variable analog circuits can be connected by a pair of wires, and one of the wires of the pair can be used as a force line and the other can be used as a sense line. As a result, it is possible to prevent the level of the analog signal from being lowered due to the wiring resistance or the like even when a signal is transmitted / received between circuits which are relatively distant from each other. Therefore, it becomes possible to disperse the variable analog circuit cells in the entire semiconductor chip.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of an embodiment of a programmable semiconductor device (hereinafter referred to as FPA: field programmable array) according to the present invention. The FPA of the present invention is formed on one semiconductor substrate (chip) such as single crystal silicon. In the FPA of this embodiment, a variable logic circuit cell VLM capable of changing a logic function by an external input and a characteristic can be changed by an external input in a portion excluding the peripheral portion of the chip. Variable analog circuit cells VAMa and VAMb
And are arranged in such a layout that they are alternately arranged. Among VAMa and VAMb, VAMa is a variable analog circuit cell which receives an analog signal as an input and converts it into a digital signal and outputs it, and VAMb is a variable analog circuit cell which receives a digital signal as an input and converts it into an analog signal and outputs it Each is configured.

The variable logic circuit cell VLM and the variable analog circuit cells VAMa and VAMb which form the FPA of this embodiment.
Are modularized to facilitate the design of the entire LSI. That is, each cell is realized by coherent and independent design data. Hereinafter, these circuit cells will be referred to as modules. In this embodiment, two variable analog modules V
AMa and VAMb are arranged on the chip so as to be adjacent to each other, and these variable analog modules VA are arranged.
The variable logic module VLM is arranged so as to surround Ma and VAMb. That is, two of the six modules are variable analog modules VAMa and VAM.
b and 4 are arranged so as to be the variable logic module VLM. This allows the variable logic module VLM
Are spread over the entire chip, and variable analog modules VAMa and VAMb are evenly distributed and arranged therein.

The ratio of the variable analog modules VAMa and VAMb to the variable logic module VLM is not limited to 2: 4, but may be any ratio. In this specification, when the variable analog modules VAMa and VAMb are not distinguished, they are collectively referred to as VAM.

Further, wiring regions HLA and VLA are provided in a grid pattern between the modules VLM and VAM. Although not particularly limited, the above-mentioned modules V
The LM and VAM are configured so that the left side is an input and the right side is an output in FIG. Then, the intersections of the grid-shaped wiring areas HLA and VLA and the portions corresponding to the module input / output terminals of the vertical wiring area HLA are
There are provided variable wiring switch circuits DSW and ASW which are composed of a plurality of switches called a switch matrix or a crosspoint switch whose connection state can be changed from the outside and a register for holding ON / OFF information thereof.

Here, DSW is a variable wiring switch circuit for switching the signal line of the digital signal, and ASW.
Means a variable wiring switch circuit for switching the signal line of the analog signal, and as described later, the same one can be used in terms of configuration. Further, each wiring group of the wiring areas HLA and VLA uses a multilayer wiring technique, one (for example, the wiring group of the wiring area HLA) along the lateral direction of the chip, and the other (for example, the wiring of the wiring area VLA). The groups are formed in a state of being insulated from each other by different wiring layers along the vertical direction of the chip.

The wiring area HL is not particularly limited.
A part of the wiring of A and VLA is a variable analog module V
Any two of them are arranged as a pair to connect between AMa and VAMb. Specifically, of the wirings of each pair, one line is a force line for transmitting an analog output signal from a certain variable analog module VAMb to any one of the variable analog modules VAMa, and the other line is the variable analog module VAMa on the receiving side. Variable analog module VAMb from the sender
It is used to function as a sense line for returning a signal to. The functions of the force line and the sense line will be described later.

Further, as shown in FIG. 1, in the periphery of the chip, internal functions connected to the wirings in the wiring areas HLA and VLA and constituted by the variable logic module VLM and the variable analog module VAM. I / O buffer units I / O1 to I / O4 for inputting / outputting signals between the circuit and a device outside the chip are provided. This I /
In the O buffer units I / O1 to I / O4, input / output buffer circuits A-I / O for analog signals mixed with a plurality of input / output buffer circuits for digital signals are provided at a predetermined ratio (for example, 8: 1). It is distributed. Since the input / output buffer circuits for analog signals are distributed, the flexibility of design is high because the analog terminals can be taken out from relatively arbitrary positions when designing a board system or the like in which this chip is mounted. Has the advantage that

FIG. 2 shows a variable analog module VAMa.
A concrete example of the variable analog module VA is shown in FIG.
A specific example of Mb is shown. As shown in FIG. 2, the variable analog module VAMa includes an input amplifier 11 for amplifying an analog input signal Ain, an A / D conversion circuit 12 for converting the amplified analog input signal into a digital signal, and a converted signal. And a control circuit 14 for controlling the gain of the input amplifier 11 and the operations of the A / D conversion circuit 12 and the output buffer circuit 13 and the like.

The control circuit 14 has a register REG1 for fetching and holding setting data SD such as circuit configuration data and control data which are also supplied from the outside in synchronization with a transfer clock CK supplied from the outside. A control operation is performed according to an external system clock φc based on the setting data of the register REG1. Control circuit 14 to A / D conversion circuit 1
The control signals supplied to 2 include, for example, an enable signal for turning the A / D conversion circuit 12 into an operating state and a non-operating state, and a timing signal for giving a predetermined operation timing. Output buffer circuit 1 from control circuit 14
The control signals supplied to 3 include, for example, a timing signal that gives output timing to the output buffer circuit 13 and a state control signal that puts the output in a high impedance state.

The variable analog module VAMb is shown in FIG.
, An input buffer circuit 21 for identifying the digital input signal Din, a D / A conversion circuit 22 for converting the received digital input signal Din into an analog signal, and an output after amplifying the converted signal. Control the output amplifier 23 and the gain of the output amplifier 23.
Control circuit 24 for controlling the operation of the A / A conversion circuit 22
Etc. The control circuit 24 also has a register REG2 for fetching and holding setting data such as circuit configuration data and control data which are also supplied from the outside in synchronization with a transfer clock CK supplied from the outside, and the setting of the register REG2 is performed. It is configured to perform control operation according to a system clock φc from the outside based on data. The control signals supplied from the control circuit 24 to the input buffer circuit 21 and the D / A conversion circuit 22 include enable signals and operation timing signals.

Variable analog module VA of this embodiment
A voltage follower 25 for generating a potential Vb applied to the guard wiring GL provided so as to surround the pair of wirings (force line FL and sense line SL) of the wiring regions HLA and VLA is provided in Mb. There is. The force line FL and the sense line SL are provided on the output side of the variable analog module VAMb.
Pair of output terminals 26a, 26b to which are respectively connected
And a terminal 26c to which the guard wiring GL is connected is provided.

On the other hand, the variable analog module VAM
As shown in FIG. 2, a pair of input terminals 16a and 16b to which the force line FL and the sense line SL are respectively connected and a guard wiring G are provided on the input side of a.
The terminal 16c to which L is connected is provided, and the force line FL and the sense line SL connected to the input terminals 16a and 16b are coupled to each other in the module VAMa to form a so-called Kelvin contact, and the input of the input amplifier 11 is input. It is connected to the terminal.

As described above, the sense line SL is provided separately from the force line FL, and the module VAMa of the next stage is provided.
By feeding back the potential of the input terminal of the input line to the output amplifier 23 of the module VAMb in the previous stage, the force line FL
Even if includes a parasitic resistance, it is possible to prevent an error from occurring in the input signal of the module at the next stage due to the parasitic resistance. In other words, when it is desired to transmit an analog signal from the module VAMb to the module VAMa, if transmission of the signal is attempted with only one wiring, if the distance from the transmission side module to the reception side module is long, the parasitic resistance of the wiring is increased. Is too large to ignore and the level of the analog signal cannot be correctly transmitted to the next-stage module.

On the other hand, if a sense line SL is provided in addition to the force line FL and the signal at the input end of the receiving side module is fed back to the input of the output amplifier 23 of the transmitting side module, the output amplifier 23 will be one of the two. Input signal (D / A
The output signal of the conversion circuit 22 operates so as to match the other input signal (the feedback signal from the module on the receiving side), so that an error due to the parasitic resistance of the force line FL is applied to the input signal of the module at the next stage. It does not occur.

The terminal 16c provided in the module VAMa to which the guard wiring GL is connected is provided in order to facilitate design by giving terminal information to which the end of the guard wiring GL is connected at the time of design. This is a dummy terminal, and in the module VAMa, this terminal 16c is a terminal that is not connected to anything. This terminal 16c is not absolutely necessary for the operation of the circuit and can be omitted.

Further, although not particularly limited, in this embodiment, the voltage follower 25 in the module VAMb for applying the potential to the guard wiring GL receives the output of the DA conversion circuit 22 as an input, and thereby the output amplifier 23. Accordingly, the same voltage as the voltage output to the force line FL is applied to the guard line GL. That is, the potential of the guard line GL is changed according to the output of the DA conversion circuit 22.

As a result, the coupling capacitance between the force line FL and the sense line SL and the guard line GL is reduced, and the apparent load of the output amplifier 22 can be reduced. Also, force line FL
Since the sense line SL is surrounded by the guard line GL, there is also an advantage that noise jumping into the force line FL and the sense line SL from outside the chip or other lines transmitting a digital signal on the chip can be suppressed.

Although not shown in FIGS. 2 and 3, the variable analog modules VAMa and VAMb are supplied with the power supply voltage VDD and the ground potential VSS. Power is supplied to the analog modules VAMa and VAMb by supplying the variable logic module with a power supply voltage VDD and a ground potential VSS.
Can be configured to be performed by a conductive layer different from the conductive layer forming the wiring for supplying the power. In this case, it is desirable that the external terminal for supplying the power supply voltage is also a separate terminal for the analog module and the variable logic module. As a result, it is possible to suppress the power supply noise generated by the operation of the digital section from being transmitted to the analog section.

Further, in this embodiment, the signal wirings forming the shift scan path SSP for transferring the setting data to each module, the signal wirings in each module and the signal wirings in the wiring areas HLA and VLA connecting the modules,
It is configured by a conductive layer different from the conductive layer forming the power supply line.

Further, in the FPA of this embodiment,
As shown in FIG. 4, the force line FL and the sense line SL provided as a pair of wirings in the wiring regions HLA and VLA are formed to have a twisted pair structure except for the portion where the variable wiring switch circuit is provided. As a result, even if noise jumps in from one wiring side, the noise acts on the force line FL and the sense line SL as in-phase noise, and therefore cancels each other and the noise is further reduced. is there.

This force line FL and sense line S
The twisted pair structure of L can be formed by two layers of wiring by a multilayer wiring technique. That is, insulation can be achieved by forming the wirings at the intersecting portions as conductive layer patterns of different layers. Therefore, paying attention to each of the force line FL and the sense line SL, in the case where the twisted pair structure is not used, it is possible to form a conductive layer pattern of one layer and the same layer, but in this embodiment, each line FL and SL has at least 2 layers. It will be formed of a conductive layer having more layers.

As shown in FIG. 4, in this embodiment, a twisted pair line TP for transmitting an analog signal is used.
L and the guard line GL are formed so as to intersect with the signal line DTL transmitting a digital signal in an insulated state. That is, the wirings in the wiring areas HLA and VLA are composed of three conductive layers. Although FIG. 4 shows a case where the signal line DTL for transmitting a digital signal is configured to pass below the twisted pair line TPL, the present invention is not limited to this, and the digital signal is transmitted. It is also possible to configure such that the signal line to be connected passes above the twisted pair line.

Further, by devising the structure of the intersection of the signal line DTL for transmitting the digital signal and the twisted pair line TPL, the signal line for transmitting the digital signal is also constituted by two conductive layers, so that the wiring regions HLA, VLA. It is also possible to form the entire wiring of 2 by two conductive layers. Further, although FIG. 4 shows a case where only the twisted pair line TPL is arranged in the wiring regions HLA and VLA where the twisted pair line TPL is arranged, a digital signal is transmitted in parallel with the twisted pair line TPL. It is also possible to use the wiring areas HLA and VLA where the signal lines DTL are arranged.

FIG. 5 shows each of the above modules VLM and VA.
An example of a data transfer method of data set in the registers in the M and variable wiring switch circuits DSW and ASW is shown. Figure 5
In the present embodiment, reference numeral 100 denotes a semiconductor chip in which the FPA according to the present invention is formed. In this embodiment, each module and the register in the variable wiring switch circuit are respectively composed of shift registers, and an S-shape is provided over the entire chip. The shift scan paths SSP are formed so as to form a shape, and are combined to operate as a shift register as a whole.

A clock path CKP for supplying a shift scan transfer clock CK to each module is provided in parallel with the shift scan path SSP.
Note that the embodiment of FIG. 5 shows a configuration in which data is transferred to all modules and registers in the variable wiring switch circuit by one shift scan path SSP. It is possible to provide several in one chip.

Further, the chip is provided with an input terminal PSDI for the data set in the register and an input terminal PCKI for the transfer clock CK corresponding to the start ends of the shift scan path SSP and the clock path CKP. Furthermore, corresponding to the end of the shift scan path SSP,
An output terminal PSDO for shift data is provided. Since the shift data output terminal PSDO is provided in this manner, it is possible to inspect whether the shift scan path SSP is abnormal.

FIG. 6 shows an example of a system clock φc supply method to each of the above modules. In this embodiment, the system clock φc is supplied by a tree-like wiring. Specifically, it is transmitted from the clock terminal PSCI provided on one side of the chip 100 to the center of the chip,
From there, it is supplied to the terminal circuit via a tree wiring network branched in an H shape. As a result, the wiring lengths from the clock terminal PSCI to the terminal circuit are made substantially equal to each other, and malfunctions due to clock skew are prevented. Since such a clock distribution system is known,
Detailed explanation is omitted.

FIG. 7 shows the variable analog module V.
A specific circuit example of the input amplifier 11 which constitutes AMa is shown. The input amplifier 11 of this embodiment is an operational amplifier OP1.
And an input resistor R0, a switch SW0 connected in parallel with the input resistor R0, and feedback resistors R1 and R connected between the output terminal and the inverting input terminal of the operational amplifier OP1.
2, R3, and switches SW1, SW2, SW3 connected in series with the resistors R1, R2, R3, respectively. By selectively turning on any one of the switches SW1, SW2 and SW3 by the data set in the register (REG1) in the control circuit 14,
The gain of the amplifier can be controlled.

Specifically, the resistance values of the resistors R1, R2 and R3 are set as R0 / 10, R0, 10R0, for example. When you want to amplify the input signal, switch SW
3 is set to the ON state, and the feedback resistor R3 having a larger resistance value than the value of the input resistor R0 is selected. On the contrary, when it is desired to attenuate the input signal, the switch SW1 is set to the ON state and the feedback resistor R1 having a smaller resistance value than the value of the input resistor R0 is selected.

By arranging the gain of the operational amplifier variably in this way, a gain corresponding to the magnitude of a signal to be processed is set for each variable analog module VAMa, and amplification and attenuation are performed with the set gain. Thus, the signal processing can be optimized. The setting range of the gain is not limited to 1/10 times, 1 times, and 10 times, and 1 times and 10 times.
Any magnification such as 2 times or 20 times may be used, and the setting step is not limited to 3 steps and may be 4 steps or more.

Further, in this embodiment, the input resistance R
A switch SW0 is provided in parallel with 0. When the switch SW0 is turned off, the operational amplifier operates as a voltage amplifier or a voltage attenuator, and when the switch SW0 is turned on, it operates as a current-voltage converter. Has been done. Therefore, when the operational amplifier of this embodiment is used, the analog input signal can be either voltage or current. The ON / OFF information of the switch SW0 for switching the function is also set in the register (REG1) in the control circuit 14. As a method of changing the gain, as described above, the feedback resistor R
In addition to the method of switching 1 to R3, a method of switching by setting a plurality of input resistors R0 having different resistance values in parallel,
There is a method of switching the current of the operational amplifier.

FIG. 8 shows a variable analog module VAM.
A specific example of the output amplifier 23 forming b is shown.
The operational amplifier OP1 shown in the figure operates in the same manner as the operational amplifier OP in the input amplifier 11 shown in FIG. 7, and a feedback resistance is provided between the output terminal and the inverting input terminal of the operational amplifier OP1. For example, a plurality of resistors R1, R2, and R3 whose resistance values are set to R0 / 10, R0, and 10R0 with respect to the input resistor R0 are provided in parallel with each other, and each resistor R1, R2,
Switches SW1, SW2, and SW3 are connected in series with R3, respectively, and the switch SW is switched by the gain setting data stored in advance in the register (REG2) in the control circuit 24.
One of SW1, SW2 and SW3 is selectively turned on.

Further, in this embodiment, the output amplifier 23
In order to operate as a voltage-current converter, the current detection resistor R4 connected between the output terminal of the operational amplifier OP1 and the force line side output terminal 26a of the circuit and the detected current are connected to each other. Feedback amplifier OP2 that feeds back to the inverting input terminal side of the operational amplifier OP1
And a correction operational amplifier OP3 for correcting the leakage current in the amplifier OP2. The feedback amplifier OP2 is connected to the inverting input terminal side resistor R6 and the feedback resistor R7 of 100 kΩ, and the correction operational amplifier OP3 is connected to the inverting input terminal side resistor R8 and the feedback resistor R9 of 50 kΩ and 100 kΩ, respectively. 100 kΩ is connected as the resistor R10 on the output terminal side.

In the output amplifier of the embodiment shown in FIG. 8, the switch SW4 is provided between the sense line side output terminal 26b of the circuit and the feedback resistors R1 to R3, and the output terminal of the operational amplifier OP1 and the feedback resistors R1 to R3. A switch SW5 is provided therebetween, a switch SW6 is provided between the output terminal of the operational amplifier OP1 and the inverting input terminal of the feedback amplifier OP2, and a switch R5 is provided between the output terminal of the feedback amplifier OP2 and the inverting input terminal of the operational amplifier OP1. SW7 is provided and switch S
When W4 is turned on and SW5 to SW7 are turned off, the output amplifier operates as a voltage-voltage converter, and the switch S
When W4 is turned off and SW5 to SW7 are turned on, the output amplifier operates as a voltage-current converter. The value of the resistor R5 is the same as that of the input resistor R0. When the output amplifier of this embodiment operates as a voltage-current converter, the magnitude of the output current Iout output from the force line side output terminal 26a is the input voltage Vi.
If n, then Iout = Vin / R4.

As the A / D conversion circuit 12 which constitutes the variable analog module VAMa and the D / A conversion circuit 22 which constitutes the variable analog module VAMb, there are known A / D conversion circuits and D / A conversion circuits. From the F of the present invention
Since a suitable type of PA can be selected and used, a specific circuit example is omitted. In addition, the voltage follower 25 that constitutes the variable analog module VAMb
Can also be configured by a general voltage follower composed of an operational amplifier in which the output of the D / A conversion circuit 22 is input to the non-inverting input terminal and the output is directly fed back to the inverting input terminal. Is omitted.

FIG. 9 shows a concrete circuit example of the variable wiring switch circuits DSW and ASW which are provided at the intersections of the wiring regions HLA and VLA and which can arbitrarily connect the respective wirings.
In FIG. 9, reference numerals A and B denote wirings provided in the horizontal wiring area HLA, and reference numerals C and D denote wirings provided in the vertical wiring area VLA. Is. A total of eight CMOS transmission switches TG1 to TG8 are provided so that two transmission switches are respectively interposed between the wirings A to D, and ON / OFF control data of these CMOS transmission switches are held. There is provided a register REG3 for operating the inverter and inverters INV1 to INV8 which invert the output signal of the register to generate the other control signal of the CMOS transfer switches TG1 to TG8.

The variable wiring switch circuits DSW and ASW are
Depending on the control data set in the register REG3, any two of the four wirings A to D can be connected. However, it is also possible to connect any three or all four wirings as needed. Further, control data for turning off all the transmission switches TG1 to TG8 may be set in the register REG3, and in this case, transmission of signals between the four wirings A to D is cut off. As a result, it is possible to prevent the wiring arranged in the same channel from being occupied by one module and becoming unavailable to another module.

Like the register REG1 of the control circuit 14 in the variable analog module VAMa shown in FIG. 2, the register REG3 is connected to the shift scan path SSP and is synchronized with the transfer clock CK supplied from the outside. It is configured to sequentially capture and hold the setting data SD serially supplied from the outside. The variable wiring switch circuits DSW and ASW, which are provided in a portion corresponding to each module input / output terminal of the vertical wiring area HLA and enable connection of any wiring in the wiring area HLA to each module input / output terminal, are provided. , A circuit having the same configuration as that of FIG. 9, but a circuit having another configuration may be used. For example, the wiring D (or B) and the transmission switches TG1, TG2 (or TG7, TG8) in the variable wiring switch circuit of FIG. 9 are omitted, and the connection between the wirings extending in three directions is arbitrarily switched. be able to.

In the variable wiring switch circuits DSW and ASW of this embodiment, the transmission switches TG1 to TG8 are used.
P-channel MOSFET and N-channel MOSFE as
Although a CMOS transmission switch in which T and T are connected in parallel is used, it is also possible to use a transmission switch that includes only one of a P-channel MOSFET and an N-channel MOSFET. By using the CMOS transfer switch, it is possible to reduce the level drop of the transmitted signal without increasing the gate control voltage.

Next, the procedure for constructing an analog / digital mixed on-chip system using the FPA of the above embodiment will be described with reference to the flowchart of FIG. First, the function of the on-chip system to be developed is determined, and the function of the on-chip system is determined by, for example, Spe
ctre-HDL (hardware description
A system design is performed by using a language (hardware description language) or the like (step S1). Next, this description is analyzed and the modules VLM and VA of the above embodiment are analyzed.
A function that can be realized by combining any of Ma and VAMb or a plurality of modules is selected, and each selected function is stored in the file FL1 as a function block (step S2). After that, circuit configuration data and control data in the module, which are required when the respective functions are realized by the modules VLM, VMa, and VAMb, are created and stored in the setting data file FL2 (step S3).

Subsequently, the module map data indicating which module is arranged in the FPA to be used and how it is arranged is read from the file FL3, and it is determined to which module in the FPA each functional block in the functional block file FL1 is allocated. At the same time, connection information between modules is created according to the allocation and stored in the connection data file FL4 between modules (step S4).

Specifically, it is determined which wiring in the wiring areas HLA, VLA is used to connect the terminals of the two modules of interest, and the variable wiring switch circuit required for the connection is turned on. , Off setting information is determined. At this time, prepare a mapping program that supports the determination of the optimal module allocation and the optimal connection between modules, and use this to automatically perform the mapping process on the workstation etc. can do.

Then, the data stored in the setting data file FL2 and the inter-module connection data file FL4 is read out, and the data is rearranged so that it can be transferred to the corresponding module on the FPA and the register in the variable wiring switch circuit. The serial data from the FPA to the serial data input terminal PSDI of the FPA and the transfer clock C corresponding to the transfer speed of this data.
K is given to the transfer clock input terminal PCKI of the FPA. In this way, the transferred data is set in each module and the register in the variable wiring switch circuit, whereby an on-chip system having a desired function is constructed on the FPA (step S5).

As such an on-chip system,
A custom LSI that requires only a small amount or a tester for inspecting a semiconductor integrated circuit can be considered. Conventionally, there has been proposed a technique of forming a tester for inspecting a logic LSI by using an FPGA which is composed of a variable logic circuit and which can form an arbitrary logic. However, even in the case of the logic LSI, the potential of the terminal is set to a desired level. A so-called DC test for inspecting whether or not the current at a terminal has a desired value is necessary, and when a logic tester is configured using an FPGA, a separate DC test device is required. On the other hand, if the FPA of the present invention is used, logic LSI
It is possible to construct a tester capable of performing both the inspection for examining the logical function of the above and the inspection for examining the DC-like characteristic on one FPA, and it is possible to greatly reduce the cost required for the test.

Further, the FPA of the above-mentioned embodiment is an analog / digital mixed on-chip system under development, and it is desired to verify (simulate) using hardware before developing and manufacturing it in a semiconductor integrated circuit. Can be used. Hereinafter, this hardware simulation will be described with reference to FIG. When developing an analog / digital mixed on-chip system, the specification of the entire system is first designed (step S1).
1). Then, the functions of the digital section and the analog section are designed respectively (step S12). Next, step S2
The system designed in 1 is constructed using the FPA of the above-mentioned embodiment, and it is verified whether the desired operation is performed (step S1).
3). At this time, F in the above embodiment of the system to be verified
Construction into the PA can be performed by the same procedure as described in steps S2 to S5 of FIG.

Specifically, the analog / digital mixed on-chip system is constructed in the FPA by using the functional design data described in HDL. Then, a test signal is input to the constructed system to operate it, and the output signal is monitored to determine whether or not the function of the system is the desired one (step S14). If a defect is found, step S11 or The process returns to S12 and the design is changed.

If the desired operation is obtained by the verification in step S13, the circuit design (ASIC or custom LSI) for realizing the same function on the semiconductor chip based on the above design data is changed by the DA tool. Etc., and a board for inspecting this chip is created in parallel (step S15). Then, the prototype chip is mounted on the boat for final verification of the system (step S16).

If a defect is found here, the process returns to step S11 or S12 to change the design (step S17). Conventionally, the verification in step S13 was possible for the digital part, but such verification could not be performed for the analog part. FP of the above embodiment
By using A, the same hardware verification can be performed for the analog part. As a result, when developing an analog / digital mixed on-chip system, a design defect can be found and corrected at an earlier stage than in the past, and the development period can be shortened.

12 and 13 show another circuit example of the variable analog module VAM. Of these, FIG.
Of the variable analog module of the output buffer circuit 1 in the module VAMa including the AD conversion circuit 12.
A correction circuit 17 capable of correcting the output is provided in the next stage of 3. Further, the control circuit 14 is provided with a dedicated register capable of retaining the data for trimming of the correction circuit 17 or a register or memory having a capacity capable of retaining the data together with other setting data. The correction circuit 17
Is, for example, the variable analog module VAM of this embodiment.
Trimming that can convert the output value to the expected value when it is found that the module output has deviated from the desired value due to the characteristic variation of the amplifier etc. as a result of the DC test of the FPA equipped with a. It is configured to have a function. Note that a similar correction circuit can be provided in the preceding stage of the input buffer circuit 21 of the variable analog module VAMb incorporating the DA conversion circuit 22 as shown in FIG.

The variable analog module of FIG. 13 is provided with a random number generation circuit 28 in addition to the correction circuit 27.
The random number generation circuit 28 produces the same effect as that when a random test signal is input from the outside by varying the analog level of the output when testing the FPA having the variable analog module VAMa of this embodiment, for example. be able to. Therefore, it can be used as a test circuit or a test device that gives a test signal in a burn-in device that tests an LSI while operating it under high temperature and high voltage, and thus the function of the device can be improved as compared with a burn-in device having a similar function. It can be simplified and the price can be greatly reduced.

A similar random number generation circuit can be provided in the variable analog module VAMa having the AD conversion circuit 12 built therein. In this case, the module VA
A random test pattern can be generated from Ma to test a variable logic module or digital circuit. Further, in FIG. 13, the correction circuit 27 may be omitted and the module may be provided with only the random number generation circuit 28.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the above embodiment, the FPA is configured by the first variable analog module of analog input digital output, the second variable analog module of digital input analog output, and the variable logic module. An FPA composed of a first variable analog module having an output and a variable logic module and an FPA composed of a second variable analog module having a digital input analog output and a variable logic module are also conceivable.

In the embodiment, three types of modules are used for F
Although the PA is configured, it may be configured by four types of modules in addition to the third variable analog module having analog input and analog output. Here, the module of analog input and analog output may be configured only by an analog circuit, or may convert an analog signal into a digital signal and perform some processing, and then convert it into an analog signal again and output it. The module may be a combination of the circuit of FIG. 2 and the circuit of FIG.

In the above description, the invention made by the present inventor was mainly described by taking as an example a FPA formed on one semiconductor chip, which is a field of application which is the background of the invention. However, a plurality of FPAs or FPAs and FPGAs, etc. L
It can also be used in the case of combining electronic components including SI to form a board system or the like.

[0072]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, according to the present invention, the analog / digital mixed system having an arbitrary function can be configured on the user side, and the degree of freedom in the arrangement of the circuits at the time of constructing the analog / digital mixed system having the desired function is increased. A highly programmable semiconductor integrated circuit can be realized.

Further, according to the present invention, when an analog / digital mixed loading system having a desired function is constructed,
Even when a signal is transmitted and received between circuits which are relatively distant from each other, it is possible to prevent the level of the analog signal from being lowered by the wiring resistance or the like. Furthermore, when the semiconductor integrated circuit of the present invention is used, a simple tester capable of performing a test without using an expensive test apparatus can be configured, and the newly developed analog / digital mixed system can be used as a semiconductor integrated circuit. It is possible to realize a hardware simulator capable of verifying whether or not it operates normally before manufacturing or trial manufacturing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of an FPA according to the present invention.

FIG. 2 is a configuration diagram showing a specific example of a first variable analog module having an AD conversion circuit configuring an FPA according to the present invention.

FIG. 3 is a configuration diagram showing a specific example of a second variable analog module having a DA conversion circuit configuring the FPA according to the present invention.

FIG. 4 is an explanatory plan view showing an example of a wiring structure of a wiring region suitable for the FPA according to the present invention.

FIG. 5 is a block diagram showing an example of a data transfer method of data set in each module constituting the FPA according to the present invention and a register in the variable wiring switch circuit.

FIG. 6 is a block diagram showing an example of a system clock φc supply method to each module constituting the FPA according to the present invention.

FIG. 7 is a circuit configuration diagram showing a specific circuit example of an input amplifier included in the variable analog module of the FPA of the embodiment.

FIG. 8 is a circuit configuration diagram showing a specific circuit example of an output amplifier included in the variable analog module of the FPA of the embodiment.

FIG. 9 is a circuit diagram showing a specific example of a variable wiring switch circuit which constitutes an FPA according to the present invention.

FIG. 10 is a flowchart showing an example of a procedure for constructing an analog / digital mixed on-chip system.

FIG. 11 is a flowchart showing an example of a procedure for developing an analog / digital mixed on-chip system using the FPA according to the present invention.

FIG. 12 is a configuration diagram showing another embodiment of the variable analog module constituting the FPA according to the present invention.

FIG. 13 is a configuration diagram showing still another embodiment of the variable analog module constituting the FPA according to the present invention.

[Explanation of symbols]

11 Input Amplifier 12 A / D Conversion Circuit 13 Output Buffer Circuit 14 Control Circuit 21 Input Buffer Circuit 22 D / A Conversion Circuit 23 Output Amplifier 24 Control Circuit VLM Variable Logic Module VAMa Variable Analog Module VAMb D with Built-in A / D Converter ? Variable analog module DSW with built-in A converter, ASW variable wiring switch circuit HLA, VLA wiring area I / O1 to I / O4 I / O buffer section FL force line SL sense line GL guard wiring

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H03M 1/66 H01L 27/04 F T E 21/82 P T F term (reference) 5F038 BH10 BH19 CA03 CA07 CD06 CD08 CD20 DF01 DF03 DF12 DF16 DF17 DT06 DT15 EZ09 EZ20 5F064. DA06

Claims (10)

[Claims] 1. A semiconductor chip is provided with a plurality of variable logic circuit cells whose logical functions can be set by a program and a plurality of variable analog circuit cells whose analog characteristics can be set by a program. A semiconductor integrated circuit device having the plurality of variable logic circuit cells and the plurality of variable analog circuit cells dispersedly arranged in a periodic repeating pattern. 2. The semiconductor integrated circuit device according to claim 1, wherein the variable analog circuit cell receives an analog signal and outputs a digital signal. 3. The semiconductor integrated circuit device according to claim 1, wherein the variable analog circuit cell receives a digital signal and outputs an analog signal. 4. The variable analog circuit cell is a first variable analog circuit cell that inputs a digital signal and outputs a digital signal, and a second variable analog circuit cell that inputs a digital signal and outputs an analog signal. The semiconductor integrated circuit device according to claim 1, wherein: 5. A first wiring region extending between the variable logic circuit cell and the variable analog circuit cell, wherein a plurality of wirings for connecting the circuit cells are formed and extending in a first direction. A second wiring region extending in the second direction is provided, and a wiring belonging to the first wiring region and a wiring belonging to the second wiring region are electrically connected to each other at the intersection of the first wiring region and the second wiring region. 5. The semiconductor integrated circuit device according to claim 1, further comprising a variable wiring switch means that enables a physical connection. 6. The variable logic circuit cell and the variable analog circuit cell each include information holding means for holding information regarding a circuit configuration inside the cell, and the information holding means of each circuit cell is connected to a common shift scan path. 6. The semiconductor integrated circuit device according to claim 1, wherein the information held by the information holding means is provided from outside the chip via the shift scan path. 7. One of the first variable analog circuit cell and the second variable analog circuit cell is provided by any two wires provided in the first wiring region and the second wiring region. 5. The semiconductor integrated circuit device according to claim 4, wherein an analog signal is transmitted by using a force line and the other as a sense line. 8. The peripheral portion of the main surface of the semiconductor chip,
An input / output unit is provided in which a plurality of input / output buffer circuits that perform transmission / reception of signals between an internal functional circuit configured by the variable logic circuit cell and the variable analog circuit cell and an external device are arranged, 8. The semiconductor according to claim 1, wherein the input / output section is provided with a plurality of input / output buffer circuits for digital signals and input / output buffer circuits for analog signals in a distributed manner. Integrated circuit device. 9. A first clock supply system wiring for supplying a first clock signal for transferring holding information to each of the information holding means via the shift scan path is provided in parallel with the shift scan path. 7. The semiconductor integrated circuit device according to claim 6, further comprising a second clock supply system wiring having a tree structure for supplying a second clock signal for operating each of the circuit cells. 10. The step of generating design data described by using a hardware description language so as to have a desired digital function and an analog function, and based on the design data, the method according to claim 1. To build a mixed analog / digital system in the semiconductor device of
Including a step of inputting a test signal into the constructed system and operating the system to determine whether or not a function is desired from an output signal; and a step of correcting the design data based on the determination result. And a method for designing a semiconductor integrated circuit device.