JP4673533B2 - Integrated circuit with dedicated and programmable logic - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit having programmable logic such as a field programmable gate array, dedicated logic such as an ASIC type device, and an interface for communication between the programmable device and the dedicated device.
[0002]
[Prior art]
The semiconductor industry is driven by a desire to provide a higher level of integration. For higher levels of integration, silicon space and cost are reduced while performance and reliability are increased. However, higher levels of integration lead to greater specificity. For example, application specific integrated circuits (ASICs) are often highly specific devices that merely serve the needs of a single customer.
[0003]
Programmable logic devices such as field programmable gate arrays (FPGAs) are a variety of integrated circuit chips that can be selected by the user that can be configured by the user to implement specific functions for the user. It has internal circuit logic with a connected state. Programmable logic is diverse, but significant design challenges in terms of size, routing, and pinout stability when mapping large and complex functions onto a silicon platform containing programmable logic Is present.
[0004]
Programmable logic devices can be linked with separate dedicated devices, but there are on / off-chip delays associated with them, large board area, and high cost. Furthermore, it is possible to program the programmable logic to perform the desired function, but this is an expensive proposal and the resulting performance is often unacceptable.
[0005]
[Problems to be solved by the invention]
Therefore, there is a need for a single integrated device that combines the flexibility of programmable logic with the performance and reliability of dedicated devices.
[0006]
[Means for Solving the Problems]
Programmable logic such as a field programmable gate array and a dedicated device such as an ASIC type device are integrally coupled on a single integrated circuit with an antifuse-based interface. Configurable non-volatile memory using programmable logic techniques provides parameter settings for a dedicated device or its convenient on-chip configuration. In one embodiment, the platform for programmable logic is half of existing programmable logic devices, which advantageously eliminates the need to configure programmable logic. Dedicated devices can implement complex but often required functions, such as bus interfaces to industry standard buses, while programmable circuitry allows the user to implement custom functions. Placing both dedicated devices and programmable logic on the same chip allows for high processing power between circuits, but the communication is internal to the integrated circuit chip, so there are more I / O pins are not required.
[0007]
Programmable logic can include a clock network that receives clock signals from input / output terminals as well as from a clock network within a dedicated device. Thus, the programmable logic can operate at a frequency independent of the dedicated circuit. The input / output clock terminals for programmable logic are usually on one side of the chip closest to the programmable logic, while the input / output clock terminals for dedicated devices are on the opposite side of the chip closest to the dedicated devices. It's above. The clock network distributes the clock signal to both programmable logic and dedicated devices.
[0008]
The interface between the dedicated device and the programmable logic has a number of conductors with buffers and test circuitry. The test circuit includes a PMOS test transistor and an NMOS test transistor, the gates of which are coupled to the output terminal of the buffer. The PMOS test transistor is coupled between the voltage supply and the output terminal, while the NMOS test transistor is coupled between the ground supply and the different output terminal. The output terminal of the PMOS test transistor is coupled to the output terminal of the inverter. During the test mode, the inverter is coupled to a voltage supply. The PMOS test transistor is much larger than the NMOS transistor in the inverter. Thus, when the PMOS test transistor is off, the inverter drives the output terminal low, but when the PMOS test transistor is on, the PMOS test transistor drives the output terminal high. . The output terminal of the NMOS test transistor is coupled to the output terminal of another inverter that is coupled to the ground source during the test operation. The NMOS test transistor is much larger than the PMOS transistor in the inverter. The test circuit allows the buffer to be beneficially tested without programming an antifuse coupled to the conductor.
[0009]
According to another embodiment of the present invention, the input / output terminals at and around the interface between the programmable logic and the dedicated device are tested using JTAG registers. The path of the test signal through the JTAG register can be selected to pass around the periphery of both the programmable logic and the dedicated device, or through the interface and around the periphery of the dedicated device.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a schematic diagram of an integrated circuit 10 according to one embodiment of the present invention. Integrated circuit 10 has programmable logic 12 and dedicated logic 14, each of which has an I / O pin for connection to an external circuit. Interface 16 connects programmable logic 12 to dedicated logic 14. Integrated circuit 10 can be thought of as a programmable logic device that “embeds” dedicated logic 14 on the same piece of silicon, or vice versa, ie as a dedicated device with “embedded” programmable logic 12. Is possible. Programmable logic 12 is, for example, a field programmable gate array (FPGA) or other circuit with user programmable circuit connections, while dedicated logic 14 is a fixed circuit that implements the desired function. For example, the dedicated logic 14 can be an application specific circuit that performs functions such as forming an interface with an industry standard bus.
[0011]
FIG. 1 further shows a programmable read only memory (PROM) 18. PROM 18 stores data that configures or sets parameters for dedicated logic 14 and may be implemented using programmable logic 12 techniques. On the other hand, the PROM 18 can be replaced with an external or internal EEPROM that achieves the same purpose.
[0012]
Beneficially, the integrated circuit 10 with connected programmable logic 12 and dedicated logic 14 is only for the user to provide the formability and flexibility found in programmable logic such as an FPGA. Rather, it provides the guaranteed functionality, ease of use, and high performance found in dedicated devices such as ASICs.
[0013]
FIG. 2 shows how to form one large simplified schematic of one embodiment of programmable logic 12 and part of interface 16 in FIGS. 2A, 2B1, 2B2, 2B3, 2C, 2D, 2E, 2F1, 2F2, 2F3, 2G, 2H, 2I, 2J1, 2J2, 2J3, 2K, 2L, 2M, 2N1, 2N2, 2N3, 2P, 2Q, 2R1, 2R2, 2R3, 2S, 2T FIG. Each of the boxes in FIG. 2 has a character for the one displayed in FIGS. 2A-2T. For example, “A” in the upper left box represents FIG. 2A. As can be seen from FIG. 2, the configuration of FIG. 2A forms a boundary with 2B on the right side and the boundary with the configuration of FIG. 2E on the lower side.
[0014]
FIG. 2 shows the two configurations of FIG. 2B disposed between the configurations of FIGS. 2A and 2C, and the two configurations of FIG. 2B are between the configurations of FIGS. 2C and 2D in the composite diagram. Arranged and the configuration of FIG. 2B is 3 to make the programmable logic 12 wider and to increase the number of gates to allow programming to form more complex circuits from the programmable logic 12. It can be double or more. It should be further understood that the corresponding configurations in FIGS. 2F, 2G, 2N, 2R are similarly iterative. Similarly, the configuration of FIG. 2F increases once the programmable logic 12 height and once between the configurations of FIGS. 2B and 2J to increase the number of gates and complexity of the circuit implemented from the programmable logic 12. It is possible to repeat the above. The repetitive portion of an integrated circuit that includes a module of logic elements and a portion of the programmable interconnect and its programming structure (eg, 2F configuration) is called a macrocell. Various aspects of the programmable integrated circuit of FIG. 2 are described in further detail below.
[0015]
The operation of the programmable logic as shown in FIGS. 2A-2T is described in US Pat. No. 5, entitled “Programmable Architecture for a Programmable Integrated Circuits Integrating Antifuses”. No. 825,201, which is incorporated herein by reference.
[0016]
FIGS. 2Q-2T show the portion of interface 16 between programmable logic 12 and dedicated logic 14 (shown in FIG. 1). As can be seen in FIG. 2R1, the interface between programmable logic 12 and dedicated logic 14 has an array of buffers 20 and programmable antifuses 22 represented by "X" symbols. . The antifuse 22 can be, for example, an amorphous silicon antifuse or other suitable antifuse structure such as an oxide-nitride-oxide antifuse. For example, U.S. Pat. No. 5,502,315, entitled "Electrically Programmable Interconnect Structure Having a PECVD Amorphous Silicon Element" with PECVD amorphous silicon elements. , 424, 655, and U.S. Pat. No. 5,557,136, entitled “Programmable Interconnect Structures and Programmable Integrated Circuits”. Related to the fuse structure. Since good Referring to them, Note Tokomu herein those patents by reference.
[0017]
FIG. 2R1 shows a portion of the interface 16 having a buffer 20 for input and output of signals from the dedicated logic 14. The silicon antifuse 22 allows for the programmable routing of these signals into the programmable logic 12. The small size of the amorphous silicon antifuse allows a programmable element 22 to be placed at each intersection of the routing lines in the interface 16, thereby providing a high level of routing capability in the programmable logic 12 of the interface 16. is doing.
[0018]
Also shown in FIG. 2R1 is PROM 18, which has an array of buffers 24 and programmable antifuses 26. There are two antifuses coupled to each buffer. One antifuse is programmed to connect the buffer to a high voltage and the other antifuse is programmed to connect the buffer to a low voltage. As is well understood by those skilled in the art, once an antifuse is programmed, it cannot be released from the programmed state. Thus, the array of programmable antifuses 26 provides a non-volatile, formable memory.
[0019]
The dedicated logic 14 of the integrated circuit 10 can implement any desired function, such as, for example, implementing a peripheral component interconnect (PCI) interface. On the other hand, dedicated logic 14 may implement a variety of related or alternative functions that may otherwise be implemented on multiple separate devices.
[0020]
FIG. 3 is a schematic diagram of an integrated circuit 30 according to another embodiment of the present invention. Integrated circuit 30 includes dedicated logic, programmable logic 12, interface 16, and PROM 18. However, in the integrated circuit 30, the dedicated logic has a number of dedicated devices 34, 36, 38. One or more of the desired dedicated devices 34, 36, 38 can be activated by appropriate programming of the programmable elements in the interface 16 or programmable logic. For example, a programming array of programmable antifuses 22 (shown in FIG. 2R1) can connect one dedicated device to a macrocell in programmable logic 12. Thus, although the embedded circuit 30 is on a piece of silicon, three different functions can operate independently. Therefore, it is not necessary to manufacture three separate circuits. In this embodiment, it may be desirable to route all inputs / outputs through programmable logic 12 so that I / O pins are not wasted on unused devices. On the other hand, volatile memory or EEPROM can configure integrated circuit 30 and dynamically select which of the dedicated devices is active.
[0021]
Although the dedicated devices 34, 36, 38 are shown as separate devices, it should be understood that the devices 34, 36, 38 can partially or completely overlap. A programmable connection of interface 16 to device 34, 36, 38 controls that a particular dedicated device 34, 36 or 38 is activated.
[0022]
FIG. 4 is a simplified schematic diagram of a field programmable gate array (FPGA) 50. As shown in FIG. 4, the FPGA 50 has two halves 52 and 54, each of which includes a logic array 56 and an input / output circuit 58. A clock circuit 60 is between the logic array 56 and distributes the clock signal to the two halves 52 and 54. The FPGA 50 is a completely realizable circuit. For example, the halved portion 52 has the configuration shown in FIGS. 2A to 2P, and the other halved portion 54 is a mirror image of the halved portion 52.
[0023]
To generate the integrated circuit 10 (FIG. 1), the halved portion 52 of the FPGA 50 forms the programmable logic 12 and the dedicated logic 14 replaces the other halved portion 54. In order to connect the dedicated logic to the programmable logic, the programmable interface illustrated in FIGS. 2Q to 2T is added. Thus, the halved portion of the FPGA 50 with the addition of the interface 16 provides a platform for generating the integrated circuit 10. The need for designing new programmable logic is disclosed by using all or part of the structure or layout of existing programmable logic devices as a platform for integrated circuit 10. Furthermore, the same platform can accept a variety of different dedicated devices. For example, the same platform may include a PCI bus interface circuit, in which case the programmable logic forms a user programmable interface to other ICs in the PCI device, and the platform includes a processor. In which case the programmable logic provides a user programmable interface to the processor. Furthermore, having common programmable logic in different devices simplifies the task of creating programming tools that configure the programmable logic to the needs of the user.
[0024]
FIG. 5 shows an interface between a plurality of macro cells 70 a, 70 b, 70 c, 70 d, 70 e, 70 f in the programmable logic 12 and the dedicated logic 14. Routing lines for transferring signals between dedicated logic 14 and programmable logic 12 or PROM 18 are evenly distributed among all macrocells. However, the routing line connections in macrocells 70a-70f are in accordance with the logic to be implemented. For example, integrated circuit 10 has 264 bits from programmable logic 12 to dedicated logic 14, has 264 bits from dedicated logic 14 to programmable logic 12, and has 528 bits from PROM 18 to dedicated logic 14. is doing. As described above, since the interface to each macrocell includes a number of routing resources comprising an array of programmable antifuses 22, the interface to each macrocell has a high level of routing possibilities. Yes.
[0025]
FIG. 6 is a schematic diagram of a clock interface 80 between programmable logic 12 and dedicated logic 14. The clock interface 80 includes a number of routing resources 82 that are routed throughout the programmable logic 12. Pads 84a, 84b, 84c, 84d, 84e, 84f, 84g that receive the clock signal are coupled to routing resource 82. Some of these pads, such as pads 84e-g, can be disposed on the opposite side of the circuit from other pads, such as pads 84a-d. Accordingly, conductors from pads 84e-g are routed to routing resource 82 via dedicated logic 14.
[0026]
Pad 86 receives a clock signal DCLK that drives dedicated logic 14 and is therefore coupled to routing resources 88 within dedicated logic 14. It is desirable for the programmable logic 12 to receive a clock signal that drives the dedicated logic 14, so that both the programmable logic 12 and the dedicated logic 14 are driven at the same timing. Accordingly, pad 86 is also coupled to at least one of routing resources 82 via buffer 90. It is also desirable for dedicated logic 14 to receive a clock signal that drives programmable logic 12. Accordingly, at least one of the pads 84a-g, such as pad 84d, is coupled to the routing resource 92 within the dedicated logic 14 via the buffer 94. In one embodiment of the invention, the clock signal lines and I / O pads are dedicated for that purpose and are separate from the data signal lines and I / O pads. However, additional buffers and routing resources can be used if desired. A more detailed configuration of the clock interface 80 is shown, for example, in FIG.
[0027]
In accordance with another aspect of the present invention, the interface 16 includes a test circuit that allows the programmable logic 12, dedicated logic 14, and interface 16 to be tested prior to programming the programmable logic 12. Yes. FIG. 7 is a schematic diagram illustrating a circuit for testing a buffer at interface 16. In FIG. 7, buffers 100 [0] through 100 [n-1] are shown, which receive signals PLout [0] through PLout [n-1] from programmable logic 12 during the normal mode. Also, signals DLin [0] to DLin [n−1] are generated for the dedicated logic 12. Each buffer 100 [i] has a NAND gate 102 [i] and an inverter 104 [i] where i is 0 to n-1. One input terminal of each NAND gate 102 [i] receives a corresponding signal PLout [0] from the programmable logic. The other input terminal of each NAND 102 [0] to 102 [n-1] receives an output signal from a corresponding one of multiplexers 103 [0] to 103 [n-1].
[0028]
A select signal to the multiplexers 103 [0] to 103 [n-1] controls whether the buffers 100 [0] to 100 [n-1] operate in the normal mode or the test mode. In the normal mode, the select signals are the multiplexers 103 [0] to 103 [n-1] and the enable signals EN [0] to EN [n-1] are sent to the NAND gates 102 [0] to 102 [n-1]. To each of the second input terminals. Each of enable signals EN [0] to EN [n-1] is high (to disable) a corresponding one of buffers 100 [0] to 100 [n-1] during normal mode operation. Low).
[0029]
In the test mode, the select signal passes through the multiplexers 103 [0] to 103 [n-1] and is output from the registers 105 [0] to 105 [n-1], respectively. n−1] is applied to the second input terminals of the NAND gates 102 [0] to 102 [n−1]. The registers 105 [0] to 105 [n-1] are connected in a chain, and i is 0 to n-2, and the output terminal of the register 105 [i] is connected to the input terminal of the register 105 [i + 1]. ing. The clock signal Clk controls the latching of the value of the input test signal Tin into the register 105 [0] and the propagation of the value through the register chain 105 [0] to 105 [n-1].
[0030]
The test circuit 101 includes PMOS transistors 106 [0] to 106 [n-1] and NMOS transistors 108 [0] to 108 [n-1], and buffers 100 [0] to 100 [n] associated with gates. -1]. As shown in FIG. 7, each of the PMOS transistors 106 [0] to 106 [n-1] is between the supply voltage Vcc and the test line 201, and the NMOS transistors 108 [0] to 108 [n-1]. ] Between the ground and the test line 205. Low current pull-down device 202 maintains test signal OUTP on line 201 at a low voltage when none of PMOS transistor 206 is on. If any of the output buffers 100 [0] to 100 [n−1] has a high output signal, the PMOS transistors 106 [0] to 106 [n−) coupled to the test line 201. 1] pulls the test signal OUTP high (Vcc). Similarly, when all of NMOS transistors 108 [0] to 108 [n-1] are off, low current pull-up device 206 maintains test signal OUTN high on line 205 and buffer 100 [ When any one of 0] to 100 [i] has a low output signal, one or more NMOS transistors 108 [0] to 108 [n−1] have a low test signal OUTN. Pull on.
[0031]
In order to test the buffers 100 [0] to 100 [n-1], the select signal Sel causes the multiplexers 103 [0] to 103 [n-1] to generate the signals T [0] to T [n-1]. Route to NAND 102 [0] through 102 [n-1]. The signals PLout [0] to PLout [n−1] to the other input terminals of the NAND gates 102 [0] to 102 [n−1] are high from the unprogrammable programmable logic 12. US Pat. No. 5,302,546, entitled “Programming of Antifuses”, incorporated herein by reference, describes an FPGA having an output signal that is high when the FPGA is not programmed. It is described. Therefore, the voltage states of the test signals T [0] to T [n−1] control the output signals from the buffers 100 [0] to 100 [n−1]. If the data signal T [i] applied to any NAND gate 102 [i] is high, the corresponding inverter 104 [i] generates a high signal, which causes the NMOS test transistor 108 [i] to Turn on and turn off PMOS test transistor 106 [i]. The NMOS transistor 108 [i] pulls down the signal OUTN when it is on. On the other hand, when the data signal T [i] is low, the inverter 104 [i] generates a low signal, which turns off the NMOS test transistor 108 [i] and turns on the PMOS test transistor 106 [i]. . The PMOS transistor 106 [i] pulls up the signal OUTP when it is on.
[0032]
Inverters 204 and 208 generate output signals TOUT1 and TOUT2 representing the states of signals OUTP and OUTN on test buses 201 and 205, respectively. The test process applies a set of values to the input test signal TIn and tests the operation of the buffers 100 [0] to 100 [n-1] by observing the resulting state of the output test signals TOUT1 and TOUT2. For example, if the test signal Tin stays low and therefore all of the test signals T [0] to T [n−1] are low, then the properly operating buffers 100 [0] to 100 [n−1] Turns on all PMOS transistors 106 [0] to 106 [n-1] and turns off all NMOS transistors 108 [0] to 108 [n-1]. In this case, signals OUTP and OUTN are high and signals TOUT1 and TOUT2 from inverters 204 and 208 are both low. However, any of the buffers 100 [0] to 100 [n-1] has failed, and therefore one or more of the output signals DLin [0] to DLin [n-1] If low, one or more of the NMOS transistors 108 [0] to 108 [n-1] pulls the signal OUTN low and the test signal TOUT2 is high and is defective. Represents a buffer.
[0033]
If signal TIn is raised high for a single clock cycle while all of signals T [0] through T [n-1] are low, then from register 105 [0] to 105 [n-1]. Start a high voltage state propagating via signals T [0] to T [n-1]. A high signal T [i] turns off the corresponding transistor 106 [i] and turns on the corresponding transistor 108 [i]. Accordingly, at least one of the transistors 108 [0] to 108 [n-1] should be on during the entire time that the high state is propagating through the registers 105 [0] to 105 [n-1]. As such, the test output signal TOUT2 should remain high. If the test output signal falls low during any clock cycle i after raising signal TIn, buffer 100 [i] has failed and signal T [i] is high. The output signal DLin [i] is not raised to a high state. The buffer causing this malfunction can be identified from the time when the state of the signal TOUT2 changes.
[0034]
A similar test pattern for signal TIn can raise all of signals T [0] to T [n-1] to a high state and drop the voltage state of signal TIn to a low for one clock cycle. Is possible. It is also possible to use the test pattern. In this way, it is possible to identify individual defective buffers. The described test allows to effectively test the interface buffers 100 [0] to 100 [n-1] without programming programmable elements of programmable logic.
[0035]
A test circuit similar to that shown in FIG. 7 can also be used to test buffers that carry signals from dedicated logic to programmable logic. In addition, two types of buffers can be connected in the same scan chain or in separate scan chains for testing purposes. FIG. 8 illustrates an interface buffer circuit 100 that receives the signal FPGAin from the programmable logic 12 and generates the signal PCIout to the dedicated logic 14 and an interface that receives the signal PCIin from the dedicated logic 14 and generates the signal FPGAout to the programmable logic 12. 3 is a schematic diagram showing a buffer 110. FIG. Interface buffer circuit 100 includes transistors 106 and 108 in the manner described above for input multiplexer 103, NAND gate 102, inverter 104, and similarly numbered elements. Signals con0b and Datain in FIG. 8 correspond to the signals EN [i] and T [i] in FIG.
[0036]
The interface buffer circuit 110 includes an input multiplexer 112, a first inverter 114, a second inverter 115, a PMOS transistor 116, and an NMOS transistor 118. The interface buffer circuit 110 is different from the interface buffer circuit 100 in that it has enable signals con5 and con9. When the enable signal is connected in this manner, the NAND gate 102 is replaced by the inverter 114, and the multiplexer 112 is either the signal PCIin from the dedicated logic 14 or the test signal Datain to generate the output signal FPGAout. Either can be selected. The PMOS transistor 116 and the NMOS transistor 118 have their gates coupled to receive the output signal FPGAout, and pull up and pull down the respective signals inp and inn, respectively, according to the state of the signal FPGAout. Signals inn and inp are on the test bus for a set of buffers 110.
[0037]
FIG. 9 shows an interface buffer circuit 120 used between the PROM 18 and the dedicated logic 14. The interface buffer 120 includes a multiplexer 123, a NAND gate 122, an inverter 124, a PMOS transistor 126, and an NMOS transistor 128, which substantially correspond to the corresponding elements 103, 102, 104, 106, 108 of FIG. Is the same. The interface buffer circuit 120 is different from the interface buffer circuit 100 in input and output signals PCIROMin and PCIROMout and test signals ROMn and ROMp. Signal PCIROMin represents the data bits from PROM 18. The signal PCIROMout represents the data bits that pass to the dedicated logic 14. Test signals ROMn and ROMp are signals on separate test buses (not shown) for testing a set of interface buffers 120 in the same manner that test signals outn and outp test a set of interface buffers 100. It is.
[0038]
FIG. 10 is a schematic diagram of a sensing circuit 210 coupled to test transistors 116 and 118 in a set of interface buffers 110. The detection circuit 210 performs the same function as the combination of the pull-down 202, the pull-up 206, the inverter 204, and the inverter 208 described above. Test transistors 126 and 128 in interface buffer 120 can be coupled to a similar sensing circuit. The signals inp and inn to the detection circuit 210 have levels according to the conductivity of the transistors 116 and 118, respectively. The sensing circuit 210 also receives a test signal at terminal PCItst that is high during the test period. Test signal PCItst is applied to the select terminals of multiplexers 212 and 214 and is received by inverters 216 and 220. When signal PCItst is high, the combination of inverters 216 and 218 provides a low current drive signal to pull up the bus carrying signal inn, and inverter 220 pulls down the bus carrying signal inp. A low current drive signal for supplying
[0039]
The signals gcnr and gcnd are test signals similar to the signals inn and inp from other test buses (not shown). Inverter 213 provides a low current bias device for the test bus carrying signal gcnd. Inverters 215 and 217 provide a low current bias device for biasing the test bus carrying signal gcnr, and signal gckchk pulls up the test bus for signals gcnd and gcnr. Or pull down. Multiplexers 212 and 214 select which of test signals gcnr, inn, gcnd, and inp is applied to inverters 224 and 222 to generate output signals padnr and padnd at the I / O pads of the integrated circuit.
[0040]
FIG. 11 is a schematic diagram illustrating the interconnection of interface cells 130, each interface cell having an interface buffer type 100, 110, 120 and an associated test structure. Although FIG. 11 shows only two interface cells 130 [i] and 130 [i + 1], in an actual device, a large number of cells can be coupled in series. For example, in one embodiment, there are 264 cells of the interface buffer that are coupled together. Furthermore, it is not necessary for each mark cell to have the same number of interface buffers 100, 110, 120. For example, in one embodiment, each interface cell has six interface buffers 100, six interface buffers 110, and twelve interface buffers 120.
[0041]
In each interface cell 130 [i], the data register 105 [i] supplies the test data signal T [i] to the interface buffer in the cell 130. Data register 105 [i] receives a test signal T [i-1] from a previous cell (not shown) or from the input / output terminal if cell 130 [i] is the first cell in the series. The output terminal of the data register 105 is connected to each buffer 100, 110, 120 in the interface cell 130 [i] and to another data register 105 [i + 1] in the next interface cell 130 [i + 1]. i]. Therefore, the same input test signal TIn as described in detail with reference to FIG. 7 can be used to test all of the interface buffers 100, 110, and 120.
[0042]
Since the register in each cell provides a test signal T [i] and the test bus signal is from a test transistor, it is not necessary to program the routing structure 132 for testing. Thus, the interface buffer can be tested without affecting the programmability of the routing resource.
[0043]
FIG. 12 is a schematic diagram of an integrated circuit 250 having a JTAG circuit according to another aspect of the present invention. As is known in the art, JTAG registers are used to test inputs / outputs at terminals or pads of integrated circuits. However, as shown in FIG. 12, JTAG blocks 252 and 254 are used at the I / O of integrated circuit 250 (on the periphery of IC 250 in FIG. 12) and at the interface between dedicated logic 14 and programmable logic 12. Is possible. In FIG. 12, a demultiplexer 256 and a multiplexer 258 direct a test signal for JTAG test to either around the entire chip or around dedicated logic.
[0044]
FIG. 13 shows a configuration for a JTAG register that conforms to the IEEE standard and is suitable for JTAG block 252 or 254. Each JTAG block is associated with a node 255, which can be either an I / O pad for that chip or a terminal at the interface 16 between the programmable logic 12 and the dedicated logic 14. . Since there are input / output buffers at the interface between programmable logic 12 and dedicated logic 14, these input / output buffers are tested with input / output buffers associated with pads in the periphery of the circuit. It is possible. Thus, a number of JTAG blocks 252 are arranged around the periphery of the circuit at the I / O pad in a conventional manner. A second set of JTAG registers 254 is associated with the buffer along interface 16.
[0045]
As shown in FIG. 12, the demultiplexer 256 that receives the test signal has two output terminals. One of the output terminals is coupled to the first of the JTAG registers 252 around the periphery, while the second output terminal is coupled to the first of the JTAG registers 254 at the interface 16. ing. The select input terminal determines which JTAG register 252 or 254 receives the test signal. Although demultiplexer 256 is shown as being remote from integrated circuit 10 for convenience of explanation, it should be understood that demultiplexer 256 is typically part of integrated circuit 250.
[0046]
Multiplexer 258 has one input terminal coupled to the last JTAG register 254 along interface 16 and another input terminal coupled to the last JTAG register 252 on the periphery of programmable logic 12. have. The output terminal of multiplexer 258 is coupled to the first JTAG register 252 along the periphery of dedicated logic 14. The select input terminal of multiplexer 258 is coupled to the select input terminal of demultiplexer 256. The last JTAG block 253 is coupled to the output terminal for the output test signal OUT.
[0047]
To test I / O on the periphery of chip 250, the JTAG circuit receives a test signal via demultiplexer 256. The demultiplexer 256 supplies a test signal to the JTAG register 252 along the periphery. JTAG block 252 passes the signal from one JTAG block 252 to the next JTAG block 252 in a conventional manner until multiplexer 258 receives the test signal. Multiplexer 258 is controlled to pass test signals across interface 16. Therefore, the test signal continues to pass from one JTAG block 252 to the next until the JTAG block 253 outputs a test signal.
[0048]
On the other hand, in the case of a JTAG test around dedicated logic 254, demultiplexer 256 provides a test signal along interface 16 to JTAG block 254. JTAG block 254 passes test signals from one JTAG block 254 to the next until multiplexer 258 receives the test signal, as is conventional. In this case, multiplexer 258 passes the test signal from the last JTAG block 254 to the JTAG block 252 along the periphery of dedicated logic 14. Until the JTAG register 253 receives and outputs a test signal, the test signal passes from one JTAG block 254 to the next.
[0049]
It is also possible to use another routing circuit in place of the demultiplexer 256 and multiplexer 258 to provide another route for the JTAG test signal. For example, the test signal can be routed through the JTAG block 254 at the interface 16 and then around the periphery of the programmable logic 12 or around the entire chip 250.
[0050]
FIG. 14A illustrates another embodiment using a test scan along the boundary between dedicated logic 14 and programmable logic 12. In the embodiment of FIG. 14A, a series of scan cells 261-265 are at the boundary between dedicated logic 14 and programmable logic 12. The scan cells 261 and 262 receive signals from the buffer 100 at the interface 16. The signal can pass through logic 280 in the programmable logic 12 but is synchronized with the clock signal PCLK used predominantly in the programmable logic 12. Flip-flops 290 and 292 that receive signal PCLK via clock tree 294 illustrate the synchronization of the signal. During normal operating mode, scan cells 261 and 262 pass signals from buffer 100 to logic 260 in dedicated logic 14. The operation of these scan cells in the test mode will be described below with reference to FIG.
[0051]
The clock signal PCLK from the programmable logic 12 passes through the buffer 100 to the dedicated logic 14 and the clock tree 272 distributes the clock signal PCLK through the dedicated logic 14 for signals that require synchronization with the signal PCLK. Let One such signal is from flip-flop 271. The scan cell 263 receives the signal and passes the signal to the buffer 110 in the interface 16 during normal operation. From there, the signal enters logic 280 in programmable logic 12.
[0052]
Dedicated logic 14 predominantly uses clock signal DCLK distributed through clock tree 276. As illustrated, logic 273 in dedicated logic 14 can generate a signal that flip-flop 274 synchronizes with signal DCLK. During normal operation, scan cell 265 passes the signal from flip-flop 274 to buffer 110 in interface 16 and buffer 110 passes the signal to logic 286 in programmable logic 12.
[0053]
The clock signal DCLK can also be passed through the buffer 110 to the programmable logic 12 for signals that require synchronization with the signal PCLK. In FIG. 14A, the flip-flop 296 generates a signal synchronized with the signal PCLK passing through the logic 284 and the buffer 100 to the scan cell 264.
[0054]
FIG. 14B shows an exemplary embodiment of the scan cell 261. The scan cell 261 includes an input multiplexer 266, flip-flops 267 and 268, and an output multiplexer 269. During the test period, initially, the input multiplexer 266 selects the input signal PI having a value that depends on the logic 280. The flip-flop 267 registers the output signal from the multiplexer 266 in response to the scan clock signal SCLK and outputs the value to the scan output signal SO. Flip-flop 268 registers the value of signal SO in response to clock signal UCLK and outputs the value to multiplexer 269. The multiplexer selects the signal from flip-flop 268 during the test. In the case of testing, all of the input signals to the IC are known, so the appropriate values for the signal PI are known. The value of signal PI is initially recorded in flip-flops 267 and 268.
[0055]
Since the scan cells 261 to 267 are connected to each other, the scan output signal SO from one scan cell is the scan input signal SI for the next scan cell. To read the scan value in flip-flop 267, the scan clock signal is toggled, so the value from register 267 in one scan cell is recorded in register 267 in the next cell. The clock signal UCLK is not toggled during this time period, so the outputs from flip-flop 268 and multiplexer 269 remain constant. The output from the last of the scan cells can be connected to the I / O pad so that the binary value from the scan cell can be examined one by one at the frequency of the scan clock.
[0056]
During normal operation, output multiplexer 269 receives input signal PI and selects it as an output signal. Accordingly, the input signal PI passes through the scan cell 261 with a very slight delay.
[0057]
FIG. 15A shows a schematic diagram of programmable logic 12 and dedicated logic 14 in integrated circuit 10 and power routing structure 300. As can be seen from FIG. 15A, the routing structures for programmable logic 12 and dedicated logic 14 do not necessarily have the same width or pitch. In particular, the I / O buffers and circuits for programmable logic 12 may be different from the I / O buffers and circuits for dedicated logic 14. A power bus 302 at the interface integrally couples the power routing structure.
[0058]
FIG. 15B shows a more detailed view of the power bus 302. As can be seen from FIG. 15B, there are multiple conductors on the programmable logic 12 side, and a different number of conductors on the dedicated device 14 side. As an example, the conductors 304, 305, 306, 307 on the programmable logic 12 are ground, 3V, second ground, 5V, respectively. The conductors 310, 311, 312, 313, 314, and 315 on the dedicated logic 14 are ground, 5V, second ground, 3V, third ground, and second 3V, respectively. The power bus 302 couples the programmable logic 12 conductors with the appropriate logic 14 conductors. Thus, for example, the power bus couples conductor 304 to both conductors 312 and 314, conductor 305 couples to conductor 311, conductor 306 couples to conductors 313 and 315, and conductor 307 is Coupled to conductor 310. Thus, a single set of input / output terminals can be used to power both programmable logic 12 and dedicated logic 14.
[0059]
In an exemplary embodiment of the invention, dedicated logic 14 has a PCI interface and associated circuit blocks, and programmable logic 12 has an FPGA. One particular example of the exemplary embodiment is QL5064, available directly from Quick Logic, Inc. The QL5064 preliminary data sheet and QL5064 User's Manual, revision 0.98, available from QuickLogic at the time of filing of this patent application, describes QL5064 and is hereby incorporated by reference in its entirety. In this embodiment, programmable logic 12 provides a flexible backend interface that the user can program to the user's circuitry as needed. Thus, the user is not limited to using a fixed interface, such as a power PC interface, which is not necessarily optimal for the user's device. However, the dedicated circuit realizes a general but complicated function of forming a PCI interface, and frees the burden of forming a PCI interface from the user.
[0060]
FIG. 16 is a block diagram of a system including an integrated circuit 410 according to an exemplary embodiment of the present invention. In this exemplary embodiment, the dedicated logic is PCI core 414 and the programmable logic is FPGA. The system of FIG. 16 is a device attached to the PCI bus 35 of the host computer. The PCI core 414 of the IC 410 is coupled to the PCI bus 350 and the FPGA 412 is coupled to the user circuit 420. In an exemplary application, the IC 410 and user circuit 420 are mounted on a printed circuit board that is plugged into a slot in the host computer for electrical connection with the host computer's PCI bus 350. The PCI core 414 also acts as a PCI host controller. The user circuit 420 can achieve the desired function, eg, video, sound, communication or processing, and the FPGA 412 provides an adhesive-free interface to most 8-bit to 64-bit microprocessors. Is possible.
[0061]
The PCI core 414 has a PCI interface buffer and logic 352 connected to the PCI bus 350. More particularly, the buffer and logic 352 couples to the I / O pins of the IC 410 for receiving and transmitting signals defined by the PCI standard. In order to implement the PCI protocol, the PCI core 414 further includes a target controller 354 and a master controller 358. The interrupt controller 404 controls the interrupt signal on the PCI bus 350, and the communication block 406 realizes PCI communication that does not require a buffer. In particular, the communication block 406 is a mailbox register for transferring a maximum of 64 bits from a single data, and an I for communication of a PCI device.₂A circuit for realizing the O standard is included. A configuration block 402 using configuration data from the PROM 18 determines the configuration parameters of the PCI core 414.
[0062]
Five DMA controllers 360 transfer data from devices on main memory or PCI bus 350 to FIFO buffers 362, 363, 364 and from FIFO buffers 366, 367, 368 to devices on main memory or PCI bus 350 Control direct memory access operations. In the exemplary embodiment, each buffer 362-364 and 366-368 is at least 72 bits wide and includes 64 bits for data and 8 bits for byte enable. FIFO buffer 362 is a “target write buffer” or post-fetch buffer and is approximately 32 quad words deep. FIFO buffers 363 and 364 are master receive buffers and are approximately 64 quad words deep to support sustained burst transfers. The FIFO buffer 366 is a “target read buffer” or prefetch buffer and is approximately 16 quad words deep. FIFO buffers 367 and 368 are master transmit buffers and are approximately 64 quadwords deep to support sustained burst transfers.
[0063]
Data from the FIFO buffers 362, 363, 364 flows into the FPGA 412 via the one-way bus 370 and the two-way bus 390. Data from the FPGA 412 flows into the FIFO buffers 366, 367, 368 via the one-way bus 370 and the two-way bus 390. A lane steering circuit 374 is located between the FIFO buffers 362-364 and the bus 370. The lane steering circuit 374 has a barrel shifter that allows the received 64-bit data to be aligned with any byte. Similarly, a lane steering circuit 384 and a data configuration unit 382 are between the bus 380 and the FIFO buffers 366-368. Lane maneuver circuit 384 can realign the 64-bit data from FPGA 412, and data composition unit 382 uses the bytes from the two consecutive data values from FPGA 412 to provide 64-bit aligned data. Can be configured. Bi-directional bus 390 has a control interface 395 that selects data transfer from either FIFO buffers 362-364 or from buffers and logic 352.
[0064]
The buffer and interface 352 is a bus clock signal PCI for synchronous communication via the PCI bus 350. Receive CLK (typically 66 MHz frequency). PCI core 414 provides clock signal PCI for synchronous data transfer. Clock signal PCI using CLK and via interface 46 to FPGA 412 Pass CLK.
[0065]
The FPGA 412 receives another user clock signal USER. It also has a CLK, which is for data transfer to the user circuit 420, but typically the clock signal PCI It is not synchronized with CLK. FIFO buffers 362 through 364 and 366 through 368 enable data transfer across the clock domain in IC 410. In the exemplary embodiment, the clock signal USER CLK can have a frequency of up to 100 MHz. However, PCI devices often use a clock signal that is lower than the clock frequency for the PCI bus. Clock signal USER The frequency of CLK is the clock signal PCI When the frequency is lower than the frequency of CLK, the IC 410 has a plurality of 64-bit buses that run between the PCI core 414 and the FPGA 412, so that the IC 410 transfers data between the PCI core 412 and the FPGA 414. It is possible to use full PCI data bandwidth. In particular, in the case of three buses as shown in FIG. 10, the clock signal USER CLK can have a frequency as low as 22 MHz and can use the entire data bandwidth of the 66 MHz PCI bus 350. Further, incorporating the PCI core 414 and FPGA 412 on the same IC 410 is one for each data line that would be required if the PCI core 414 and FPGA 414 were separate IC devices. It is possible to have a large number of data lines without having I / O pins.
[0066]
The design of an integrated circuit, such as IC 410 of FIG. 16, generally requires simulation to determine the delay and timing of circuit components. In particular, the synchronization circuit requires that the circuit between the clocked register or latch be fast enough to complete the required logic operation within one clock cycle. Circuits such as IC 410 present a challenge to currently available circuit simulation software. This is because the wiring and actual logic implemented in the FPGA 412 is unknown until the user programs the FPGA 412. This makes it difficult to simulate the dedicated logic 412. This is because dedicated logic 412 receives and sends signals from FPGA 412.
[0067]
One simulation method simply uses the driver strength from the FPGA 412 as a parameter to the dedicated logic 412 simulation. However, when this is done, current simulation software ignores the conductive interconnect length between the driver at interface 16 and the first logic element in dedicated logic 12. As IC manufacturing technology achieves smaller dimensions, the effect of interconnect length becomes critical to the actual simulation of dedicated logic 12. In particular, for interconnects of 0.35 microns or less, the interconnect is a significant delay.
[0068]
In accordance with one aspect of the present invention, a simple model for FPGA 412 allows current simulation software such as a synopsis design compiler to properly consider FPGA 412 when simulating PCI core 16. FIG. 17 illustrates one embodiment of a model 422 for programmable logic for use with dedicated logic 12. Programmable logic model 422 has an I / O (input) pad 431 coupled to buffer 110 and an I / O pad (output) 100 coupled to buffer 100. Buffers 100 and 110 are accurately modeled according to the actual drive strength to be used. In the simulation, the pad has a pin capacity and a slew versus capacity table in its model. This simulation can ignore the actual circuit used in the programmable logic and the read length between the buffer and the pad, which is unpredictable before programming. However, conventional software accurately considers the interconnect length between buffers 100 and 110 and dedicated logic 12.
[0069]
Using only two pads simplifies the model for programmable logic, but additional pads can be added and connected to selected buffers as desired. For example, a pad for an input clock signal or a pad for a PROM buffer.
[0070]
Although the invention has been described in connection with certain specific embodiments for illustrative purposes, the invention is not limited thereto. The representation of the various configurations in the various drawings is exemplary. Aspects of the present invention should not be limited to amorphous silicon antifuses and oxide-nitride-oxide antifuses, but extend to other antifuse structures. Further, it should be understood that the conductive routing resource can be composed of any suitable conductive material or combination of materials and need not be composed of metal. Accordingly, various modifications, applications and combinations of the various features of the described embodiments can be practiced without departing from the scope of the invention as defined in the claims.
[Brief description of the drawings]
FIG. 1 is a schematic diagram of an integrated circuit according to one embodiment of the present invention having programmable logic, dedicated devices, and an interface therebetween.
FIG. 2 shows how to form a large schematic diagram of one embodiment of a portion of an interface and programmable logic using antifuses, FIG. 2A, 2B1, 2B2, 2B3, 2C, 2D, 2E , 2F1, 2F2, 2F3, 2G, 2H, 2I, 2J1, 2J2, 2J3, 2K, 2L, 2M, 2N1, 2N2, 2N3, 2O, 2P, 2Q, 2R1, 2R2, 2R3, 2S, 2T FIG.
2A is a partial schematic diagram constituting a part of the schematic diagram shown in FIG. 2. FIG.
2B1 is a partial schematic diagram constituting a part of the schematic diagram shown in FIG. 2. FIG.
2B2 is a partial schematic diagram constituting a part of the schematic diagram shown in FIG. 2. FIG.
2B3 is a partial schematic diagram that forms part of the schematic diagram shown in FIG. 2. FIG.
FIG. 2C is a partial schematic diagram that forms part of the schematic diagram shown in FIG. 2;
FIG. 2D is a partial schematic diagram that forms part of the schematic diagram shown in FIG. 2;
2E is a partial schematic diagram that forms part of the schematic diagram shown in FIG. 2. FIG.
FIG. 2F1 is a partial schematic diagram constituting a part of the schematic diagram shown in FIG. 2;
FIG. 2F2 is a partial schematic diagram constituting a part of the schematic diagram shown in FIG.
FIG. 2F3 is a partial schematic diagram constituting a part of the schematic diagram shown in FIG.
FIG. 2G is a partial schematic diagram constituting a part of the schematic diagram shown in FIG.
FIG. 2H is a partial schematic diagram that forms part of the schematic diagram shown in FIG. 2;
FIG. 2I is a partial schematic diagram that forms part of the schematic diagram shown in FIG. 2;
2J1 is a partial schematic diagram constituting a part of the schematic diagram shown in FIG. 2. FIG.
FIG. 2J2 is a partial schematic diagram constituting a part of the schematic diagram shown in FIG.
FIG. 2J3 is a partial schematic diagram constituting a part of the schematic diagram shown in FIG.
FIG. 2K is a partial schematic diagram constituting a part of the schematic diagram shown in FIG.
FIG. 2L is a partial schematic diagram that forms part of the schematic diagram shown in FIG. 2;
FIG. 2M is a partial schematic diagram that forms part of the schematic diagram shown in FIG. 2;
FIG. 2N1 is a partial schematic diagram constituting a part of the schematic diagram shown in FIG. 2;
2N2 is a partial schematic diagram that forms part of the schematic diagram shown in FIG. 2;
FIG. 2N3 is a partial schematic diagram that forms part of the schematic diagram shown in FIG.
FIG. 2O is a partial schematic diagram that forms part of the schematic diagram shown in FIG. 2;
FIG. 2P is a partial schematic diagram that forms part of the schematic diagram shown in FIG. 2;
FIG. 2Q is a partial schematic diagram constituting a part of the schematic diagram shown in FIG. 2;
FIG. 2R1 is a partial schematic diagram constituting a part of the schematic diagram shown in FIG.
FIG. 2R2 is a partial schematic diagram constituting a part of the schematic diagram shown in FIG.
FIG. 2R3 is a partial schematic diagram constituting a part of the schematic diagram shown in FIG.
FIG. 2S is a partial schematic diagram constituting a part of the schematic diagram shown in FIG. 2;
FIG. 2T is a partial schematic diagram that forms part of the schematic diagram shown in FIG. 2;
FIG. 3 is a schematic diagram of an integrated circuit according to another embodiment of the present invention.
4 is a simplified schematic diagram of a field programmable gate array (FPGA) having a portion that can be used as a platform for programmable logic in the embedded circuit shown in FIG. 1. FIG.
FIG. 5 is a schematic diagram illustrating an interface between a dedicated device and a plurality of macrocells in programmable logic.
FIG. 6 is a schematic diagram illustrating a clock interface between programmable logic and a dedicated device.
FIG. 7 is a schematic diagram showing two interface buffers and a test circuit.
FIG. 8 is a schematic diagram illustrating an interface buffer and test circuit between a programmable logic and a dedicated device and an interface buffer and test circuit between the dedicated device and the programmable logic.
FIG. 9 is a schematic diagram showing an interface buffer and a test circuit between a PROM and a dedicated device.
FIG. 10 is a schematic diagram of a weak detection circuit coupled to a test transistor and within the test circuit.
FIG. 11 is a schematic diagram illustrating interconnection of test configurations associated with one cell of an interface buffer.
FIG. 12 is a schematic diagram of a JTAG circuit according to one embodiment of the present invention.
FIG. 13 is a schematic diagram showing a conventional configuration (configuration specific) of a JTAG register that can be used in the present invention and is based on the IEEE standard.
14A is a schematic diagram illustrating the use of test scan cells at the boundary between dedicated logic and programmable logic. FIG.
FIG. 14B is a schematic diagram illustrating the use of a test scan cell at the boundary between dedicated logic and programmable logic.
FIG. 15A is a schematic diagram illustrating a power routing arrangement according to one embodiment of the present invention.
FIG. 15B is a schematic diagram illustrating a power routing arrangement according to one embodiment of the present invention.
FIG. 16 is a schematic block diagram showing an embodiment of the present invention in which a dedicated device implements an interface to a PCI bus.

Claims (13)

In integrated circuits,
Programmable logic,
Dedicated device,
An interface disposed between the dedicated device and the programmable logic and having an array of programmable antifuses ;
A first clock circuit in the programmable logic;
A second clock circuit in the dedicated device;
Have
A plurality of pads are provided for receiving a clock signal, the pads are coupled to the first clock circuit by a plurality of routing resources, and the programmable logic is at a frequency independent of the dedicated device. An integrated circuit, wherein at least one of the plurality of pads is coupled to the first clock circuit and the second clock circuit so as to be operable . 2. The integrated circuit of claim 1, wherein the interface includes a plurality of interface buffers, the interface buffers being coupled to the programmable antifuse array. The integrated device of claim 1, further comprising a configurable non-volatile memory coupled to the dedicated device for storing data for configuring or setting parameters for the dedicated device. Circuit . The integrated circuit of claim 1, wherein the programmable logic is a field programmable gate array. 2. The device of claim 1, further comprising a second dedicated device, wherein the interface is disposed between the second dedicated device and the programmable logic, the dedicated device and the second dedicated device. An integrated circuit that can operate independently. The integrated circuit of claim 1 , wherein the dedicated device comprises an application specific integrated circuit (ASIC) . 2. The integrated circuit of claim 1 , wherein the integrated circuit has four sides, the plurality of pads having a first number of pads and a second number of pads, the first number of pads and The integrated circuit wherein the second number of pads is on opposite sides of the integrated circuit. 2. The integrated circuit side of claim 1 , wherein the first number of pads is on one side of the integrated circuit closest to the programmable logic and the second number of pads is closest to the dedicated device. An integrated circuit on the department. The integrated circuit of claim 1 , wherein the at least one of the plurality of pads coupled to the second clock is located on the second side. The interface of claim 1 , further comprising:
A plurality of first conductors from the programmable logic to the dedicated device;
A plurality of second conductors from the dedicated device to the programmable logic;
A buffer coupled to the first conductor and the second conductor;
A test circuit coupled to each buffer,
A PMOS test transistor comprising a first terminal coupled to a voltage source, a second terminal coupled to a first output terminal, and a gate terminal coupled to the output terminal of the buffer;
An NMOS test transistor comprising a first terminal coupled to a ground source, a second terminal, and a gate terminal coupled to the output terminal of the buffer;
Having a test circuit,
A weak detection circuit coupled to the test circuit,
A first inverter including a first PMOS transistor and a first NMOS transistor, the first inverter having an input terminal and an output terminal, the input terminal being coupled to a voltage supply source; A first inverter having an output terminal coupled to the second terminal of the PMOS test transistor, the PMOS test transistor being larger than the first NMOS transistor in the first inverter;
A second inverter including a second PMOS transistor and a second NMOS transistor, the second inverter having an input terminal and an output terminal, the input terminal being coupled to a ground source; A second inverter, wherein the output terminal is coupled to the second terminal of the NMOS test transistor, the NMOS test transistor being larger than the first PMOS transistor in the second inverter;
Weak detection circuit, having
An integrated circuit . 11. The test circuit according to claim 10, wherein a plurality of test circuits are coupled to the weak detection circuit, the output terminal of the first inverter is coupled to each second terminal of the PMOS test transistor, and the second inverter. An output circuit coupled to each second terminal of the NMOS test transistor. 11. The device of claim 10, further comprising a formable non-volatile memory, the interface further comprising:
A plurality of third conductors from the formable non-volatile memory to the dedicated device;
The has the buffer is the first conductor, the second conductor is coupled to the third conductor integrated circuit. The integrated circuit of claim 1 , wherein the integrated circuit has a first side on one side of the interface and a second side on the opposite side of the interface;
A first set of peripheral input / output terminals around the periphery of the first side;
A second set of peripheral input / output terminals around the periphery of the second side;
A set of interface input / output terminals between the programmable logic and the dedicated device;
A first set of JTAG registers coupled to the first set of peripheral input / output terminals;
A second set of JTAG registers coupled to the second set of peripheral input / output terminals;
A third set of JTAG registers coupled to the interface input / output terminals;
An input terminal for receiving a test signal; a select terminal; a first output terminal coupled to the first set of JTAG registers; and a second output terminal coupled to the third set of JTAG registers. Demultiplexer,
A select terminal; a first input terminal coupled to the first set of JTAG registers; a second input terminal coupled to the third set of JTAG registers; and a second input terminal coupled to the second set of JTAG registers. A multiplexer having an output terminal,
An integrated circuit .

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