JP2003151272A - Storage device and its internal control method, system, and control method for storage means in system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage device to which efficient access can be performed and in which current consumption can be reduced. SOLUTION: A memory device 12 is constituted so that a shape of a logic address map can be changed. A CPU 11 controls a shape of the logic address map of the memory device 12 in accordance with an access mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION In recent years, semiconductor memory (dynamic RAM: Dynamic RA
M) is an increase in storage capacity required by customers (system side), faster access (higher operating frequency), I /
The current consumption tends to increase due to the expansion of the O bus width (increasing the width of the number of bits handling data in one access).
Along with this, the current consumption of the entire system equipment equipped with the memory device is also increasing, and customers are demanding reduction of the power consumption of the memory device.

Further, the increase of the above-mentioned current consumption may cause a rise in the chip temperature of the memory device. Generally, D
RAM cell data retention characteristics (≈ Refresh characteristics: TREF)
Is deteriorated at high temperature (holding time is shortened), and for this reason also, reduction of current consumption is required.

Therefore, semiconductor memories are required to have improved performance such as increased storage capacity, increased access speed, expanded I / O bus width, and reduced power consumption.

[0004]

2. Description of the Related Art A memory device has a memory cell array in which a plurality of memory cells are arranged in an array and a sense amplifier. Each memory cell is connected to a word line and a bit line, and the sense amplifier is connected to the bit line. The sense amplifier is paired with the bit line and amplifies and holds information (read data) of one cell.

The memory cell array is array-developed in the X-expansion direction in which the word line is expanded by the row address and in the Y-expansion direction in which the bit line and the sense amplifier are expanded by the column address. If the memory capacity is 1 Mbit, as an example, the logical address of the memory device may be 10 bits (2
¹⁰ = 1024 word lines: WL) X address (Row
Address) and a Y address (Column Address) of 10 bits (2 ¹⁰ = 1024 bit lines: BL (1024 sense amplifiers)) (Note: bit line definition = pair of complementary bit lines) ). At this time, if the wiring pitches of the word lines and the bit lines are the same, the logical memory array is imaged as a square.

The internal operation of the memory device is an SDRAM (Synchr) which is synchronous with the system clock CLK.
Onous DRAM) will be described as an example. SDRAM is
Active / synchronous with the system clock CLK to activate / deactivate the memory device as a control command.
It operates by a precharge command (falling and rising of a chip enable signal / CE (“/” indicates a bar) in an asynchronous memory device) and a read / write command for inputting / outputting data to / from the memory device.

When an active command is externally applied at the rising edge of the system clock CLK, the X address is fetched and decoded by the X decoder to select one word line and activate it. Each memory cell connected to the selected word line outputs data to each bit line, and each sense amplifier amplifies and holds the data (latches the data).

After that, when a read command is externally applied at the rising edge of the system clock CLK (with a delay of several CLKs from the active command), the Y address is fetched and decoded by the Y decoder to be held in one sense amplifier. Output data to the outside of the memory device.
Further, when a write command is externally applied, the Y address is fetched and decoded by the Y decoder to write the write data (input when the write command is applied) to the memory cell via one sense amplifier. After that, if necessary, read / write commands are issued at any time, and the desired Y
The memory cell is accessed according to the address and the outside.

After the read / write command is completed,
At the rising edge of the system clock CLK (with a few CLK delay from the read / write command), a precharge command is applied to reset (equalize) the activated word line, sense amplifier and bit line, and the memory array becomes Return to the initial state (preparing for the next active command).

It takes an internal time until the reset operation, and it is necessary to delay (wait) several CLK in order to apply the next active command from the precharge command. Similarly, it is necessary to delay (wait) several CLK from the active command to the read / write command.

Although the number of input / output bits of the memory array is 1 for simplicity of explanation, the number of input / output bits is n (nI / O) (ex. 4I / O). )
In this case, n sense amplifiers are simultaneously activated by the Y address. Each sense amplifier is connected to n I / O ports via n I / O buses.

The depth of the Y address is called the page length. The memory device responds to one active command to operate at least I / O bus width × page length sense amplifiers. For example, in the case of an SDRAM in which the Y address is set to 8 bits (YA <0: 7>), the page length is 256. This SDRAM is a 32-bit I / O
With the O bus width, at least 8,192 (= 256 × 32) sense amplifiers operate in response to the active command.

The SDRAM latches information of a plurality of memory cells connected to a word line selected by an active command in a plurality of sense amplifiers by a read command that is input at any time. Therefore, by activating one word line, the information of the memory cells for the page length can be appropriately read out. More specifically, for each read / write command that is input at any time, the Y decoder is used to select a sense amplifier at any time according to the Y address that is input at the same time as the command, so that information is read from the memory cell at an arbitrary Y address. That is, the X address can be randomly accessed while the X address is fixed. Such an operation is called a Y address priority operation. Information can be similarly written to the memory cell of an arbitrary Y address in response to a write command.

In this Y address priority operation, in addition to the advantage of random access, a plurality of data latched in each sense amplifier of the sense amplifier group which operates by one active command can be efficiently used. . In other words, one word line charge / discharge current and one (plural) sense amplifier (plural) bit line charge / discharge currents enable random access to the memory cells included in page 256.

Therefore, the current consumption required for one access is a value obtained by dividing the current consumption due to the charging / discharging of the word line and the charging / discharging of the bit line by the number of accesses to the page activated at the same time. Therefore, as the number of accesses in a page activated at the same time increases, the current consumption of the SDRAM per access decreases.

Further, in the Y address priority operation, the number of clocks required from applying an active command to a read / write command and the number of clocks required from applying a precharge command to the next active command are The share of the Therefore, the ratio of data occupying the input / output bus (data occupancy) is high, and the efficiency of the I / O bus in the system is good. For these, the higher the system clock frequency (higher frequency), the greater the latency that must be taken.
In M, the data occupation rate of the input / output bus can be increased.

[0017]

By the way, the SDRAM
Depending on the customer's system that uses, the bit length to be accessed is small (for example, continuous 4 bits or 8 bits). SDRAM by such a system
Access from a single active command to the precharge command, the number of reads / reads that is less than the page length.
The write operation cannot be performed and X is generated by the next active command.
The address is changed. For convenience, such an operation is performed as X.
This is called address priority operation. In this operation, the sense amplifier activated by one active command is not used efficiently.

For example, the Y address is changed (the X address is constant) and four memory cells are accessed. In this case, the charge / discharge current of one word line selected by the X address and the number of activated sense amplifiers (8192).
Current) (including the charge / discharge current of the bit line by the sense amplifier). The current consumption at this time is P (y). Therefore, the consumption current for accessing one memory cell is P (y) / 4.

On the other hand, when the X address is changed (Y address is arbitrary) to access four memory cells, an active command and a precharge command are required every time the X address is changed. Therefore, in the case of this access method, four times (4
× P (y)), and the current consumption for accessing one memory cell is P (y).

Therefore, in the case of a system or application which frequently uses the X address priority operation, a memory device having a shallow Y address (small number of pages) and a deep X address is effective.

However, the X address priority operation and the Y address priority operation may be mixed depending on the access method of the system using the memory device and the step of the application. In such a case, if a memory device having a shallow Y address is used, the access speed may be extremely slow depending on the access order, which hinders the speed improvement. On the other hand, using a memory device with a shallow X address hinders reduction of current consumption.

Further, when a large current consumption operation such as the X address priority operation is repeated, the temperature (junction temperature) of the chip of the memory device may be increased. In this case, the data retention characteristic deteriorates due to the temperature rise, and the refresh operation, which is a data retention operation, must be frequently performed. Then, the chip temperature is the sum of the temperature rise due to the access to the memory device and the self-heating due to the refresh operation of the memory device, which leads to the deterioration of the data retention characteristic and the further increase of the current consumption due to the frequent refresh operation. Further, when the data holding operation is performed asynchronously regardless of the control of the customer system side (self-refresh operation), the busy state in which the refresh operation does not respond to the access from the outside increases, and the system performance increases. Decrease (the data occupancy of the I / O bus decreases).

The present invention has been made to solve the above problems, and an object thereof is a storage device capable of efficient access and reduction of current consumption, a storage device internal control method, a system, and a storage device. It is to provide a control method of a storage means in the system.

[0024]

In order to achieve the above object, a map changing means for controlling the logical address of the memory array to change the logical address map shape of the memory array, as in the invention described in claim 1. Equipped with. As a result, the map shape is changed according to the access form information, and efficient access and reduction of current consumption are achieved.

The map changing means changes the shape of the logical address map each time the memory array is activated, as in the second aspect of the invention. According to a third aspect of the invention, based on the access form information for changing the shape of the logical address map of the memory array, the external address is input every cycle when the external address for the access in the first address direction is input. An address control means for replacing a part of the above with the first address or the second address.

According to a fourth aspect of the present invention, based on the access form information for changing the logical address map shape of the memory array, every cycle in which an external address for the access in the first address direction is input, An address invalidating unit for invalidating the external address or a part thereof is provided.

According to a fifth aspect of the invention, based on access form information for changing the shape of the logical address map of the memory array, every cycle in which an external address for access in the first address direction is input, A part of the external address is replaced with the first address or the second address.

According to a sixth aspect of the invention, based on the access form information for changing the shape of the logical address map of the memory array, every cycle in which an external address for the access in the first address direction is input, Invalidate the external address or a part thereof.

According to a seventh aspect of the present invention, the control means supplies the access mode information to the storage means at each time, and the storage means has an array of memory cells arranged at a first address and a second address. The logical address map form of the stored memory array is changed according to the access form information.

The control means supplies the access form information by any one of the address, the data and the code information by the control signal. As a result, the shape of the pin or the like is hardly changed, and the access form information is easily supplied.

According to a ninth aspect of the present invention, the control means is a memory array in which memory cells are arrayed at a first address and a second address of the storage means according to access mode information at each time. Control is performed so that the logical address map form is changed according to the access form information.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 3 is a schematic block diagram of the module 10. Module 10 is MCM (Multi Chip Module)
And includes a CPU 11 and a memory device 12, which are mounted on a substrate 13. The CPU 11 is connected to the memory device 12 and accesses the memory device 12.

The CPU 11 gives the access form information to the memory device 12 once or before the access is started.
The memory device 12 has a function of changing the logical address map shape according to the access form information. More specifically, the memory device 12 changes the logical address map shape in response to the access form information, X address, and Y address applied from the outside (CPU 11). Therefore,
The CPU 11 functions as a memory controller that controls the logical address map shape of the memory device 12.

The logical address map shape is determined by the depth of the X address and the Y address. The capacity of the memory cell array is constant. Therefore, the memory device 12
The depth of the X address and the depth of the Y address are changed complementarily.

The memory device 12 is provided with an external address terminal for inputting an address signal having the number of bits necessary for designating the maximum value of the X address and the maximum value of the Y address by a plurality of logical address map shapes. .

For example, a memory device having a capacity of 128 Mbits (32 I / O, 4-bank configuration) generally (standard) has 1 MB memory cells for each I / O in each bank. These memory cells are selected from a plurality (4) selected by a 12-bit row address (X address).
An array of (096) word lines and a plurality of (256) bit lines selected by an 8-bit column address (Y address) are arrayed. And SDRA
A memory device such as M is configured to take in an X address and a Y address by an address multiplexing method. Therefore, a general memory device has twelve address pins that capture a 12-bit X address, and captures a Y address from those address pins.

On the other hand, the memory device 12 of the present embodiment changes the depth of the X address and the depth of the Y address according to the logical address map shape. FIG. 4 shows a first memory array M1 formed in a logical address map shape (first shape) similar to that of the general memory device described above. FIG. 5 shows a second memory array M2 formed in a logical address map shape (second shape) in which the X address is deeper and the Y address is shallower than in FIG.

In the first memory array M1, the logical address map shape is an X address depth m (the number of logical word lines is 2 ^m ) and a Y address depth n (logical page length 2 ⁿ ).
In the drawing, 2 ^m is described as 2 ** m) In the second memory array M2, the logical address map shape is X address depth m.
+1 (number of logical word lines 2 ^{m + 1} ), Y address depth n-
1 (logical page length 2 ^n-1 ).

In the first memory array M1, one logical line of 2 ^m word lines is selectively activated, and the information of 2 ⁿ memory cells is amplified by the corresponding sense amplifier in the same number. , Retained.

In the second memory array M2, a logical one of the 2 ^{m + 1} word lines is selectively activated and 2
The information of ^n-1 memory cells is amplified and held by the corresponding sense amplifier in the same number.

Here, by a random access request along the Y direction based on an externally applied Y address,
Any memory cell information is accessed. In the case of the first memory array M1 (FIG. 4), the memory device 12 is the first (Y's in the figure) Y externally applied.
Four internal Y address signals (Y1 + 0, Y1 + 1, Y1 + 2, Y1 + 3) are sequentially generated based on the address Y1 according to the burst length. Then, the memory device 12 continuously serially accesses the memory cell selected by the internal row address signal to the outside.

Next, the memory device 12 similarly sequentially generates four internal Y address signals (Y2 + 0, Y2 + 1, Y2 + 2, Y2 + 3) based on the second Y address Y2, The memory cells selected by the internal row address signal are serially accessed externally.

Further, the memory device 12 similarly sequentially generates four internal Y address signals (Y3 + 0, Y3 + 1, Y3 + 2, Y3 + 3) based on the third Y address Y3, The memory cells selected by the internal Y address signal are serially accessed externally.

In the serial access described above, access to the respective start addresses Y1, Y2, Y3 having the same (common) X address is called a page operation by random access. Then, the access to the Y address added (+ 0, + 1, + 2, + 3) to the head addresses Y1, Y2, Y3 is called a burst operation (the burst length of the burst operation is 1, 2, , 8, etc., but here the burst length is 4).

When the X address changes, after the memory device 12 is once precharged (equalized),
The word line corresponding to the changed X address is selectively activated, and the memory cell connected to the bit line corresponding to the Y address is accessed. Here, page operation is performed three times (3
However, the page operation can be performed up to 2 ⁿ / 4 (2 ⁿ accesses).

On the other hand, in the case of the second memory array M2 (FIG. 5), the memory device 12 uses the burst length based on the first (Yeared in parentheses in the figure) Y address Y1 applied from the outside. 4 internal Y address signals (Y1
+ 0, Y1 + 1, Y1 + 2, Y1 + 3) are sequentially generated. Then, the memory device 12 continuously serially accesses the memory cell selected by the internal row address signal to the outside.

Next, when the X address changes, the memory device 12 once performs a precharge (equalize) operation,
Selectively activate the word line corresponding to the changed X address, and sequentially generate four internal Y address signals (Y2 + 0, Y2 + 1, Y2 + 2, Y2 + 3) based on the second Y address Y2. Then, the memory cells selected by the internal Y address signal are serially accessed to the outside continuously.

Further, when the X address changes, the memory device 12 once performs a precharge (equalize) operation,
Selectively activate the word line corresponding to the changed X address, and sequentially generate four internal Y address signals (Y3 + 0, Y3 + 1, Y3 + 2, Y3 + 3) based on the third Y address Y3. Then, the memory cells selected by the internal row address signal are continuously serially accessed from the outside. Here, the page operation is completed once (4 accesses), but the page operation can be performed up to 2 ^n-1 / 4 (2 ^n-1 accesses).

Consider the occupation ratio of the I / O buses in the first memory array M1 and the second memory array M2.
In the first memory array M1, the number of continuous accesses to one X address is as large as 2 ⁿ times, and the occupation rate of the I / O bus can be increased. On the other hand, in the second memory array M2, the number of continuous accesses to one X address is 2 ^n-1 times, which is half that in the first memory array M1, and the I / O bus occupancy rate is high. First memory array M
May be limited to less than 1.

Next, consider the current consumption in the first memory array M1 and the second memory array M2. The current consumption of each memory array M1, M2 corresponds to the charge / discharge current due to the activation of the word line and the activation of the sense amplifier.

Let P be the consumption current of the activation of the word line and the activation of the sense amplifier when the first memory array M1 is precharged once. At this time, the second memory array M2 is set to 1
When precharged twice, it is P / 2. Consider the current consumption when the first memory array M1 is operated with X address priority. Burst length 4, page operation 1 time (4 accesses), while accessing while changing X address, 1
The average of the current consumption of the activity of the word line and the activity of the sense amplifier per access is P / 4 (= P / 4). When the second memory array M2 is operated in the same manner, the average of the consumption currents of the activation of the word line and the activation of the sense amplifier per access is P / 8 (= (P / 2) ÷ 4). As described above, the second memory array M2 is more advantageous in terms of current consumption in the X address priority operation in which the page is not fully utilized.

Therefore, when the memory device is accessed by the operation with priority in the Y address direction, it is better to use the logical address map of the first memory array M1 for the I / O.
In some cases, the bus occupancy rate can be used high. On the contrary, when the memory device is accessed by the operation that has priority in the X address direction, it is more efficient in current consumption to use the logical address map of the second memory array M2.

FIG. 1 shows a memory device (SDRAM) 1.
It is a block diagram for explaining the outline of No. 2. SDRA
M12 is a clock buffer 21 and a command decoder 2
2, an address buffer 23, an input / output buffer 24, a control signal latch 25, a mode register 26, an address generation circuit 27, a write / read (I / O) control circuit 28, and a DRAM core 29.

The clock buffer 21 receives the clock enable signal CKE and the external clock signal CLK from an external device and outputs the internal clock signal CLK1 generated based on them to each circuit.

The command decoder 22 receives an external command C from an external device in response to the internal clock signal CLK1 from the clock buffer 21, that is, the clock signal CLK.
Enter the OM. In the present embodiment, the external command COM is composed of a chip select signal / CS, a column address strobe signal / CAS, a write enable signal / WE and a row address strobe signal / RAS. Then, the command decoder 22 responds to the internal clock signal CLK1 at that time by the external command COM,
That is, various commands such as a write command, a read command, and a refresh command are decoded from the state (H level or L level) of each signal / CAS, / WE, / CS, / RAS. Then, the command decoder 22 uses the address buffer 23, the input / output buffer 24, the control signal latch 25, the various commands decoded from the external command COM as an internal command and an enable signal.
It outputs to the mode register 26 and the I / O control circuit 28.

The address buffer 23 has a buffer function and a latch function, and receives address signals A _{0 to} A A from an external device based on an internal command from the command decoder 22.
₁₂ and bank address signals BA ₀ and BA ₁ are input. The address buffer 23 receives the input address signals A _{0 to} A ₁₂
It also amplifies the bank address signals BA ₀ and BA ₁ , latches the address data based on them, and outputs them to the control signal latch 25, the mode register 26 and the address generation circuit 27.

A standard memory device having substantially the same memory capacity as this memory device 12 is 12
It operates with the bit address signals A _{0 to} A ₁₁ and the 2-bit bank addresses BA ₀ and BA ₁ . Therefore, the memory device 12 has many address pins for inputting the 1-bit address signal A ₁₂ to the standard memory device.

The input / output buffer 24 is activated based on the enable signal from the command decoder 22, and receives write data DQ _{0 to} DQ ₃₁ and mask control signal DQM from an external device. Output buffer 24, the write data DQ ₀ to DQ ₃₁ in response to the internal clock signal CLK1
Is output to the I / O control circuit 28. Further, the input / output buffer 24 responds to the internal clock signal CLK1 by the I / O.
The read data DQ _{0 to} DQ ₃₁ from the control circuit 28 are output to an external device. Further, the input / output buffer 24 responds to the mask control signal DQM, and the write data DQ _{0 to} DQ _31.
To mask.

The control signal latch 25 inputs the internal command from the command decoder 22 and the address data from the address buffer 23. Then, the control signal latch 25 outputs control signals for various processing operations such as write data write, read data read, refresh, and self refresh to the DRAM core 29 based on these internal commands and address data. To do.

The mode register 26 inputs an internal command (mode register set command) from the command decoder 22 and address data from the address buffer 23. Then, the mode register 26 determines the DRAM core 2 based on these internal commands and address data.
9 holds the mode of various processing operations to be carried out for 9. Then, the mode register 26 outputs a control signal based on the held mode information.

The mode information held by the mode register 26 includes access form information. The access form information is information indicating the logical address map shape of the DRAM core 29. The mode register 26 outputs an address configuration selection signal generated based on the access form information to the address generation circuit 27.

The address generation circuit 27 inputs address data based on the address signals A _{0 to} A ₁₂ from the address buffer 23. Then, the address generation circuit 27 generates the row address data and the column address data corresponding to the logical address map shape of the DRAM core 29 at that time based on the mode of the mode register 26 and the address configuration selection signal, and the DRAM core 29. Output to. The address generation circuit 27 has a function of automatically generating a column address incremented from an input address based on the burst length set in the mode register 26.

The I / O control circuit 28 controls input or output based on the internal command from the command decoder 22. The I / O control circuit 28 outputs the write data (32 bits) from the input / output buffer 24 to the DRAM core 29 and the read data (32 bits) from the DRAM core 29 to the input / output buffer 24.

The DRAM core 29 is composed of a plurality of (four in this embodiment) banks, and each bank has a control signal from the control signal latch 25, row address data and column address data from the address generation circuit 27. Respectively. That is, the DRA is stored in the address buffer 23.
Bank address signal BA corresponding to the number of banks of the M core
₀ , BA ₁ are input, and the control signal latch 25 and the address generation circuit 27 are provided for each bank.

The DRAM core 29 executes various processing operations such as write data write, read data read, refresh, and self refresh on the built-in memory cell array based on the control signal and address data. Therefore, the DRAM core 29 writes the write data DQ _{0 to} DQ ₃₁ input from the input / output buffer 24 into the memory cell at a predetermined address based on the control signal and the address data.

FIG. 2 is a principle diagram for explaining the function of changing the logical address map shape according to the access form information. The memory device 12 includes an address configuration selection circuit 30, a changeover switch 31, a row related circuit 32, a column related circuit 33, first and second decoders 34 and 35, and a memory cell array 36. For example, the address configuration selection circuit 30
Includes the command decoder 22 and the mode register 26 of FIG. The changeover switch 31, the row related circuit 32 and the column related circuit 33 are included in the address generating circuit 27 of FIG. 1, and the first and second decoders 34 and 35 and the memory cell array 36 are D.
It is included in the RAM core 29. The configuration may be changed appropriately. Further, the address configuration selection circuit 30 may be separately provided.

A plurality of control signals and a plurality of address signals are input to the address configuration selection circuit 30. The address configuration selection circuit 30 analyzes the command supplied from the outside at that time based on the plurality of control signals. Then, when the command at that time is a command for changing the logical address map shape, the address configuration selecting circuit 30 generates the address configuration selection signal ASS generated to change the logical address map shape based on the address signal at that time. Switch 31 and first and second decoders 34, 3
Output to 5.

An external input address and an address configuration selection signal ASS are input to the changeover switch 31. The changeover switch 31 responds to the address configuration selection signal ASS to output the external input address to the row related circuit 32 or the column related circuit 3.
Switch to supply to 3. The signal to be switched is the external address signal added to the external address signal applied to the standard memory device having the same memory capacity. That is, the memory device 12 of FIG.
In the case of, the external address signal A ₁₂ corresponds to it. The memory device 12 supplies the external address signal A ₁₂ to the row related circuit 32 or the column related circuit 33 in response to the access form information.

The row related circuit 32 outputs the column address generated based on the supplied address signal to the first decoder 34.
Supply to. The column related circuit 33 outputs the column address generated based on the supplied address signal to the second decoder 35.
Supply to.

The first decoder 34 receives the supplied address
Bit line that decodes the signal and corresponds to the address signal
(Or column line) to generate a column selection signal,
The column selection signal is supplied to the memory cell array 36.
The number of selectable bit lines depends on the selected logical address
Address signal A in this embodiment.
₀~ A₇2 depending on (Fig. 1)ⁿ(N = 8). Obey
Then, the second decoder 35ⁿOne of two bit lines
Is configured to generate a selection signal to select a book
It

The first decoder 34 includes a clamp means 34a. Clamping means 34a is provided to clamp the inputs of the circuit not required by the logical address map shape.

The logical address map shape shown in FIG.
2 if the memory array M1) is selectedⁿBit of book
One of the wires (2ⁿOne of a number of sense amplifiers
Address signal A is a selection signal for selecting₀~ A_n-1Based on
It is generated based on. On the other hand, the logical address map shown in FIG.
In case of selecting the shape (second memory array M2)
Two ^n-1Signal for selecting one of the two bit lines
(Actually 2ⁿ2 of 2 bit lines are addresses
Signal A₀~ A_n-2It is generated based on.

Therefore, when the second memory array M2 is selected, the operation of the circuit portion for inputting the address signal A _n-1 is stabilized (actually, a plurality of bit lines corresponding to the logical address map shape are used). The inputs are clamped by the clamp means 34a for simultaneous selection).

For example, a decoration with four bit lines connected
The 2-bit address signal A ₀, A₁By 4
Select one of the bit lines. Connected to the decoder
The number of wires selected with respect to the number of wires
U Therefore, the compression rate of the first decoder 34 at this time is 1 /
It is 4.

The clamp means outputs one address signal (for example, A ₁ ) at a predetermined level (decoder type is NAND).
It is clamped to H level when logic is used and L level when NOR logic is used. In this case, the decoder selects two of the four bit lines connected by the 1-bit address signal A ₀ . At this time, the compression rate of the decoder becomes 1/2.

That is, the clamp means changes the compression rate of the decoder. Therefore, the clamp means 34a of the present embodiment
Clamps a predetermined address to a level according to the configuration of the first decoder 34 in order to change the compression rate of the first decoder 34.

The second decoder 35 decodes the supplied address signal to generate a row selection signal for selecting a word line corresponding to the address signal, and supplies the row selection signal to the memory cell array 36. The number of selectable word lines depends on the selected logical address map shape.
In this embodiment, as shown in FIG. 5, address signals A _{0 to} A _0
12 (Fig. 1) gives a maximum of 2 ^{m + 1} (m = 12). Therefore, the first decoder 34 is configured to generate a selection signal for selecting ^one of the 2 ^{m + 1} word lines.

The second decoder 35 includes a clamp means 35a. Clamping means 35a are provided to clamp the inputs of the circuit not required by the logical address map shape.

The logical address map shape shown in FIG.
2 if the memory array M1) is selected^mBook work
The selection signal for selecting one of the address lines is the address signal A
₀~ A _mIt is generated based on. On the other hand, the logical address shown in FIG.
Select the dress map shape (second memory array M2)
2 if^{m + 1}Select one of the word lines
The selection signal is the address signal A₀~ A_{m + 1}Is generated based on
It

Therefore, when the first memory array M1 is selected, the operation of the circuit portion for inputting the address signal A _{m + 1} is stabilized (actually, a plurality of sub word lines are formed according to the logical address map shape). The inputs are clamped by the clamp means 35a for simultaneous selection).

The clamp means 35a includes the first decoder 34.
Similarly to the clamping means 34a of the second decoder 35, a predetermined address is set to change the compression rate of the second decoder 35.
Clamp to a level according to the configuration of 5.

The number of selected word lines is changed by changing the number of sub word lines driven at one time.
That is, in the memory cell array 36, the main word line driven by the selection signal generated by the decoder 35,
A sub-word line is provided which is connected to the main word line through a plurality of gates and which is driven secondarily by driving the main word line. For example, the sub word line is provided for each column block. When the main word line is driven, the sub word line is driven by the gate that responds to the driving. Therefore, the number of sub word lines to be driven is made to correspond to the access form information by taking the logic of the drive of the main word line and the access form information at the gate which drives the sub word lines. Thereby, the logical address map shape can be substantially changed according to the access form information.

FIG. 7 shows the structure of the memory cell array and the first
5 is an explanatory diagram of selection corresponding to the memory array M1 (see FIG. 4) of FIG. The memory cell array 36 includes cells 37 arrayed by 2 ^m word lines and 2 ⁿ bit lines.
And a sense amplifier 38 connected to each bit line. Of the plurality of word lines, the X decoder 35 (FIG. 2)
Address signal XA <0: m> (address signal A ₀ ~
One is activated based on the logic of A ₁₁ ). Further, 2 ⁿ sense amplifiers 38 corresponding to the selected word line are activated. 2 connected to the selected word line
Cell information is read from the ⁿ cells 37 to the corresponding sense amplifiers 38. Then, one of the plurality of sense amplifiers 38 based on the logic of the address signal YA <0: n> (address signals A _{0 to} A ₇ ) is connected to a data bus line (not shown) by the Y decoder 34 (FIG. 2). It In this way, the read or write operation is performed on the selected cell 37 via the sense amplifier 38 connected to the data bus line.

FIG. 8 shows the structure of the memory cell array and the second
6 is an explanatory diagram of selection corresponding to the memory array M2 (see FIG. 5) of FIG. The memory cell array 36 is composed of two divided column blocks, and each block has an address signal XA.
Either one is selected by _{m + 1} . Each block includes 2 ^m subword lines and 2 ^n-1 sense amplifiers 38. Therefore, the memory cell array 36 has two sub word lines selected by substantially the same X address, and these word lines correspond to one word line in FIG.

Of the plurality of sub word lines, the X decoder 3
5 address signal XA <0: m + 1> (address signal A ₀ ~
One is activated based on the logic of A ₁₂ ). Then, the 2 ^n-1 sense amplifiers 38 corresponding to the selected sub-word line are activated, and the cell information is read from the plurality of cells 37 connected to the sub-word line to the corresponding sense amplifier 38. Then, a plurality of sense amplifiers 38
Address signal YA at the Y decoder 34 (FIG. 2).
One based on the logic of <0: n-1> (address signals A _{0 to} A ₆ ) is connected to a data bus line (not shown). In this way, the read or write operation is performed on the selected cell 37 via the sense amplifier 38 connected to the data bus line.

Therefore, the memory cell array 36 shown in FIG.
Then, the cell information from the 2 ⁿ cells 37 connected to the word line activated by one X address XA is latched by the sense amplifier 38. Therefore, since access to the cell 37 selected by the same X address is performed only by designating the Y address, the access time is short and the current consumption is small.

On the other hand, in the memory cell array 36 corresponding to the logical address map shape shown in FIG. 8, the cell information from 2 ^n-1 cells 37 connected to one activated sub-word line is sent to the sense amplifier 38. Latched. The sub-word line activated at this time is 1/2 the length of the word line in FIG. Also, the sense amplifier 38 to be activated
Is 1/2 that of the case shown in FIG. Therefore, although the number of cells 37 that can be accessed by the same X address is 1/2, the current consumption is also 1/2.

In FIG. 8, the memory cell array 36
The two column blocks that make up X are selected by the expanded X address XA _{m + 1} . Therefore, X address X
The output destination of A _{m + 1} is switched from the row related circuit 32 to the column related circuit 33. That is, the memory device 12 replaces the X address XA _{m + 1} given from the outside from the direction of selecting the word line by the X address to the direction of selecting the bit line by the Y address. The X address XA _{m + 1} selects the sub word line in the column block and the sense amplifier 38.

As described above, this embodiment has the following effects. (1) The memory device 12 is configured so that the logical address map shape can be changed. The CPU 11 controls the logical address map shape of the memory device 12 according to the access form. As a result, efficient access can be performed.

(2) In the memory device 12, the number of sense amplifiers 38 activated by a part of the X address is changed based on the logical address map shape. As a result, current consumption can be reduced.

(2) In accordance with the logical address map shape,
Part of the address signal supplied from the outside is transferred from the X direction to Y
The direction is replaced or vice versa. As a result, the logical address map shape can be easily changed.

(3) The address configuration is set by the mode register setting command. As a result, it is not necessary to provide a dedicated terminal, and the increase in the shape of the memory device 12 can be suppressed.

The above embodiment may be modified into the following modes. In the above embodiment, the address configuration selection circuit 30 is provided to generate the address configuration selection signal ASS, and the changeover switch 31, the first and second decoders 34, 35 respond to the signal ASS to send the address signal from the X direction. Although the replacement is performed in the Y direction, as shown in FIG. 9, the changeover switch 31, the first and second decoders 34 and 35 accept the access form information supplied from the outside, and directly respond to the information to obtain the logical address. The map shape may be changed.

In the above embodiment, the X direction is the word line selection direction (row direction) and the Y direction is the bit line selection direction (column direction). However, the X direction and the column direction, and the Y direction may be the row direction. . In that case, the address signal supplied from the outside is replaced from the Y direction to the X direction.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to FIGS.
For convenience of explanation, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof is partially omitted.

FIG. 10 is a schematic block diagram of the memory device 40. The memory device 40 includes a command generation circuit 41, a mode register 42, and an address generation circuit 43. For example, the command generation circuit 41 includes the clock buffer 21 and the command decoder 22 shown in FIG. As shown in this figure, the circuit may be appropriately changed as long as it has a desired function (function of changing the logical address map shape).

The command generating circuit 41 is connected to the clock terminal and the command terminal, and the clock signal CL shown in FIG.
Input K and external command COM. In response to the clock signal CLK, the command generating circuit 41 responds to the external command COM, that is, each signal / CAS, / WE, at that time.
Various commands are decoded from the states of / CS and / RAS (see FIG. 1). The command generation circuit 41 outputs an ACT signal in the case of an active command and a READ / WRITE signal (hereinafter, RD in the case of a read / write command).
/ WR signal), and the mode register set command, the MRS signal is output.

[0099] The mode register 42 is connected to the address terminal, inputs the external address signal A ₀ ~A _{1 2.} The mode register 42 uses the MRS from the command generation circuit 41.
Based on the signal and the address signals A _{0 to} A ₁₂ , the mode information of various processing operations performed on the DRAM core 29 is held. The mode information includes access form information. That is, the mode register 42 is external (CPU 11 in FIG. 3).
From the incasarell access form information to the mode register 4
Hold at 2. Then, the mode register 42 outputs an address configuration select signal (hereinafter, simply select signal) ASS corresponding to the held access form information.

Address generation circuit 43 includes an X address generation circuit 44 and a Y address generation circuit 45. The X address generation circuit 44 includes an ACT signal, a select signal ASS,
Address signals A _{0 to} A ₁₂ are input. The X address generating circuit 44 responds to the ACT signal by sending the address signals A ₀ to
A ₁₂ is accepted as a row address and the row address is output to the DRAM core 29. At this time, the X address generation circuit 44 validates or invalidates a part of the address signals A _{0 to} A ₁₂ based on the select signal ASS.

The logical address map shape shown in FIG. 4 (first
In the case of the memory array M1), the word line is selected and activated by the address signals A _{0 to} A ₁₁ . On the other hand, the logical address map shape shown in FIG. 5 (second memory array M2)
In the case of, the word line (sub-word line) receives the address signal A _0.
~ A ₁₂ selects and activates.

Therefore, when the memory device 40 is set to operate as the first memory array M1, the X address generation circuit 44 invalidates the address signal A ₁₂ and sets the address signals A _{0 to} A ₁₁ to the row address. Output as. On the other hand, the X address generation circuit validates the address signal A ₁₂ and outputs the address signals A _{0 to} A ₁₂ as row addresses when the memory device 40 is set to operate as the second memory array M2.

An ACT signal, a select signal ASS, and address signals A _{0 to} A ₇ are input to the Y address generation circuit 45. The Y address generation circuit 45 receives the address signals A _{0 to} A ₇ as column addresses in response to the ACT signal, and outputs the column addresses to the DRAM core 29. At this time, the Y address generation circuit 45 validates or invalidates a part of the address signals A _{0 to} A ₇ based on the select signal ASS.

The logical address map shape shown in FIG. 4 (first
In the case of the memory array M1), the bit lines are selected and activated by the address signals A _{0 to} A ₇ . On the other hand, in the case of the logical address map shape (second memory array M2) shown in FIG. 5, the bit lines are selected and activated by the address signals A _{0 to} A ₆ .

Therefore, the Y address generation circuit 45 validates the address signal A ₇ and sets the address signals A _{0 to} A ₇ to the column address when the memory device 40 is set to operate as the first memory array M1. Output as. On the other hand, if the Y address generation circuit 45 that is configured such that the memory device 40 operates as a second memory array M2, invalidates the address signal A _7, and outputs an address signal A ₀ to A ₆ as the column address .

FIG. 11 is an operation waveform diagram of FIG. Me
The memory device 40 raises the clock signal CLK.
In response to, input and output signals to and from the outside. Memory device
40 indicates that the external command COM is a mode register set command.
Address signal BA at that time in case of command (MRS)
₀, BA₁, A ₀~ A₁₂Or a part of it
Received as information V, and various modes based on the information V
To set.

At time t1, the memory device 40 sets the logical address map shape in the first memory array M1 based on the register setting information V. Next, the memory device 40 invalidates a part (address signal A ₁₂ ) of the address signals A _{0 to} A ₁₂ received in response to the next active command (ACT), and based on the address signals A _{0 to} A _11. One word line selected from the 4096 word lines is activated. As a result, the cell information of the memory cells connected to the word line is read by the sense amplifier.

[0108] Next, the memory device 40 receives the address signal A ₀ to A ₇ in response to the read command (RD), is selected by the address signal A ₀ to A ₇ from the 256 sense amplifiers Sense amplifier (# 0 shown in FIG. 7
0 sense amplifier 38) is connected to the data bus line. As a result, the cell information of the memory cells corresponding to the address signals A _{0 to} A ₇ (Y address) received by the read command is output to the outside.

After that, the memory device 40 receives the read command RD and the Y addresses A _{0 to} A ₇ continuously or intermittently for each system clock CLK, and performs the page operation (# 80 → # 7F → # FF) by them. ) Is possible. The I / O data bus has a continuous Y address of 25
Data of up to 6 addresses can be read. Therefore, at this time, read data from 256 memory cells can be continuously read to the I / O data bus,
The occupancy of the I / O data bus by the read data is high.

At time t2, the memory device 40 sets the logical address map shape in the second memory array M2 according to the register setting information V received in response to the mode register set command (MRS). Next, the memory device 40 receives the address signals A _{0 to} A ₁₂ (A ₁₂ (FIG. 8) in response to the next active command (ACT).
Then, _one subword line selected from the 8192 subword lines is activated based on XA _{m + 1} ) = “L”). As a result, the cell information of the memory cells connected to the sub word line is read by the sense amplifier.

[0111] Next, the memory device 40 receives the address signal A ₀ to A ₇ in response to the read command (RD), as part of the address signal A ₀ to A ₇ (address signal A ₇₎ disable , 128 by address signals A _{0 to} A ₆
A sense amplifier selected from the sense amplifiers (the # 00 sense amplifier 38 at the bottom in FIG. 8) is connected to the data bus line. As a result, the cell information of the memory cells corresponding to the address signals A _{0 to} A ₆ (Y address) received by the read command is output to the outside.

After that, the memory device 40 receives the read command RD and the Y addresses A _{0 to} A ₇ , and performs a page operation (# 7F) by them. Next, the memory device 40 deactivates the word line (subword line) and the sense amplifier by the precharge command (PRE) and returns to the standby state. Next, the memory device 40 receives the address signal A ₀ in response to the active command (ACT) after the specified clock (4 clocks in FIG. 11).
~A ₁₂ (A ₁₂ (in FIG. _{8 XA m + 1) = "} H") to activate one sub-word line selected from among the 8192 sub word lines based on. As a result, the cell information of the memory cells connected to the sub word line is read by the sense amplifier.

[0113] Next, the memory device 40 receives the address signal A ₀ to A ₇ in response to the read command (RD), as part of the address signal A ₀ to A ₇ (address signal A ₇₎ disable , 128 by address signals A _{0 to} A ₆
A sense amplifier (# 00 sense amplifier in the middle stage shown in FIG. 8) selected from the individual sense amplifiers is connected to the data bus line. As a result, the cell information of the memory cells corresponding to the address signals A _{0 to} A ₆ (Y address) received by the read command is output to the outside.

At this time, the length of the activated sub-word line is shorter than that of the word line of the first memory array M1, and the number of activated sense amplifiers is also the first memory array M1.
Less than that. Therefore, the second memory array M2
Page address is limited to half, but Y address Y
If the access is within A <6: 0>, the active and precharge current consumption required for the same number of accesses is halved.

FIG. 12 is a block diagram showing an example of the address generation circuit 43. The address generation circuit 43 includes an X address generation circuit 44, a Y address generation circuit 45, and an inverter circuit 46.

The X address generating circuit 44 includes 12 first buffer latch circuits 44a corresponding to the address signals A _{0 to} A ₁₁ and a second buffer latch circuit 44b corresponding to the address signal A ₁₂ . Second buffer latch circuit 44
b includes a clamp means (not shown). Note that the circuit configuration may be appropriately changed by providing the clamp means and the column decoder 48, or connecting them as another circuit.

The Y address generating circuit 45 includes seven first buffer latch circuits 45 corresponding to the address signals A _{0 to} A _6.
comprising a a, a second buffer latch circuit 45b corresponding to the address signal A _7. The second buffer latch circuit 45b includes a clamp means (not shown). The circuit configuration may be appropriately changed by providing the clamp means in the row decoder 47 or connecting the row decoder 47 as another circuit.

The inverter circuit 46 logically inverts the input select signal ASS and outputs an inverted select signal to the second buffer latch circuit 44b of the X address generating circuit 44. The select signal ASS is input to the second buffer latch circuit 45b of the Y address generation circuit 45. Therefore, both the second buffer latch circuits 44b and 45b operate complementarily.

In the X address generation circuit 44, the first buffer latch circuit 44a latches the address signals A _{0 to} A ₁₁ and outputs the latch signal to the row decoder 47. The second buffer latch circuit 44b latches the address signal A _12, and outputs the clamped signal to the latch signal or a predetermined level in response to the inverted select signal.

In the Y address generating circuit 45, the first buffer latch circuit 45a latches the address signals A _{0 to} A ₆ and outputs the latch signal to the column decoder 48. The second buffer latch circuit 45b latches the address signal A _7, in response to the select signal ASS and outputs a signal of clamping the latch signal or a predetermined level.

As described above, this embodiment has the following effects. (1) The memory device 40 invalidates a part of the X address or the Y address according to the changed logical address map shape. As a result, since the external address input is constant regardless of the shape, it is possible to save the trouble of changing the supplied signal according to the map shape.

The above embodiment may be modified into the following modes. The X address generation circuit 44 may be configured to have a means for clamping an output signal so that a circuit (for example, a decoder) at a subsequent stage corresponding to the invalidated address signal A ₁₂ does not malfunction. In addition, the Y address generation circuit 45
However, it may be configured to have a means for clamping an output signal so that a circuit (for example, a decoder) at a subsequent stage corresponding to the invalidated address signal A ₇ does not malfunction.

(Third Embodiment) The third embodiment of the present invention will be described below with reference to FIGS. 13 and 14.
For convenience of explanation, the same components as those in the first and second embodiments will be designated by the same reference numerals and the description thereof will be partially omitted.

FIG. 13 is a schematic block diagram of memory device 50, and FIG. 14 is an operation waveform diagram thereof. The memory device 50 includes a command generation circuit 41, an address configuration register 51, and an address generation circuit 43.

The address configuration register 51 is connected to the address configuration setting terminal and inputs an address configuration setting signal. The address configuration register 51 also receives the ACT signal from the command generation circuit 41.

Address configuration register 51 determines whether or not the address configuration signal has been changed in response to the ACT signal. The address configuration signal is supplied from the outside (for example, the CPU 11 in FIG. 3) by the logic corresponding to the logical address map shape. That is, the address configuration register 51 is
Each time an active command is received based on the T signal, it is determined whether or not the logical address map shape is changed,
The address configuration setting is stored based on the determination result.
Then, the address configuration register 51 outputs the select signal ASS corresponding to the setting.

The memory device 50 as described above needs a terminal for applying the address configuration signal, but the logical address map shape can be changed without using the mode register set command. Therefore, the cycle (the number of clocks) for receiving the active command is smaller than that in the above embodiment, and the access speed can be improved as a whole.

The above embodiment may be modified into the following modes. The setting of the address configuration may be judged by the system clock signal CLK. That is, the address configuration register 51
Is connected to the clock terminal, and the system clock signal CL
Enter K. The address configuration register 51 uses the rising edge (or falling edge) of the system clock signal CLK.
In response to the rising edge and the falling edge), it is determined whether or not the logical address map shape is changed based on the address configuration signal, and the address configuration setting is stored based on the determination result. Then, the address configuration register 51 outputs the select signal ASS corresponding to the setting. With this configuration, the shape of the logical address map can be changed more easily than when applying the mode register set command. Further, compared with the above-described embodiment, the select signal ASS can be generated by the clock signal CLK earlier than the command generation circuit 41 accepts various commands. Therefore, without delaying the operation of the address generation circuit 43 that receives the X address signal,
Access delay can be prevented.

In the second and third embodiments, the X address generating circuit and the Y address generating circuit may be shared. That is, as shown in FIG.
Y shared address generation circuit 61, changeover switch 62,
It includes latch circuits 63 and 64, a column circuit 65, and a row circuit 66. Changeover switch 62 address signals A ₀ to A _{1 2}
Address configuration select signal ASS
In response to 2, the shared address generating circuit 61 is transferred to the column related circuit 65.
Alternatively, it is connected to the row circuit 66.

The column related circuit 65 is a circuit including an X decoder, and the row related circuit 66 is a circuit including a Y decoder. The latch circuit 6 is provided between the column circuit 65 and the changeover switch 62.
3 is inserted and connected, and the row related circuit 66 and the changeover switch 6
A latch circuit 64 is inserted and connected between the two.

The address configuration select signal ASS2 is the logic of the control signal for controlling the switching so as to supply the output signal of the shared address generation circuit 61 to the column system circuit 65 or the row system circuit 66 according to the operation, and the address configuration select signal. This is a signal including the logic of the signal ASS.

FIG. 16 is a block diagram showing an example of the shared address generation circuit 61. Shared address generation circuit 61
Are seven first buffer latch circuits 61a corresponding to the address signals A _{0 to} A ₆ and a second one corresponding to the address signal A ₇ .
Comprising buffer latch circuit 61b, 5 pieces of the third buffer latch circuits 61c corresponding to the address signal A ₈ to A _11, a fourth buffer latch circuit 61d corresponding to the address signal A _12.

The changeover switch 62 includes first to third switches 62a to 62c. The first switch 62a outputs the output signal of the first buffer latch circuit 61a to the row related circuit 66.
Alternatively, it is supplied to the column circuit 65. The second switch 62b is
The output signal of the second buffer latch circuit 61b is transferred to the row related circuit 6
6 is made invalid / valid or is supplied to the column related circuit 65. The third switch 62c determines whether to invalidate / validate the output signal of the fourth buffer latch circuit 61d with respect to the column related circuit 65.

Such a structure can reduce the area occupied by the address generation circuit, and is effective for downsizing the memory device. (Fourth Embodiment) A fourth embodiment of the present invention will be described below with reference to FIGS.

In this embodiment, the shape of the logical address map is changeable in the asynchronous memory.
Since the schematic configuration of the asynchronous memory is already known, the drawing and description thereof are omitted.

This memory device determines the address signal ADD as the X address (row address) at the fall of the chip enable signal (/ CE) or the row address strobe signal (/ RAS). Next, the memory device determines the address signal ADD as a Y address (column address) by a read or write control signal or the like, and accesses the cell designated by those addresses. The operation waveform at that time is shown in FIG.

The change of the logical address map shape is applied to the unused terminal at the fall of the chip enable signal / CE (or the row address strobe signal / RAS). For example, an I / O terminal, an expanded address terminal ADD2, and an address configuration setting terminal are used.

Further, the logical address map shape may be changed in a memory device of a completely asynchronous specification such as SRAM (Static RAM) or flash memory. The operation waveform at that time is shown in FIG.

In the asynchronous memory device, the address map may be controlled by the following illegal entry method (a control method from the outside which is not normally used in the access from the outside).

In the illegal entry method, as in the case of using the mode register set command in the synchronous method (MRS method), the address configuration select signal in the memory device is changed from the word line activation signal from the chip enable signal / CE. Will generate sooner. As a result, access delay can be prevented without delaying the operation of the X address generation circuit or the changeover switch (see FIG. 15) for changing its output.

The illegal entry method will be described in detail. FIG. 19 is a waveform diagram illustrating a mode setting cycle for address configuration. The memory device has a dedicated terminal for mode setting for address configuration, and by fetching the necessary information from the dedicated terminal to the information for determining each type of address configuration, it is possible to prevent external access delay and prevent malfunction. The safe operation of normal operation can be guaranteed.

That is, the memory device does not operate normally when the chip enable signal / CE1 is at the H level. During this period, the address code Code based on the address signal ADD is fetched in response to the program mode signal / PE (= address configuration setting terminal) input from the dedicated terminal. Specifically, the memory device activates the input of the address code at the falling edge of the program mode signal / PE, and latches the address code information at the rising edge of the signal / PE.

On the other hand, when the chip enable signal / CE1 is at the L level, the memory device enters the operation state corresponding to the external access and fetches the address signal ADD corresponding to the external access.

In the figure, t1 to t5 are external specification timing conditions. At the timing shown in the figure, the input circuit of the external dedicated terminal is activated at the fall of the program mode signal / PE to start the decoding operation for the address signal. Then, the decoding result is determined at the rising edge of the program mode signal / PE, and the input circuit is deactivated. By this operation, power consumption can be reduced.

In the mode setting cycle for the above address configuration, the logic of the program mode signal / PE may be inverted. Also, the address code may be input from a data terminal (called DQ or I / OPin).

Further, as will be described later, the mode may be determined after the program cycle by the code method is repeated several times. FIG. 20 is an explanatory diagram of commands. When using this command, the reference clock
(System clock CLK and chip enable signal / C
For E1), a memory device of a specification system that recognizes a command and performs an external access operation is targeted.

Therefore, in the memory device of the specification system which does not operate by the command with respect to the chip enable signal / CE1 as shown in FIGS. 17 and 18, the address is simply determined for each kind of address configuration based on FIG. It may be used as information for the setting and used as the number of times for setting the mode.

Commands (1) to (6), (8) to (1
0) is a command used in normal operation, and commands (7) and (11) are commands that have no meaning in normal operation. Command 7 is a write (WR) operation, but does not input data (masked) because the signals / LB and / UB are at the H level. Command (11) is
It is a read (RD) operation, but similarly signals / LB, / I
No data is output because it is masked by B.

As described above, by fetching a command (illegal command) not used for normal operation as information for determining each type of address configuration, it is possible to set information without providing a dedicated terminal.

FIG. 21 is a waveform diagram for explaining the mode setting cycle for address configuration. By continuously inputting a plurality of commands (11) shown in FIG. 20, information necessary for mode setting for address configuration is shown. Shows the case where is taken in as an address code.

The memory device takes in the address signal ADD as the address code Code in response to the command (11). This operation is repeated N times. N from the first time
When all the N address codes Code fetched corresponding to the command (11) up to the first match, the address code Code is validated and the mode setting for the address configuration is performed.

If the command (11) matches N-1 times, the mode for address configuration is set based on the address code Code fetched corresponding to the Nth command (11). Good. Further, the fetching of the address code Code is performed in an arbitrary cycle (for example, 1
It may be changed to the first time). Various other applications can be developed.

As for the address code for setting the mode, the number of address bits may be determined corresponding to the number of types of address configuration. In the case of N mode setting cycles as shown in FIG. 21, a counter circuit is used inside the device. When the upper bits of the counter circuit change for N number of mode setting cycle entries, the circuit configuration is such that the mode is determined.

FIG. 22 is an operation waveform diagram of an entry control circuit which is a mode setting circuit for configuring a program address. As shown in FIG. 22A, the first entry circuit outputs the H-level first address enable signal proaddz in the third cycle, and outputs the first entry signal proentz in the fourth cycle. Then, the first entry circuit uses the first address enable signal proa.
Reset ddz and the first entry signal proentz at the same time. As a result, the memory device sends the previously determined address configuration information to the 4th by the first entry signal proentz.
The information of the latest address configuration is changed according to the address code information fetched in the second cycle.

As shown in FIG. 22 (b), the first entry circuit causes the other commands (device activation active command and read / write command) during counting.
When is accepted, the count is reset. As a result, the first address enable signal proaddz and the enable signal proaddz are held at the L level.

That is, in the mode setting for determining each type of address configuration, if the same command for that purpose does not continue for the specified number of times, it is canceled. (The memory device maintains the previously determined address configuration information) FIG. 23 is an operation waveform diagram of the entry control circuit (second entry circuit) which is the mode setting circuit for the program address configuration corresponding to FIG. is there.

The second entry circuit outputs the H level address enable signal peaddz in response to the L level program mode signal / PE, and then responds to the H level program mode signal / PE in the H level enable signal.
Output peaddz. As a result, the memory device transmits the information of the previously determined address configuration to the second entry signal proe.
It is changed to the latest address configuration information according to the address code information imported by ntz.

FIG. 24 is an operation waveform diagram of the entry signal generating circuit. As shown in FIG. 24 (a), the signal generation circuit responds to the first entry signal proentz to generate the combined signal en.
Output tz. In addition, as shown in FIG. 24 (b), the signal generation circuit responds to the entry signal peentz to generate the combined signal en.
Output tz.

FIG. 25 is an operation waveform diagram of the mode setting address buffer for address configuration. The address buffer activates the input circuit in response to the H-level address enable signal peaddz and outputs the address signal az <0: 3>. The same operation is performed in response to the first address enable signal proaddz.

FIG. 26 is an operation waveform diagram of a mode setting address latch for address configuration. The address latch uses the address setting az <0: 3> output in response to the H level address enable signal peaddz and latches the code Code latched in response to the combined signal entz for setting the mode. Output as <0: 3>.
The same operation is performed in response to the first address enable signal proaddz.

The mode setting decoder for address configuration uses the mode setting address signal paz <for address configuration.
0: 3> is decoded and an address configuration select signal for several types of address maps is output.

FIG. 27 is an operation waveform diagram of the mode setting decoder. The decoder uses the mode setting address signal pa
Decode z <0: 3> to select one of the address configuration select signals for several types of address maps and bring it to H level.

As described above, this embodiment has the following effects. (1) In the asynchronous memory device as well, similar to each of the above-described embodiments, by changing the logical address map shape, efficient access and reduction of current consumption can be achieved.

(2) By adopting the illegal entry method, there is no need to change the conventional part, and it is possible to easily cope with it with less labor. The above embodiment may be modified into the following modes.

The number of bits of the memory cell, the address configuration,
The switching type of the address configuration may be changed as appropriate. When the depth of the X address is smaller than the depth of the Y address, the address configuration setting terminal can be shared by the address terminals that are not used when active. The command for setting the address configuration can be a precharge command or another new command in addition to the active command.

The function of changing the address map is independently realized for each bank. System performance is further improved by setting (changing) the logical address map for each bank.

The function of changing the address map may be fixed by the bonding or the product by the internal fuse, or by the customer by the internal ROM function. The vendor may fix each product for a specific purpose, or the customer may rewrite the ROM in the memory device for each system (characteristic) and use it.

The position of the address bit to be clamped may be changed appropriately. -The position of the address bit to be invalidated may be changed appropriately. In each of the above embodiments, the logical address map shape can be changed from outside at any time, but a ROM such as bonding or Fuse is provided, and the logical address map shape is changed to a desired shape at the time of shipment or user use,
You may make it maintain the shape. Also, a ROM that can be rewritten from the outside may be provided, and the logical address map shape may be changed as necessary. In these cases, the logical address map shape is fixed for a short period or a long period. Therefore, the existing program and CPU can be used. Further, it is possible to save the trouble of changing the logical address map shape for each row access cycle.

In each of the above embodiments, the memory device which takes in the X address and the Y address by the address multiplex system is embodied, but the memory device having all the external input terminals corresponding to the X address and the Y address is embodied. It may be embodied.

The various embodiments described above can be summarized as follows. (Supplementary Note 1) In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address, the logical address of the memory array is controlled to change the logical address map shape of the memory array. Storage device equipped with map changing means. (1) (Appendix 2) The storage device according to Appendix 1, wherein the map changing unit changes the logical address map shape each time the memory array is activated. (2) (Supplementary note 3) The storage device according to Supplementary note 1 or 2, wherein the setting of the logical address map shape is performed during a standby period or at the time of switching from standby to active by external access. (Supplementary note 4) The storage device according to any one of supplementary notes 1 to 3, wherein the address map is changed at least during a period from activation to deactivation of the circuit based on the first or second address. (Supplementary note 5) The storage device according to any one of Supplementary notes 1 to 4, wherein the depth of at least one of the first and second addresses is changed to change the shape of the logical address map. (Supplementary note 6) The storage device according to any one of supplementary notes 1 to 5, comprising a control terminal for controlling the logical address. (Supplementary note 7) The storage device according to any one of supplementary notes 1 to 6, wherein the memory array is composed of a plurality of banks, and a logical address map shape can be set for each bank. (Supplementary Note 8) In a storage device that accesses a memory array in which memory cells are arrayed at a first address and a second address, the first memory is accessed based on access form information that changes a logical address map shape of the memory array.
A storage device comprising address control means for replacing a part of the external address with the first address or the second address in each cycle of inputting an external address for access in the address direction. (3) (Supplementary note 9) In a storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address, based on access form information for changing a logical address map shape of the memory array, The first
A storage device comprising address invalidation means for invalidating the external address or a part of the external address for each cycle of inputting an external address for access in the address direction. (4) (Supplementary note 10) The storage device according to supplementary note 9, wherein the address invalidating means includes means for clamping an arbitrary address in order to vary a compression rate of decoding. (Supplementary Note 11) An address configuration selection circuit that generates the address configuration selection signal according to the setting of the logical address map shape by a control signal to which the access form information is applied or a combination of a plurality of control signals is provided, 10. The storage device according to appendix 8 or 9, wherein the control means or the address invalidation means executes the replacement or the invalidation based on an address configuration selection signal. (Supplementary Note 12) An external address is input, and based on the address configuration selection signal, an output signal thereof is converted into a first signal generation circuit for generating a selection signal in the first address direction and a selection signal in the second address direction. 12. The storage device according to any one of appendices 8 to 11, comprising an address generation circuit having a switching unit that switches to a second signal generation circuit to generate. (Supplementary Note 13) A first signal generating circuit which inputs an external address and generates a selection signal in the first address direction based on the address configuration selection signal, and an external address which is input based on the address configuration selection signal. 12. The storage device according to any one of appendices 8 to 11, further comprising a second signal generation circuit that generates the selection signal in the second address direction. (Supplementary Note 14) The storage device according to Supplementary Note 8 or 9, wherein the address control unit or the address invalidation unit includes a ROM such as a bonding or a Fuse that stores the access form information. (Supplementary note 15) The storage device according to supplementary note 8 or 9, wherein the address control unit or the address invalidation unit includes an externally rewritable ROM that stores the access form information. (Supplementary Note 16) An internal control method in a memory device for accessing a memory array in which memory cells are arrayed at a first address and a second address, the access form information changing a logical address map shape of the memory array. On the basis of the above, an internal control method in a storage device which replaces a part of the external address with the first address or the second address in each cycle in which the external address for access in the first address direction is input. (5) (Supplementary note 17) An internal control method in a memory device for accessing a memory array in which memory cells are arrayed at a first address and a second address, the access including changing a logical address map shape of the memory array. An internal control method in a storage device, which invalidates the external address or a part thereof every cycle when an external address for access in the first address direction is input based on form information. (6) (Supplementary note 18) The supplementary information is set during the standby period or at the same time as the active operation.
An internal control method in the storage device according to 6 or 17. (Supplementary note 19) The internal control method for a storage device according to any one of supplementary notes 16 to 18, wherein the number of activated sense amplifiers is controlled according to the shape of the logical address map. (Additional remark 20) The internal control method in the storage device according to any one of additional remarks 16 to 19, wherein a compression rate of decoding is varied according to the shape of the logical address map. (Supplementary Note 21) The address configuration selection signal is generated according to the setting of the logical address map shape by a control signal to which the access form information is applied or a combination of a plurality of control signals, and based on the address configuration selection signal. 21. The internal control method for a storage device according to any one of appendices 16 to 20, which executes the replacement or the invalidation. (Supplementary note 22) The internal control method in the storage device according to supplementary note 21, wherein the first and second addresses are generated by a common address generating means, and an output destination of the common address generating means is switched by the address configuration selection signal. (Supplementary note 23) The storage device according to supplementary note 21, further comprising first and second address generating means for generating the first and second addresses according to an external address, and switching the input destination of the external address with the address configuration selection signal. Internal control method. (Supplementary Note 24) In a system comprising a storage means and a control means for accessing and controlling the storage means, the control means supplies the access form information at any time to the storage means, and the storage means is a first A system for changing a logical address map form of a memory array in which memory cells are arrayed at an address and a second address according to the access form information. (7) (Supplementary note 25) The system according to supplementary note 24, wherein the control means supplies the access form information by any one of address, data, and code information by a control signal.
(8) (Supplementary note 26) The system according to supplementary note 24 or 25, wherein the control means supplies the access form information at the same time as or before the start of access. (Supplementary note 27) The supplementary note 24 or 26, wherein the control means supplies the access form information from code information by a control signal, and the storage means receives the code information in accordance with an edge of a pulse signal of a constant cycle. system. (Supplementary note 28) A method for controlling a storage means in a system including a storage means and a control means for accessing and controlling the storage means, wherein the control means stores the storage information according to access mode information at each time. A control method of a storage means in a system for controlling to change a logical address map form of a memory array in which memory cells are arrayed at a first address and a second address included in the means according to the access form information. (9)

[0171]

As described above in detail, according to the inventions described in 1 to 4, it is possible to provide a storage device capable of efficient access and reduction of current consumption.

As has been described in detail above, according to the fifth and sixth aspects of the present invention, it is possible to provide an internal control method of a storage device which can achieve efficient access and reduction of current consumption.

As described in detail above, according to the inventions of claims 7 and 8, it is possible to provide a system capable of achieving efficient access and reduction of current consumption. As has been described in detail above, according to the invention described in claim 9, it is possible to provide a method of controlling the storage means in the system which achieves efficient access and reduction of current consumption.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an outline of an SDRAM.

FIG. 2 is a schematic block diagram of a memory according to the first embodiment.

FIG. 3 is a block diagram of a memory system.

FIG. 4 is an explanatory diagram of an address configuration suitable for Y-direction priority operation.

FIG. 5 is an explanatory diagram of an address configuration suitable for X-direction priority operation.

FIG. 6 is an explanatory diagram of current consumption according to an address configuration and an access order.

FIG. 7 is an explanatory diagram of an address map.

FIG. 8 is an explanatory diagram of an address map.

FIG. 9 is a schematic block diagram of another memory device.

FIG. 10 is a schematic block diagram of a memory device according to a second embodiment.

11 is a timing diagram of FIG.

FIG. 12 is a block diagram of an address generation circuit.

FIG. 13 is a schematic block diagram of a memory device according to a third embodiment.

FIG. 14 is a timing diagram of FIG. 13.

FIG. 15 is a schematic block diagram of another memory device.

FIG. 16 is a block diagram of an address generation circuit.

FIG. 17 is a timing diagram of the asynchronous memory according to the fourth embodiment.

FIG. 18 is a timing diagram of a completely asynchronous memory.

FIG. 19 is a waveform diagram illustrating a mode setting cycle.

FIG. 20 is an explanatory diagram of commands.

FIG. 21 is a waveform diagram illustrating a mode setting cycle.

FIG. 22 is an operation waveform diagram of the program mode setting circuit.

FIG. 23 is an operation waveform diagram of the program mode setting circuit.

FIG. 24 is an operation waveform diagram of the combined entry signal generation circuit.

FIG. 25 is an operation waveform diagram of a mode setting address buffer.

FIG. 26 is an operation waveform diagram of a mode setting address latch.

FIG. 27 is an operation waveform diagram of the mode setting decoder.

[Explanation of symbols]

11 CPU as control means 12 Memory device as storage means 10 system

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Claims (9)

[Claims] 1. A storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address, wherein a logical address of the memory array is controlled to change a logical address map shape of the memory array. A storage device provided with a map changing means for performing. 2. The storage device according to claim 1, wherein the map changing unit changes the logical address map shape each time the memory array is activated. 3. A memory device for accessing a memory array in which memory cells are arrayed at a first address and a second address, wherein the memory array accesses the memory array based on access form information for changing a logical address map shape of the memory array. A storage device comprising address control means for replacing a part of the external address with the first address or the second address for each cycle in which the external address for access in the direction of one address is input. 4. A storage device for accessing a memory array in which memory cells are arrayed at a first address and a second address, wherein the memory array accesses the memory array based on access form information for changing a logical address map shape of the memory array. A storage device comprising address invalidation means for invalidating the external address or a part of the external address for each cycle in which an external address for one-address access is input. 5. An internal control method in a memory device for accessing a memory array in which memory cells are arrayed at a first address and a second address, the access form information changing a logical address map shape of the memory array. An internal control method in a storage device, which replaces a part of the external address with the first address or the second address every cycle when the external address for access in the first address direction is input based on the above. 6. An internal control method in a memory device for accessing a memory array in which memory cells are arrayed at a first address and a second address, the access form information changing a logical address map shape of the memory array. The internal control method in the storage device, wherein the external address or a part thereof is invalidated every cycle when the external address for access in the first address direction is input. 7. A system comprising a storage means and a control means for accessing and controlling the storage means, wherein the control means supplies occasional access form information to the storage means, and the storage means comprises: A system for changing a logical address map form of a memory array in which memory cells are arrayed at a first address and a second address according to the access form information. 8. The system according to claim 7, wherein the control means supplies the access form information by any one of address, data and code information by a control signal. 9. A method for controlling a storage means in a system including a storage means and a control means for accessing and controlling the storage means, wherein the control means is configured to operate according to access form information at each time. A method for controlling a storage unit in a system for controlling a logical address map form of a memory array in which memory cells are arrayed at a first address and a second address included in the storage unit according to the access form information.