JP2003151264A - Ferroelectric memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ferroelectric memory device whose configuration is simple and which can be functioned surely by unnecesitating a transistor or selection provided for every memory cell while considering peculiar conditions in a ferroelectroc substance. SOLUTION: This device is provided with a plurality of X axis electrode lines, a plurality of Y axis electrode lines intersecting orthogonally with these plurality of X axis electrode lines, and ferroelectric capacitors connected directly between both electrode lines at intersection positions of these X axis electrode lines and Y axis electrode lines, when a basic anti-electric field is assumed to Ec, write-in voltage is set to voltage being higher than 1.Ec and lower than 2.Ec.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device using a ferroelectric material for an insulating film of a capacitor for information storage,
In particular, it relates to a ferroelectric memory device having an array of ferroelectric memory cells.

[0002]

2. Description of the Related Art As shown in the characteristic diagram of FIG. 9, a ferroelectric substance has an electric polarization P that is generated once an electric field E is applied.
Remains even if the electric field is no longer applied, and the direction of polarization is reversed when an electric field of a certain strength or more is applied in the direction opposite to the above electric field (see A, B, C in the figure). , D).

A ferroelectric memory device using this ferroelectric material as an insulating film of a capacitor for information storage utilizes high-speed polarization reversal (a polarization reversal speed is several ns) and its residual polarization of a ferroelectric thin film. It is a non-volatile memory that can be rewritten at high speed.

The voltage required for the polarization reversal of the ferroelectric thin film is low (about 1 to 2 V), and it is not necessary to apply a high voltage (for example, 10 to 12 V) for writing or reading like EEPROM and flash memory, and the low voltage is required. Can operate with a single power supply.

FIG. 10 is a diagram showing a ferroelectric memory device having a one-transistor / one-capacitor cell structure using such a ferroelectric memory. In this figure, Q0
0 to Qn1 are selection transistors, C00 to C
n1 is a ferroelectric capacitor for storing information, WL0 to WLn are word lines connected to the gates of the selection transistors Q00 to Qn1, and BL0 and BL1 are bit lines.
PL0 to PLn are plate lines, Cbl0 and Cbl1
Is a bit line capacitor indicating the parasitic capacitance of the bit lines BL0 and BL1. The selection transistor Q00 and the ferroelectric capacitor C00 form a set of memory cells MC00, and the other memory cells MC01 to MCn1 are also the same. A large number of such memory cells are arranged to form a memory array. Further, 1 is a bit line selection circuit, 2 is a word line selection circuit, 3 is a plate line selection circuit, 4 is a reference voltage V of the bit lines BL0 and BL1 and the reference voltage generation circuit 6.
It is a sense amplifier that detects a potential difference between r.

In the ferroelectric memory device configured as described above, writing and reading of data are performed as follows. Here, the writing and reading of data will be described taking the ferroelectric memory cell MC00 as an example.

As for the operation at the time of writing, the bit line BL0 is set to the H level by the bit selection circuit 1, the word line WL0 is set to the H level by the word line selection circuit 2 to turn on the selection transistor Q00, and the plate The line selection circuit 3 changes the potential of the plate line PL0 to, for example, FIG.
As shown in FIG. 1, the L level is first changed to the H level, and then changed to the L level.

The potential change L-H- of the plate line PL0
Through L, the ferroelectric capacitor C on the bit line BL0 side
00 is in a positive polarization state. This state is the state of data "1".

Next, regarding the read operation, first, in the initial state, the plate line PL0 is set to the L level by the plate line selection circuit 3, and the bit line BL0 is set to the L level by the bit line selection circuit 1 to 0V. Precharge.
After that, a bit line B is generated by a signal from the bit line selection circuit 1.
L0 is set in a floating state, and the word line selection circuit 2 operates to set the word line WL0 to the H level and select transistor Q.
00 is turned on. In this state, the ferroelectric capacitor C00 and the bit line capacitor C on the bit line BL0 side
bl0 is connected in series.

Next, when an H level potential is applied from the plate line selection circuit 3 to the plate line PL0, the bit line BL
The potential of 0 is the potential corresponding to the electrostatic capacitance of the ferroelectric capacitor C00 and the bit line capacitor Cbl0.
It occurs on L0. When the stored data is "1", the ferroelectric capacitor C00 on the bit line BL0 side is polarization-inverted, and a relatively high potential resulting from this is generated on the bit line BL0. On the contrary, if the stored data is "0", the ferroelectric capacitor C00 of the bit line BL0 does not undergo polarization reversal, and a very low potential is applied to the bit line BL0.
Will happen on top.

The bit line BL0 and the reference voltage generating circuit 6
The sense amplifier 4 detects the potential difference between the reference voltages Vr of the above and identifies "1" and "0" of the data.

Since the memory using the ferroelectric capacitor is a destructive read in which the data is once destroyed when the data is read, the bit line BL0 is set to the H level (data "1") based on the detection content of the sense amplifier 4. in the case of)
Is applied and the data is rewritten.

[0013]

As described above, since the memory device using the ferroelectric capacitors is arranged in a matrix, the selecting transistor is provided for each memory cell. If there is no selection transistor, a voltage is applied to the ferroelectric capacitor (eg, C00) of the memory cell to be selected at the time of writing, and the ferroelectric capacitors of other memory cells (eg, C10, C11, C
The voltage is also applied to 01). This is a so-called crosstalk phenomenon, but a selection transistor is provided like other DRAMs or the like for the purpose of avoiding erroneous selection due to this phenomenon.

Conventionally, regarding the ferroelectric capacitor, the idea has not been established regarding the change of the coercive electric field when a plurality of ferroelectrics are combined in series and parallel, and the crosstalk phenomenon at the time of writing and reading operations is considered. In order to avoid it, it was unavoidable to install the selection transistor as described above.

However, recently, the present inventors have advanced the analysis of the ferroelectric substance, and it has been clarified that the characteristic thereof can be expressed as a double saturation function model and each characteristic of the ferroelectric capacitor can be specified numerically. It was

In view of the above, the present invention eliminates the selection transistor provided for each memory cell in consideration of the condition peculiar to the ferroelectric substance, and has a simple structure and a reliable ferroelectric memory. The purpose is to provide a device.

[0017]

According to another aspect of the present invention, a ferroelectric memory device has a plurality of X-axis electrode lines, a plurality of Y-axis electrode lines intersecting with the plurality of X-axis electrode lines, and the X-axis electrodes. Line and Y
A ferroelectric capacitor directly connected between both electrode lines at an intersection with the axis electrode line, and when the basic coercive electric field of the ferroelectric capacitor is Ec, when writing data,
The write voltage is set to a voltage higher than 1 · Ec and lower than 2 · Ec, and the X-axis electrode line and / or the Y-axis electrode line other than the selected X-axis electrode line and Y-axis electrode line is set to the write voltage. It is characterized in that the voltage is set to about half of the above.

According to the ferroelectric memory device of claim 1 of the present invention, the write voltage is larger than 1 · Ec and 2 · E.
Since the voltage is set smaller than c, the voltage required for polarization reversal is applied to the selected ferroelectric capacitor. On the other hand, since crosstalk needs to pass through three or more adjacent ferroelectric capacitors, the X-axis and Y-axis electrode lines other than the selected electrode line, which is a part of this path, are approximately half the write voltage. By setting to, the crosstalk phenomenon does not occur because only the voltage of Ec or less is applied to the ferroelectric capacitors other than the selected ferroelectric capacitor.

Therefore, since the selection transistor which has conventionally been required for each memory cell can be omitted, the structure of the ferroelectric memory device can be simplified,
Also, the required area becomes smaller.

According to a second aspect of the present invention, there is provided a ferroelectric memory device according to the first aspect, which has a two-capacitor type structure in which two ferroelectric capacitors are paired and polarized in opposite polarities. Characterize.

According to the ferroelectric memory device of the second aspect of the present invention, since two ferroelectric capacitors polarized in opposite polarities are stored as a set, the detection voltage is determined by the difference between both outputs. . For this reason, the absolute value of detection becomes large and the variation is canceled, so that stable detection can be performed.

According to another aspect of the ferroelectric memory device of the present invention, there is provided a ferroelectric layer, a plurality of upper electrodes provided on one surface side of the ferroelectric layer and extending in the X-axis direction, and other ferroelectric layers. It is characterized in that it comprises a plurality of lower electrodes provided on the surface side and extending in the Y-axis direction orthogonal to the upper electrode, and that a ferroelectric capacitor is formed at each intersection of the upper electrode and the lower electrode. .

According to the ferroelectric memory device of the third aspect of the present invention, the ferroelectric layer can be uniformly formed as a wide film or substrate, and the upper electrode and the lower electrode can be formed on both surfaces of the film or the like and in a direction orthogonal to each other. Since it is only necessary to form each of them, the configuration is simplified and the degree of integration can be made extremely high. still,
In using this ferroelectric memory device, a voltage higher than 1 · Ec and lower than 2 · Ec is used as a write voltage.

According to a fourth aspect of the present invention, there is provided a ferroelectric memory device in which a source region and a drain region of the first conductivity type, a channel region of the second conductivity type formed between the source region and the drain region, and a channel region are formed. A memory gate which is a conductor layer formed to be insulated from the channel region, a ferroelectric layer formed on the memory gate, and a control gate which is a conductor layer formed on the ferroelectric layer. A ferroelectric memory device in which provided memory gate type ferroelectric memory elements are connected in a matrix, wherein a drain line connecting drain regions of ferroelectric memory elements in the same row in each column, and the same row in each column , A memory gate line connecting the memory gates of the ferroelectric memory device, a source line connecting the source regions of the ferroelectric memory devices in the same column of each row, a ferroelectric memory of the same column in each row Comprising a control gate line, which connects the control gates of the child, the basic coercive field of the ferroelectric layer when the Ec, when data is written,
The write voltage is set to a voltage higher than 1 · Ec and lower than 2 · Ec, and the memory gate line and / or the control gate line other than the selected memory gate line and the control gate line is set to a voltage approximately half the write voltage. It is characterized by setting to.

According to the ferroelectric memory device of the fourth aspect of the present invention, the write voltage is larger than 1 · Ec and 2 · E.
Since the voltage is set smaller than c, the voltage required for polarization reversal is applied to the ferroelectric layer of the selected ferroelectric memory element. On the other hand, since crosstalk needs to pass through the ferroelectric layers of three or more adjacent ferroelectric memory elements, memory gate lines and control gate lines other than the selected line which is a part of this path are Since the voltage is set to about half of the write voltage, only the voltage of Ec or less is applied to the ferroelectric capacitors other than the selected ferroelectric capacitor, so that all three ferroelectric layers are polarized inversion. The necessary voltage is not applied and the crosstalk phenomenon does not occur.

Therefore, it is not necessary to provide a selection transistor for each memory cell in order to avoid the crosstalk phenomenon, so that the structure of the ferroelectric memory device can be simplified.

According to another aspect of the ferroelectric memory device of the present invention, the source and drain regions of the first conductivity type, the channel region of the second conductivity type formed between the source region and the drain region, and the channel region are formed. A floating gate which is a conductor layer formed to be insulated from the channel region, a ferroelectric layer formed on the floating gate, a control gate which is a conductor layer formed on the ferroelectric layer,
A ferroelectric memory device in which floating gate type ferroelectric memory elements are connected in a matrix, the drain lines connecting the drain regions of the ferroelectric memory elements in the same row in each column, and the same column in each row. A source line for connecting the source region of the ferroelectric memory device, and when the basic coercive electric field of the ferroelectric layer is Ec, it is applied between the source region or the drain region and the control gate during data writing. Write voltage is set to a voltage at which a voltage greater than 1 · Ec and less than 2 · Ec is applied to the ferroelectric layer, and a source line other than the selected source line or drain line and control gate line or The drain line and / or the control gate line are set to a voltage approximately half the write voltage. And wherein the door.

According to the ferroelectric memory device of the fifth aspect of the present invention, the write voltage is set to a voltage at which a voltage higher than 1 · Ec and lower than 2 · Ec is applied to the ferroelectric layer. Therefore, the voltage required for polarization reversal is applied to the ferroelectric layer of the selected ferroelectric memory element. on the other hand,
Since crosstalk must pass through three or more adjacent ferroelectric memory devices, the source line or drain line other than the selected line, which is a part of this path, and the control gate line are approximately half the write voltage. By setting to, the crosstalk phenomenon does not occur because only the voltage of Ec or less is applied to the ferroelectric capacitors other than the selected ferroelectric capacitor.

Therefore, it is not necessary to provide a selection transistor for each memory cell in order to avoid the crosstalk phenomenon, so that the structure of the ferroelectric memory device can be simplified.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the characteristics of the ferroelectric portion, which is the main part of the ferroelectric memory device, will be described.

The hysteresis characteristic representing the relationship between the voltage applied to the ferroelectric substance and the polarization charge is modeled as a sum of non-inversion terms and inversion terms including a simple saturation function, that is, a double saturation function model. The non-inversion term is a term that does not accompany the inversion of spontaneous polarization in the hysteresis characteristic of the ferroelectric substance. In the non-inversion term, when the applied voltage is zero, the polarization charge becomes zero regardless of whether the applied voltage is zero. That is, the non-inverting term has no hysteresis. On the other hand, the inversion term is a term that accompanies the inversion of spontaneous polarization in the hysteresis characteristic of the ferroelectric substance. In the inversion term, when the applied voltage is zero, the polarization charge does not become zero but shows a constant value. The polarization charge at this time is called remanent polarization charge (or simply “residual polarization”).
The remanent polarization differs depending on whether the applied voltage is changed from positive to zero or from negative to zero. That is, the inversion term has hysteresis.

Using the basic coercive electric field Ec, the input voltage Vin applied to the ferroelectric substance is set to −n · Ec ≦ Vin ≦ n · E.
It is given in the range of c (however, 1 ≦ n).

The non-inversion term calculation means calculates the non-inversion term saturation charge Q.
The non-inverting term Qp is calculated according to the following mathematical formula based on pmax and the non-inverting term power receiving sensitivity constant Kp. Qp = -Qpmax {1 1 exp (Kp · Vin)} where −n · Ec ≦ Vin <0 Qp = Qpmax {1-exp (−Kp · Vin)} where 0 ≦ Vin ≦ n · Ec

Here, the non-inverting term saturation charge Qpmax and the non-inverting term power receiving sensitivity constant Kp correspond to the amplitude Va (= n · Ec) of the constant sampling AC voltage Vin (= Vasinωt) applied to the ferroelectric. Difference saturation polarization charge Ppmax and difference power receiving sensitivity constant K obtained by approximating the difference dielectric polarization charge Pp between the saturation polarization charge Ps and the residual polarization charge Pr corresponding to the amplitude Va
It is calculated as pp. Pp = Ppmax {1-exp (-Kpp · Va)}

The inversion term calculation means calculates the inversion term saturation charge Qrm.
ax, inversion term power receiving sensitivity coefficient Krn, and basic coercive electric field Ec
The first inversion term Qr
l and the second inversion term Qr2 are calculated. The first inversion term Qr1 is an inversion term when the input voltage Vin rises from the negative voltage −n · Ec to the positive voltage n · Ec, and the second inversion term Qr2 is the input voltage Vin when the input voltage Vin is the positive voltage n · Ec. It is an inversion term when falling from Ec to a negative voltage −n · Ec. Qrl = -Qrmax [1-exp {Krn. (-E
c)}] where −n · Ec ≦ Vin ≦ 0 Qrl = −Qrmax [1-exp {Krn (Vin−
Ec)}] where 0 ≦ Vin ≦ Ec Qrl = Qrmax [1-exp {-Krn (Vin-Ec)}] where Ec ≦ Vin ≦ n · Ec Qr2 = -Qrmax [1-exp {Krn (Vin + Vin +
Ec)}] where −n · Ec ≦ Vin ≦ −Ec Qr2 = Qrmax [1-exp {−Krn (Vin +
Ec)}] where −Ec ≦ Vin ≦ 0 Qr2 = Qrmax [1-exp {−Krn · Ec}] where 0 ≦ Vin ≦ n · Ec

Here, the inversion term saturation charge Qrmax, the inversion term power receiving sensitivity constant Kr and the basic coercive electric field Ec are the constant sampling AC voltage Vin (= Vasin) applied to the ferroelectric substance.
Remanent polarization saturation charge Prmax and remanent polarization coercive electric field Er obtained by approximating the residual polarization charge Pr corresponding to the amplitude Va (= n · Ec) of ωt) by the following formula.
It is calculated as c. Pr = Prmax [1-exp {-Kr (Va-Er
c)}] where Va ≧ Erc

Further, the inversion term power receiving sensitivity coefficient Krn is calculated according to the following equation based on the remanent polarization power receiving sensitivity constants Kr and n in the above equation. Krn = Kr
However, “Ec ≦ Vin ≦ n · Ec” when the input voltage Vin rises from the negative voltage −n · Ec to the positive voltage n · Ec.
, And when the input voltage Vin falls from the positive voltage n · Ec to the negative voltage −n · Ec, “−n · Ec ≦ Vin ≦.
-Ec "area. Krn = (n−1) Kr However, when the input voltage Vin rises from the negative voltage −n · Ec to the positive voltage n · Ec, the region of “0 ≦ Vin ≦ Ec” and the input voltage Vin is the positive voltage n · Ec. A region of “−Ec ≦ Vin ≦ 0” when the voltage drops from Ec to a negative voltage −n · Ec.

The synthesizing means calculates the first history characteristic Q1 and the second history characteristic Q2 according to the following mathematical expressions. Q1 = Qp + Qrl Q2 = Qp + Qr2

The non-inversion term saturation charge Qpmax used in the non-inversion term calculation means, the non-inversion term power reception sensitivity constant Kp, and the basic coercive electric field Ec, the inversion term saturation charge Qrmax, and the remanent polarization power reception sensitivity constant Kr used in the inversion term calculation means. ,
It is called a characteristic constant that represents the hysteresis characteristic of a ferroelectric substance. These 5
One characteristic constant can be used to specify the hysteresis characteristic peculiar to the ferroelectric capacitor. Further, by using nl and n2 that define the applied voltage V, the hysteresis characteristic of the ferroelectric capacitor under an arbitrary applied voltage V can be simulated.

As described above, the hysteresis characteristic peculiar to the ferroelectric capacitor can be specified, but by using the analysis result, the assembly of the ferroelectric capacitors connected in series or in parallel for the first time. It is now possible to specify the history characteristics as.

Generally speaking, the method for obtaining the hysteresis characteristic of the aggregate of the ferroelectric capacitors is, in the case of series connection, by adding the numerical values related to the horizontal axis (function of the input voltage Vin), and also in parallel. In the case of connection, the characteristics can be expressed by adding the numerical values related to the vertical axis (charge item). This has been obtained in the experiment.

An example of the case of serial connection will be described with reference to FIG. When the input voltage Vin is applied to the series circuit of the ferroelectric capacitors C1 and C2 as shown in FIG. 8A, the inversion term Qr1 of the ferroelectric capacitor C1, the divided voltage Vin1 and the ferroelectric capacitor C2 are applied. The inversion term Qr2 and the divided voltage Vin2 are as shown in FIGS. Here, Ec1 and Ec2 are respective basic coercive electric fields, and the inversion term Qr1 and the inversion term Qr2.
Are equal in value because they are connected in series.

As shown in FIG. 7D, the combined characteristics are such that the basic coercive electric field is the sum of Ec1 and Ec2, and the voltage V
in also becomes the sum voltage (Vin1 + Vin2). Note that the remanent polarization power reception sensitivity constant Kr has a gentler slope by the composite amount. Although this is a study on the inversion term, the hysteresis characteristic in the case of series connection can be easily obtained by similarly obtaining the non-inversion term and adding it to the inversion term.

Moreover, since the basic coercive electric field in the case of series connection is the sum of the individual basic coercive electric fields, it is clear that polarization inversion does not occur while a voltage lower than the sum of the basic coercive electric fields is applied. Becomes

In this way, as shown in FIG. 2, not only simple series (a) and parallel (b) but also series-parallel (c,
As for the characteristic of d), by repeating the series or parallel procedure,
You can ask for it as well.

These series-connected parallel-connected ferroelectric capacitors have new hysteresis characteristics different from the hysteresis characteristics of the individual ferroelectric capacitors. Therefore, by forming the ferroelectric capacitors having the same or different characteristics in various serial-parallel connection configurations, it is possible to obtain a ferroelectric capacitor assembly having a desired hysteresis characteristic by means of a circuit.

Next, an embodiment of the present invention will be described with reference to the drawings based on the above-described examination of the ferroelectric capacitor.

FIG. 3 shows a ferroelectric memory device of an embodiment of the present invention, which is a ferroelectric memory device of 1C structure corresponding to the conventional 1Tr.1C structure. Bit lines BL0 to BL2 are provided as a plurality of X-axis electrode lines, and plate lines PL0 to PLn are provided as a plurality of Y-axis electrode lines intersecting these bit lines BL0 to BL2.
Ferroelectric capacitor C00 directly connected between the lines 0 to BL2 and the plate lines PL0 to PLn at the intersections.
To Cn2. When the basic coercive electric field of the ferroelectric capacitors C00 to Cn2 is Ec, the write voltage is set to a voltage higher than 1 · Ec and lower than 2 · Ec.

As can be seen from comparison with FIG. 10 shown as a conventional example, FIG. 3 excludes the select transistors Q00 to Qn1 from each memory cell, and the word line W.
L0 to WLn and the word line selection circuit 2 are unnecessary. However, instead, the write voltage is set to a specific range based on the characteristic analysis of the ferroelectric capacitor.

In the ferroelectric memory device of the present invention configured as described above, data writing and reading are performed as follows. Here, the ferroelectric memory cell MC00
As an example, data writing and reading will be described.

Regarding the operation at the time of writing, the bit line BL0 is set to H level (or L level) by the bit selection circuit 1, and the potential of the plate line PL0 is first set to L level and then to H level by the plate line selection circuit 3. The level is changed so that it becomes the L level. Assuming that this L level is zero voltage, the H level is 1 · Ec <H level <
2 · Ec.

Further, at the time of this writing, the unselected bit lines BL1 and BL2 are fixed to the voltage of half the H level.

The unselected bit lines BL1,
The reason why BL2 is fixed to half the voltage of the H level is to divide the crosstalk path by fixing it at a predetermined potential. Therefore, instead of the unselected bit lines BL1 and BL2, the unselected plate lines PL1 to PLn may be fixed at a predetermined potential, and the unselected bit lines BL1 and BL2 and the plate lines PL1 to PL1 may be fixed. PLn may be fixed at a predetermined potential.

Potential change L-H- of this plate line PL0
Through L, the ferroelectric capacitor C on the bit line BL0 side
00 has a positive (or negative) polarization state when a voltage is applied as indicated by the solid line in the figure. This state is a state of data "1" (or "0"). The voltage of the difference between the H level and the L level becomes the write voltage Ew.

At this time, the bit line BL0 and the plate line PL
Between 0 and 0, for example, ferroelectric capacitors C10, C11
And C01 (or C12 and C02) form a crosstalk path as indicated by a broken line in the figure. However, the write voltage Ew is set to the relationship of 1 · Ec <Ew <2 · Ec with respect to the basic coercive electric field Ec of each ferroelectric capacitor, and the write voltage Ew is abbreviated except for the bit line BL0. Since the voltage is set to half, the ferroelectric capacitors C10, C11 and C01 (or C12 and C)
The crosstalk path shown by the broken line in the figure through 02) is cut by a voltage lower than Ec, crosstalk does not occur, and only the ferroelectric capacitor C00 is normally selected.

Next, regarding the read operation, first, in the initial state, the plate line PL0 is set to the L level by the plate line selection circuit 3, and the bit line BL0 is set to the L level by the bit line selection circuit 1 to 0V. Precharge.
After that, the bit line B
Make L0 floating. In this state, the ferroelectric capacitor C00 and the bit line capacitor C on the bit line BL0 side
bl0 is connected in series.

At this time, the bit lines BL1 and BL2 other than the selected bit line BL0 are set to a read voltage, that is, a voltage half the H level. This prevents the memory cells other than the selected memory cell, that is, the ferroelectric capacitors such as MC01 and MC02 from being applied with a voltage of Ec or more and preventing their storage states from being inverted. In addition, the plate lines PL1 to P that are not selected
Ln may also be set to half the voltage of the H level at the same time.

Next, when an H level potential is applied from the plate line selection circuit 3 to the plate line PL0, the bit line BL
The potential of 0 is the potential corresponding to the electrostatic capacitance of the ferroelectric capacitor C00 and the bit line capacitor Cbl0.
It occurs on L0. When the stored data is "1", the ferroelectric capacitor C00 on the bit line BL0 side is polarization-inverted, and a relatively high potential resulting from this is generated on the bit line BL0. On the contrary, if the stored data is "0", the ferroelectric capacitor C00 of the bit line BL0 does not undergo polarization reversal, and a very low potential is applied to the bit line BL0.
Will happen on top.

Like the write voltage Ew, the voltage Er at the time of reading is also the basic coercive electric field E of each ferroelectric capacitor.
The relation of 1 · Ec <Er <2 · Ec is set for c. Therefore, by setting the bit lines BL1 and BL2 other than the selected bit line BL0 to the read voltage, that is, half the H level voltage, the polarization states of capacitors other than the selected ferroelectric capacitor C00 are changed. No voltage that can be reversed is applied,
Data is read normally.

The bit line BL0 and the reference voltage generating circuit 6
The sense amplifier 4 detects the potential difference between the reference voltages Vr of the above and identifies "1" and "0" of the data.

Since the memory using the ferroelectric capacitor is a destructive read in which the data is once destroyed when the data is read, the bit line BL0 is set to the H level (data "1") based on the detection content of the sense amplifier 4. in the case of)
Is applied and the data is rewritten.

A voltage equal to or lower than the basic coercive electric field voltage Ec is applied to the memory cells other than the selected memory cell at the time of writing and reading. When a voltage of Ec or less is applied, it goes without saying that polarization inversion does not occur, but the non-inversion term charge Qp goes in and out of the ferroelectric capacitor according to the applied voltage, D
A RAM-like operation is performed. However, the level is small and does not affect the detection operation.

Although the read operation of FIG. 3 has been described by reading the stored data of the ferroelectric memory cell MC00 independently, instead of this, a memory cell group in a horizontal row coupled to the plate line PL0, that is, MC00, MC
The storage data of 01 and MC02 may be collectively read.

That is, in this case, first, in the initial state, the plate line PL0 is set to the L level by the plate line selection circuit 3 and all the bit lines BL are set by the bit line selection circuit 1.
0 to BL2 are set to L level and precharged to 0V. After that, the bit lines BL0 to BL2 are brought into a floating state by a signal from the bit line selection circuit 1. In this state, the ferroelectric capacitors C00 to C02 and the bit line capacitors Cbl0 to CB12 on the bit line side are connected in series.

From the plate line selection circuit 3 to the plate line PL
When an H level potential is applied to 0, the bit lines BL0 to B0
The potential of L2 is generated on the bit lines BL0 to BL2 according to the electrostatic capacitance of the ferroelectric capacitors C00 to C02 and the bit line capacitors Cbl0 to CB12. The ferroelectric capacitors C00 to C02 whose stored data is "1" undergo polarization inversion, and a relatively high potential resulting from this is generated on the bit lines BL0 to BL2. vice versa,
The ferroelectric capacitors C00 to C02 whose stored data is "0" do not undergo polarization reversal, and extremely low potentials are generated on the bit lines BL0 to BL2.

The sense amplifier 4 detects the potential difference between the bit lines BL0 to BL2 and the reference voltage Vr of the reference voltage generation circuit 6 to discriminate between "1" and "0" of the data. Although only the sense amplifier for the bit line BL0 is shown in FIG. 3, a sense amplifier is provided for each bit line.

Since the memory using the ferroelectric capacitor is a destructive read in which the data is destroyed once at the time of reading the data, the data is read out to the bit lines BL0 to BL2 based on the detection content of each sense amplifier 4. A voltage is applied according to the data "1" or "0" and the data is rewritten.

In the ferroelectric memory device shown in FIG. 3, the selection transistor conventionally required for each memory cell can be omitted, so that the structure can be simplified and the size can be reduced.

FIG. 4 is a ferroelectric memory device of another embodiment of the present invention, which is a ferroelectric memory device of 2C structure corresponding to the conventional 2Tr / 2C structure.

Bit line BL0a as a plurality of X-axis electrode lines
To BL2b and plate lines PL0 to PL as a plurality of Y-axis electrode lines intersecting these bit lines BL0a to BL2b.
3 are provided, and ferroelectric capacitors C00a to C32b are directly connected between the bit lines BL0a to BL2b and the plate lines PL0 to PL3 at intersections. Then, in order to form a two-capacitor type configuration in which two capacitors are paired and polarized in opposite polarities,
The memory cells MC00 to MC are arranged so that the ferroelectric capacitors C00a and C00b form the memory cell MC00.
32 is configured.

These ferroelectric capacitors C00a to C3
When the basic coercive electric field of 2b is Ec, the write voltage is
The voltage is set to be larger than 1 · Ec and smaller than 2 · Ec.

This FIG. 4 eliminates the selection transistor from each memory cell, as in FIG.
The word line and the word line selection circuit are unnecessary.

In the ferroelectric memory device of the present invention having such a configuration, data writing and reading are performed as follows. Here, the ferroelectric memory cell MC00
As an example, data writing and reading will be described.

Regarding the operation at the time of writing, the bit line BL0a is set to the H level (or L level) by the bit selection circuit 1, and conversely, the bit line BL0b is set to the L level (or H level), and the plate line selection circuit is set. 3, the potential of the plate line PL0 is first set to the L level and then to the H level,
Further, it is changed so as to reach the L level. If this L level is zero voltage, the H level is 1 · Ec <H level <2 · Ec.

Further, at the time of this writing, the unselected bit lines BL1a to BL2b are fixed to the voltage of half the H level.

The unselected bit line BL1a
~ BL2b instead of the unselected plate line PL
1 to PL3 may be fixed at a predetermined potential, and unselected bit lines BL1a to BL2 and plate lines PL1 to PL3 may be fixed at a predetermined potential.

Potential change L-H- of this plate line PL0
Through L, the ferroelectric capacitor C00a on the bit line BL0a side and the ferroelectric capacitor C on the bit line BL0b side
00b is a positive and negative (or negative and positive) polarized state. This state is a state of data "1" (or "0"). The voltage of the difference between the H level and the L level becomes the write voltage Ew.

At this time, a crosstalk path is formed between the bit lines BL0a and BL0b and the plate line PL0 via another ferroelectric capacitor. However, the write voltage Ew is set to the relationship of 1 · Ec <Ew <2 · Ec with respect to the basic coercive electric field Ec of each ferroelectric capacitor, and the write voltage Ew is abbreviated except for the bit line BL0. Since the voltage is set to half, the crosstalk path through the other ferroelectric capacitors is cut by a voltage lower than Ec, crosstalk does not occur, and the ferroelectric capacitor C00a of the memory cell MC00 is normally formed. , C00b
Only selected.

Next, regarding the read operation, first, in the initial state, the plate line PL0 is set to the L level by the plate line selection circuit 3, and the bit lines BL0a and BL0b are set to the L level by the bit line selection circuit 1. Precharge to 0V. After that, the bit lines BL0a and BL0b are brought into a floating state by a signal from the bit line selection circuit 1. In this state, the ferroelectric capacitor C00a and the bit line BL
The bit line capacitor Cbl0a on the 0a side is connected in series, and the ferroelectric capacitor C00b and the bit line BL0b are connected.
The bit line capacitor Cbl0b on the side is connected in series.

At this time, the selected bit lines BL0a, B0
The bit lines BL1a to BL2b other than L0b are set to a read voltage, that is, a voltage that is half the H level. Memory cells MC other than the memory cell MC00 selected by this
It is possible to prevent the ferroelectric capacitors 01 to MC32 from being applied with a voltage of Ec or more, and to prevent their storage states from being inverted. The plate lines PL1 to PLn that are not selected may be set to half the voltage of the H level at the same time.

Next, when an H level potential is applied from the plate line selection circuit 3 to the plate line PL0, the bit line BL
The potentials of 0a and BL0b are the ferroelectric capacitor C00.
a, C00b and bit line capacitors Cbl0a, Cbl
The potential corresponding to the electrostatic capacitance with 0b is applied to the bit lines BL0a, B0.
Each occurs on L0b.

If the stored data is "1",
The ferroelectric capacitor C00a on the side of the bit line BL0a undergoes polarization reversal, and the relatively high potential resulting from this causes a bit line B
L0a, while the ferroelectric capacitor C00b of the bit line BL0b does not undergo polarization reversal, and an extremely low potential occurs on the bit line BL0b. Therefore, this difference voltage is detected by the sense amplifier 4 and the data is " It is determined to be 1 ″.

On the contrary, when the stored data is "0", the ferroelectric capacitor C00 on the bit line BL0b side.
b is polarization-inverted, and a relatively high potential resulting from this is generated on the bit line BL0b, while the ferroelectric capacitor C00a of the bit line BL0a is not polarization-inverted and a very low potential is generated on the bit line BL0a. Therefore, the differential voltage of opposite polarity is detected by the sense amplifier 4, and it is determined that the data is “0”.

The difference voltage applied to the sense amplifier 4 is determined by the difference between the read voltages of the two ferroelectric capacitors polarized in opposite polarities, so that the absolute value becomes large and the detection margin is large. Become. Further, even if each detected voltage value rises or falls due to a temperature change or a temporal change, the variation is canceled and the difference is secured, so that stable detection can be performed. Furthermore, the influence of other incidental capacitance components is canceled.

Like the write voltage Ew, the voltage Er at the time of reading is also the basic coercive electric field E of each ferroelectric capacitor.
The relation of 1 · Ec <Er <2 · Ec is set for c. Therefore, the selected bit lines BL0a, B0
The bit lines BL1a to BL2b other than L0b are set to the read voltage, that is, half the H level voltage, so that the selected ferroelectric capacitors C00a and C00 are selected.
A voltage that reverses the polarization state of the capacitors other than b is not applied, and the data is normally read.

Since the memory using the ferroelectric capacitor is a destructive read in which the data is once destroyed when the data is read, based on the detected content of the sense amplifier 4, if the data is "1", the bit line An H level voltage is applied to BL0a and an L level voltage is applied to the bit line BL0b,
The data is rewritten.

The read operation of FIG. 4 has been described by reading the stored data of the ferroelectric memory cell MC00 independently. However, instead of this, a memory cell group in a horizontal row coupled to the plate line PL0, that is, MC00, MC
The storage data of 01 and MC02 may be collectively read.

That is, in this case, the specific read operation is only the 2C configuration, and the memory cell group in one horizontal row, that is, MC00, MC01, MC0 described in FIG. 3 is used.
Since the operation is the same as the operation of collectively reading the storage data of No. 2, the description thereof will be omitted for simplicity.

Also in the ferroelectric memory device of FIG. 4,
Similar to FIG. 3, since the selection transistor conventionally required for each memory cell can be omitted, the configuration can be simplified and the size can be reduced.

FIG. 5 is a diagram showing a configuration example of the memory section of the ferroelectric memory device as shown in FIG.

The ferroelectric layer Fsub is used in the memory section of this ferroelectric memory device. The ferroelectric layer Fsub may be provided as a single layer for the entire memory device, and may be composed of a ferroelectric substrate or film. And
Bit electrode lines BL0 to BLi as upper electrodes extending in the X-axis direction are provided on one surface side of the ferroelectric layer Fsub, and plate electrode lines PL0 as a plurality of lower electrodes extending in the Y-axis direction on the other surface side. ~ PLi are provided. With this structure alone, ferroelectric capacitors are formed at the respective intersections of the bit electrode lines BL0-BLi and the plate electrode lines PL0-PLi.

Since the ferroelectric substance is polarized only in one direction, there is no horizontal crosstalk inside the ferroelectric layer Fsub. For example, the shaded bit electrode line BL1 in FIG.
When a voltage is applied between the plate electrode line PL1 and the plate electrode line PL1,
Only that intersection (which is a cross-hatched line) is selected.
The crosstalk is a path through the electrode lines as described in FIGS. 3 and 4, but the write and read voltages are larger than 1 · Ec and 2 · Ec as in the examples of FIGS. 3 and 4. It is not affected by setting the voltage lower than Ec, setting the electrode lines not selected to half the write and read voltages, and so on.

According to this ferroelectric memory device, the ferroelectric layer Fsub can be uniformly formed as a wide film or substrate, and the bit electrode lines BL0 to BL0 are formed on both surfaces of the film or the like in the orthogonal direction.
Since it is only necessary to form BLi and the plate electrode lines PL0 to PLi, the configuration is simplified and the degree of integration can be made extremely high.

Although FIG. 5 shows a configuration example of the memory unit of the ferroelectric memory device of FIG. 3, the memory unit of the ferroelectric memory device of FIG. 4 can be similarly configured. it can.

FIGS. 6 and 8 are diagrams showing a configuration example of a ferroelectric memory device in which ferroelectric memory elements using the field effect of the remanent polarization of the ferroelectric in a MOS-FET are connected in a matrix. is there. FIG. 6 shows an example in which a memory gate type in which writing is directly performed using a memory gate is used as a ferroelectric memory element, and FIG. 8 is a floating gate that does not have a terminal for directly applying a voltage. This is an example of using a type.

The memory gate type ferroelectric memory device is
As shown in FIG. 7, a source region 22 and a drain region 24 of the first conductivity type, and a source region 22 and a drain region 24.
A channel region 26 of the second conductivity type formed between the channel region 26 and the insulating layer 28.
A memory gate MG which is the lower conductor layer 30 formed via the ferroelectric layer 32 formed on the lower conductor layer 30 and a conductor layer 34 formed on the ferroelectric layer 32. It is configured with a control gate CG. A floating gate type ferroelectric memory device has no memory gate MG terminal.

In FIG. 6, the drain lines DL1 to DL3 connecting the drain regions of the ferroelectric memory elements in the same row in each column and the memory gates MG of the ferroelectric memory elements in the same row in each column are connected. Memory gate line M
GL1 to MGL3, source lines SL1 to SL3 that connect the source regions of the ferroelectric memory elements in the same column in each row,
Control gate lines CGL1 to connect the control gates CG of the ferroelectric memory elements in the same column in each row
It is equipped with CGL3. Note that R is a detection resistor, which is provided separately for each of the drain lines DL1 to DL3.

When recording information in the ferroelectric memory elements M11 to M33, the control gate electrode CG is used.
A voltage is applied between the memory gate electrode MG and the memory gate electrode MG. As a result, the ferroelectric layer 32 is polarized, and the polarized state is maintained even after the voltage is removed. By changing the polarity of the applied voltage, two polarization states having different polarities can be obtained, and the two states can be recorded in a nonvolatile manner.

When the control gate electrode CG side is polarized as the positive electrode, the voltage of the control gate electrode CG necessary for forming the channel becomes small.
When the side of the control gate electrode CG is polarized as a negative electrode, the voltage of the control gate electrode CG necessary for forming the channel becomes large. Therefore, a voltage between both voltages is applied to the control gate electrode CG, and the potentials of the drain lines DL1 to DL3, which are determined by whether or not a channel is formed, that is, the magnitude of the current flowing between the drain and the source, are detected. Thus, the recorded information can be read.

Also in the ferroelectric memory device in which the ferroelectric memory elements are connected in a matrix, in order to avoid the influence of crosstalk, conventionally, a selection transistor is provided in the control gate CG or the like, and a plurality of reference voltages are used. It has been necessary to devise a circuit such as providing different types and switching.

However, in the present invention, when the basic coercive electric field of the ferroelectric layers of the ferroelectric memory elements M11 to M33 is Ec, the write voltage and the read voltage are larger than 1 · Ec and smaller than 2 · Ec. It is set to voltage.

Further, at the time of this writing, unselected control gate lines CGL2, CGL3
Is fixed to half the write voltage.

The unselected control gate lines CGL2 and CGL3 are fixed to half the write voltage because the crosstalk path is divided by fixing it at a predetermined potential. Therefore, the unselected control gate line CGL
Instead of 2, CGL3, unselected memory gate lines MGL2, MGL3 may be fixed at a predetermined potential, and unselected control gate lines CGL2, CGL3 and memory gate lines MGL2.
The MGL3 may be fixed at a predetermined potential.

Therefore, a voltage necessary for polarization reversal is applied to the ferroelectric layer of the selected ferroelectric memory element (for example, M11). On the other hand, crosstalk is caused by three adjacent ferroelectric memory devices (for example, M21, M22, M1).
Although it is necessary to pass through the ferroelectric layer of 2), the write voltage Ew is set to 1 with respect to the basic coercive electric field Ec of each ferroelectric layer.
・ Ec <Ew <2 · Ec is set, and the voltage other than the control gate CGL1 is set to the write voltage E.
Since the voltage is set to about half the voltage of w, the crosstalk path through the ferroelectric layer is cut by a voltage lower than Ec, crosstalk does not occur, and only the ferroelectric layer of M11 normally operates. To be selected.

In the ferroelectric memory device of FIG. 6, the power supply voltage VDD and the drain line DL are used as the reading means.
1 to DL3, a detection resistor R is individually provided to detect a voltage drop. Instead of the detection resistor R, a drain line selection transistor is provided for each drain line. It may be configured to selectively detect.

Therefore, it becomes unnecessary to provide a selection transistor for each memory cell as in the conventional case.
The structure of the ferroelectric memory device can be simplified.

FIG. 8 shows a ferroelectric memory device using the field effect of the remanent polarization of a ferroelectric substance in a MOS-FET, which uses a floating gate type device having no terminal for directly applying a voltage. It is a figure which shows the structural example of a dielectric memory device.

In this floating gate type ferroelectric memory device, a part of the voltage applied between the substrate such as the drain or source region and the control gate CG is applied to the ferroelectric layer 32 for writing, so that the polarization is inverted. Is done.

Therefore, the voltage that contributes to the polarization inversion, that is, the write voltage is determined by the capacitance ratio of the capacitor capacitance of the ferroelectric layer 32 and the MOS capacitance of the insulating layer 28.
Therefore, the voltage applied to the ferroelectric layer 32 is 1 · Ec
So that the voltage is larger and smaller than 2.Ec,
The voltage to be applied will be determined. In this case, the capacitance ratio between the capacitor capacitance of the ferroelectric layer 32 and the MOS capacitance of the insulating layer 28 changes depending on the temperature, the change over time, etc., so it is necessary to allow a certain amount of allowance for the determination.

Since the write operation and the read operation are performed in the same manner as in the configuration example of FIG. 6, the repetitive description will be omitted.

In the ferroelectric memory device of FIG. 8 as well, as in the case of FIG. 6, the write voltage is 1.
Since a voltage higher than Ec and lower than 2.Ec is set, a voltage required for polarization reversal is applied to the ferroelectric layer of the selected ferroelectric memory element. On the other hand, since a voltage of Ec or less is applied to the ferroelectric capacitors other than the selected ferroelectric capacitor, the crosstalk phenomenon does not occur.

In the ferroelectric memory device shown in FIGS. 6 and 8, an example in which each memory cell is composed of one dielectric memory cell has been described. However, each memory cell also has two ferroelectric materials. It is also possible to provide a ferroelectric memory device of a memory cell having a two-element configuration in which memory elements are used and stored in opposite polarities. In this case, the same effect as that described for the ferroelectric memory device having the 2C configuration in FIG. 4 can be further exerted.

[0113]

According to the ferroelectric memory device of the first aspect of the present invention, the write voltage is larger than 1 · Ec and 2 · Ec.
Since the voltage is set lower than Ec, the voltage required for polarization reversal is applied to the selected ferroelectric capacitor. On the other hand, since crosstalk needs to pass through the three adjacent ferroelectric capacitors, the voltage required for polarization reversal is not applied to any of the three ferroelectric capacitors, and the crosstalk phenomenon occurs. Does not occur.

Therefore, since the selection transistor which has conventionally been required for each memory cell can be omitted, the structure of the ferroelectric memory device can be simplified,
Also, the required area becomes smaller.

According to the ferroelectric memory device of the second aspect of the present invention, since two ferroelectric capacitors polarized in opposite polarities are stored as a set, the detection voltage is determined by the difference between both outputs. . For this reason, the absolute value of detection becomes large and the variation is canceled, so that stable detection can be performed.

According to the ferroelectric memory device of the third aspect of the present invention, the ferroelectric layer can be uniformly formed as a wide film or substrate, and the upper electrode and the lower electrode are formed in the direction orthogonal to both surfaces of the film or the like. Since it only needs to be formed, the structure is simplified and the degree of integration can be extremely increased. When using this ferroelectric memory device, a write voltage of 1
A voltage greater than Ec and less than 2.Ec will be used.

According to the ferroelectric memory device of the fourth aspect of the present invention, the write voltage is larger than 1 · Ec and 2 · E.
Since the voltage is set smaller than c, the voltage required for polarization reversal is applied to the ferroelectric layer of the selected ferroelectric memory element. On the other hand, since the crosstalk needs to pass through the ferroelectric layers of the three adjacent ferroelectric memory elements, the voltage required for polarization inversion cannot be applied to any of the three ferroelectric layers. There is no crosstalk phenomenon.

Therefore, in order to avoid the crosstalk phenomenon, it is not necessary to selectively use a plurality of types of write voltages or to provide a selection transistor for each memory cell as in the conventional case. The configuration of the device can be simplified.

According to the ferroelectric memory device of the fifth aspect of the present invention, the write voltage is set to a voltage at which a voltage higher than 1 · Ec and lower than 2 · Ec is applied to the ferroelectric layer. Therefore, the voltage required for polarization reversal is applied to the ferroelectric layer of the selected ferroelectric memory element. on the other hand,
Since crosstalk must pass through three or more adjacent ferroelectric memory devices, the source line or drain line other than the selected line, which is a part of this path, and the control gate line are approximately half the write voltage. By setting to, the crosstalk phenomenon does not occur because only the voltage of Ec or less is applied to the ferroelectric capacitors other than the selected ferroelectric capacitor.

Therefore, in order to avoid the crosstalk phenomenon, it is not necessary to provide a selection transistor for each memory cell as in the conventional case, so that the structure of the ferroelectric memory device can be simplified.

[Brief description of drawings]

FIG. 1 is a characteristic analysis diagram when a ferroelectric capacitor is connected in series.

FIG. 2 is a diagram showing an example of series-parallel connection of ferroelectric capacitors.

FIG. 3 is a diagram showing the configuration of a ferroelectric memory device having a one-capacitor cell structure according to the present invention.

FIG. 4 is a diagram showing the configuration of a ferroelectric memory device having a 2-capacitor cell structure according to the present invention.

FIG. 5 is a diagram showing a configuration example of a memory unit of a ferroelectric memory device of a ferroelectric memory device having a one-capacitor cell structure according to the present invention.

FIG. 6 is a diagram showing a configuration example of a ferroelectric memory device in which memory gate type ferroelectric memory elements are connected in a matrix according to the present invention.

FIG. 7 is a diagram showing a configuration of a ferroelectric memory element.

FIG. 8 is a diagram showing a configuration example of a ferroelectric memory device in which floating gate type ferroelectric memory elements are connected in a matrix according to the present invention.

FIG. 9 is a hysteresis characteristic diagram of a ferroelectric substance.

FIG. 10 is a diagram showing a configuration of a ferroelectric memory device having a 1-transistor / 1-capacitor cell structure using a conventional ferroelectric memory.

FIG. 11 is a diagram showing an example of an applied potential of a plate line.

[Explanation of symbols]

1-bit line selection circuit 3 Plate line selection circuit 4 sense amplifier 6 Reference voltage generator MC00-MCn2 memory cells C00-Cn2 Ferroelectric capacitor PL0 to PLn plate line BL0 to BLn Bit line cbl bit line capacitor Fsub dielectric layer M11 to M33 ferroelectric memory device SL1 to SL3 source lines DL1 to DL3 drain lines CGL1 to CGL3 Control gate line MGL1 to MGL3 Memory gate lines

Claims (5)

[Claims] 1. A plurality of X-axis electrode lines, a plurality of Y-axis electrode lines intersecting with the plurality of X-axis electrode lines, and both electrode lines at intersections of the X-axis electrode lines and the Y-axis electrode lines. A ferroelectric capacitor directly connected between the ferroelectric capacitors and the basic coercive electric field of the ferroelectric capacitor is Ec, the write voltage is set to a voltage higher than 1 · Ec and lower than 2 · Ec. A ferroelectric memory device characterized by the above. 2. The ferroelectric memory device according to claim 1, wherein the ferroelectric memory device has a two-capacitor type configuration in which two ferroelectric capacitors are paired and polarized in opposite polarities. 3. A ferroelectric layer, a plurality of upper electrodes provided on one surface side of the ferroelectric layer and extending in the X-axis direction, and an upper electrode provided on the other surface side of the ferroelectric layer. 2. A ferroelectric memory device comprising a plurality of lower electrodes extending in the Y-axis direction orthogonal to, and forming a ferroelectric capacitor at each intersection of the upper electrode and the lower electrode. 4. A source region and a drain region of the first conductivity type, a channel region of the second conductivity type formed between the source region and the drain region, and a channel region formed on the channel region and insulated from the channel region. A ferroelectric memory device having a memory gate which is a conductive layer, a ferroelectric layer formed on a memory gate, and a control gate which is a conductive layer formed on the ferroelectric layer. A ferroelectric memory device connected in a matrix, wherein a drain line connecting the drain regions of the ferroelectric memory elements in the same row in each column and a memory gate of the ferroelectric memory elements in the same row in each column are connected. Memory gate line, a source line connecting the source regions of the ferroelectric memory devices in the same column of each row, and a controller connecting the control gates of the ferroelectric memory devices in the same column of each row. And a basic coercive electric field of the ferroelectric layer is Ec, the write voltage is set to a voltage higher than 1 · Ec and lower than 2 · Ec. Body memory. 5. A source region and a drain region of the first conductivity type, a channel region of the second conductivity type formed between the source region and the drain region, and formed on the channel region and insulated from the channel region. Floating gate type ferroelectric memory including a floating gate which is a conductive layer, a ferroelectric layer formed on the floating gate, and a control gate which is a conductive layer formed on the ferroelectric layer In a ferroelectric memory device in which elements are connected in a matrix, a drain line connecting the drain regions of the ferroelectric memory elements in the same row in each column and a source region of the ferroelectric memory elements in the same column in each row are connected. A source line to be connected is provided, and when the basic coercive electric field of the ferroelectric layer is Ec, and when the data is written, the source region or the drain region and the coercive field are connected. The write voltage applied between the control gates is larger than 1 · Ec in the ferroelectric layer and 2
-A voltage lower than Ec is set, and the source line or drain line and / or control gate line other than the selected source line or drain line and control gate line are set to approximately half the write voltage. A ferroelectric memory device characterized by setting.