JP2003150576A - Fft arithmetic unit and fft arithmetic method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up an FFT arithmetic operation by allowing pipeline processing in respective FFT arithmetic stage units by avoiding access competi tion to the same bank. SOLUTION: Respective memories 7 and 9 are divided into the i number of banks according to the data number i simultaneously inputted to a butterfly arithmetic operation part 21. The readout/write-in address of data to the respective banks is controlled by two address forming parts 11 and 13. When the memory 7 outputs the data to the butterfly arithmetic operation part 21 in a certain FFT arithmetic stage, the memory 9 stores an output result from the butterfly arithmetic operation part 21 via a swap means 23 and a selector 25, and while, when the memory 9 outputs the data to the butterfly arithmetic operation part 21, the memory 7 stores the output result from the butterfly arithmetic operation part 21 via the swap means 23 and the selector 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FF that performs a fast Fourier transform (FFT).
The present invention relates to a T calculation device and an FFT calculation method.

[0002]

2. Description of the Related Art An FFT arithmetic unit is generally constructed by combining butterfly arithmetic units. FIG. 10 shows the conventional 1
It is a figure which shows an example of the processing procedure of 6-point FFT calculation. As shown in the figure, for example, in the FFT operation with the number of data N = 16, the processing in the 4-point FFT operation device (butterfly operation unit) 101 composed of a plurality of (here, four) butterfly operation units is predetermined. The number of times (here 8
Times) by executing. Although a plurality of 4-point FFT operation devices 101 are shown in FIG. 10 for the sake of convenience, the actual operation is one 4-point FF.
It is performed by using the T arithmetic unit 101 repeatedly.

Specifically, in step 1, first,
Data x (0), x (4), x sampled at every 4 points from the memory 103 storing 16 data
(8) and x (12) are sequentially read to execute the 4-point FFT operation. Then, the operation result is sequentially stored in the memory 105 every other point in g2 (0), g2 (1), g2 (2), and g2 (3). Then, continuously, data x (1), x (5), x sampled from the memory 103 at every 4 points.
(9), x (13) are read out, 4-point FFT operation is executed, and the operation result is g2 (4), g2 (5), g in the memory 105.
Sequentially store in 2 (6) and g2 (7). Thereafter, in the same manner, the 4-point FFT operation is executed on all the data in the memory 103, and the operation result is mapped in the memory 105.

Next, in step 2, from the result obtained in step 1, the memory 1
The data is sequentially read every four points from 05, and the four-point FFT operation is executed. The result of executing the 4-point FFT operation on all the data in the memory 105 is output as data X (0), X (1), ..., X (14), X (15), and the number of data N = 16. The FFT calculation of is completed.

[0005]

However, the conventional FFT operation device has the following problems.

First, in the case where the memory is composed of only four banks as shown in FIG. 10 (four bank structure), but only one bank, only one data is stored in one memory access. Since it cannot be read, it is necessary to sequentially read the four pieces of data input to the 4-point FFT operation device from the memory in a time-division manner. Therefore, pipeline processing cannot be performed, which is a constant for increasing the speed of the FFT operation. There is a limit.

That is, when performing pipeline processing,
In order to read four data as pipeline stages, it is necessary to have four stages for reading data (M1, M2, M3, M4, EX, ...).
Here, M1 is the first data read stage, M
2 is the second data read stage, M3 is the third data read stage, M4 is the fourth data read stage, and EX is the 4-point FFT execution stage. Thus, for example, M2 stage and M
If one stage is overlapped (such overlap occurs in pipeline processing), it is not possible to read simultaneously, so pipeline processing cannot be performed.

Next, in order to read out the four data required for the 4-point FFT operation at the same time, as shown in FIG. 10, even when the memory 103 and the memory 105 have a four-bank configuration, with respect to the writing to the memory 105, Access conflict occurs in the same bank, and a plurality of writes in the same bank conflict. Therefore, in this case as well, pipeline processing cannot be performed, and there is a certain limit to speeding up the FFT operation.

That is, for example, the FFT processing is performed in the following three steps.
Think of it as a stage pipeline. The first stage is FF
A stage for reading the data of the T operation target from the memory 103, a second stage for executing the FFT operation,
The third stage is a stage for writing the calculation result to the memory 105. At this time, as for reading from the memory 103, since one data is read from each bank, simultaneous reading can be performed in one stage (one cycle). However, regarding writing to the memory 105, in order to enable reading of four data at the same time in step 2, the 4-point FFT operation device 101
Since it is necessary to write the four data output from the same bank to the same bank, if the data is written to the same bank in one cycle at this time, access conflict occurs and pipeline processing cannot be performed. Further, regarding the writing of the memory 105, as shown in FIG. 11, when the four data output from the 4-point FFT operation unit 101 are written in four banks respectively so that access conflict does not occur, simultaneous writing is performed in one cycle. However, access conflict occurs in reading from the memory 105 when the FFT operation of step 2 is performed. Therefore, in either case, pipeline processing cannot be performed.

The present invention has been made in view of the above points, and an FFT arithmetic unit capable of speeding up the FFT arithmetic by improving a method of mapping data to an intermediate buffer required for the FFT arithmetic. And an FFT calculation method.

[0011]

(1) An FFT operation device according to the present invention comprises a butterfly operation unit, a first storage unit configured to include a plurality of banks and storing data processed by the butterfly operation unit, A first address generation unit that generates a data read address for the first storage unit so that access to the same bank does not conflict when reading data from the first storage unit, and a calculation result output from the butterfly calculation unit. A rearrangement unit for rearranging, a second storage unit configured from a plurality of banks for storing data output from the rearrangement unit, and an access to the same bank do not conflict when writing data to the second storage unit. And a second address generation unit that generates an address for writing data to the second storage unit.

According to this structure, when the data is read from the first storage unit and the data is written to the second storage unit, address control is performed so that accesses to the same bank do not conflict with each other. Since it is avoided and pipeline processing can be performed in units of each FFT operation stage, FFT operation can be performed at high speed.

(2) In the FFT operation device of the present invention, in the above configuration, an input buffer for temporarily storing data to be FFT processed and data stored in the input buffer are set in the first storage section. And a data conversion unit that converts the data into a predetermined data array.

According to this structure, the data to be FFT processed is temporarily stored in the input buffer beforehand, and the data stored in the input buffer is converted into a predetermined data array and stored in the first storage section. The FFT operation can be performed at high speed on arbitrary data.

(3) In the FFT arithmetic unit of the present invention, in the above-mentioned constitution, the butterfly arithmetic unit is constructed by arranging one or a plurality of two-input butterfly arithmetic units in parallel.

According to this configuration, one or a plurality of two-input butterfly computing units are arranged in parallel to form the butterfly computing unit, so that a plurality of data can be processed in arbitrary units in parallel. Coupled with the fact that pipeline processing can be performed in units of FFT operation stages, FFT operations can be performed at higher speed.

(4) In the FFT operation device of the present invention having the above-mentioned configuration, the first storage unit and the second storage unit are both two data that are simultaneously input to the butterfly operation unit at each address. Take the configuration to memorize.

According to this configuration, the first storage section and the second storage section
In the storage unit, since two data that are simultaneously input to the butterfly computing unit are stored at each address, it is possible to reduce the number of designated addresses for reading and writing addresses at one time, and access conflict for the same bank. In combination with avoiding the above and enabling pipeline processing in units of each FFT operation stage, the FFT operation can be performed at a higher speed.

(5) In the FFT operation device of the present invention, in the above configuration, when the butterfly operation unit is configured by arranging one or a plurality of two-input butterfly operation units in parallel, the data conversion unit. Has a configuration in which the conversion process is performed so that two addresses that are simultaneously input to the butterfly computing unit are stored in each address in the first storage unit.

According to this structure, in the first storage section, two data that are simultaneously input to the butterfly computing unit are stored at each address, so that it is possible to reduce the number of addresses to be read at one time. Coupled with the fact that pipeline processing can be performed in units of each FFT operation stage while avoiding access competition for the same bank, FFT operation can be performed at higher speed.

(6) In the FFT operation device of the present invention, in the above-mentioned configuration, both the first storage unit and the second storage unit have the same number of banks as the number of data simultaneously input to the butterfly operation unit. The configuration is composed of.

According to this structure, the first storage section and the second storage section
Since each storage unit is composed of the same number of banks as the number of data input to the butterfly operation unit at the same time, it is possible to avoid access conflict for the same bank and perform pipeline processing in units of each FFT operation stage. The calculation can be performed at high speed.

(7) In the FFT operation device of the present invention, the first storage section and the second storage section are composed of two memories, and one of the two memories corresponds to an FFT operation stage. The configuration further includes a switching unit that selectively switches the functions of the two memories so that the second memory functions as the first memory and the other functions as the second memory.

According to this structure, two memories are provided, and when one functions as the first storage unit, the other functions as the second memory.
Since switching control is performed so that it functions as a storage unit,
Pipeline processing can be performed with the minimum required number of memories, and FFT operation can be performed at high speed.

(8) The receiving apparatus of the present invention has a configuration including any one of the FFT arithmetic units described above.

According to this structure, it is possible to provide a receiving device having the same effects as the above.

(9) The wireless communication terminal device of the present invention has a configuration including the above-mentioned receiving device.

With this configuration, it is possible to provide a wireless communication terminal device having the same effects as the above.

(10) The base station apparatus of the present invention has a configuration including the above receiving apparatus.

With this configuration, it is possible to provide a base station device having the same effects as the above.

(11) In the FFT operation method of the present invention, the access to the same bank is prevented from competing when reading data from the first storage unit which is composed of a plurality of banks and which stores the data processed by the butterfly operation unit. First
A first address generation step of generating a data read address for the storage section, a rearrangement step of rearranging the operation results output from the butterfly operation section, and a plurality of banks which are output in the rearrangement step. A second address generating step of generating an address for writing data to the second storage unit so that access to the same bank does not conflict when writing data to the second storage unit which stores data.

According to this method, address control is performed so that access to the same bank does not conflict when reading data from the first storage unit and when writing data to the second storage unit. Since it is avoided and pipeline processing can be performed in units of each FFT operation stage, FFT operation can be performed at high speed.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an FF according to an embodiment of the present invention.
It is a block diagram which shows the structure of T arithmetic unit.

This FFT operation device has an input buffer 1 in which N = 2 ^k (k is a positive integer) data to be subjected to FFT operation is initially stored, a data conversion section 3, and a first selector 5.
A first memory 7, a second memory 9, a first address generator 11, a second address generator 13, and a second memory
Selector 15, a third selector 17, a fourth selector 19, a butterfly computing unit 21, a swap means (sorting unit) 23, a fifth selector 25, and a sixth selector 27. . Here, in the following description, the total number of FFT-processed data is N = 2 ^k (k is a positive integer), and the number of butterfly calculators arranged in parallel that configure the butterfly calculator 21 is b, Let i be the number of data that are simultaneously input to the butterfly operation unit 21 (i = 2b when the butterfly operation unit has two inputs).

The input buffer 1 is a buffer in which N pieces of data to be FFT processed are initially stored, and here it is assumed that one data is stored in one address. The input buffer 1 can be composed of a plurality of banks so that a plurality of data can be read simultaneously.

The data conversion unit 3 includes the input buffers 1 to m.
The (0 ≦ m <N / 2) -th data and the (m + N / 2) -th data are read out, the two read-out data are combined into one word (see FIG. 2), and the 1 to the memory 7. Here, FIG. 2 shows an arrangement of data stored in the memory. Then, the value of the parameter m is incremented from 0 to (N / 2−1) and the above processing is performed to load all the data in the input buffer 1 into the first memory 7. At this time, the input address of the data combined in one word to the first memory 7 depends on the number i of input data to the butterfly operation unit 21, and the data combined in the data conversion unit 3 is i. The data is input to the first memory 7 every other address.

The selector 5 selects either the output of the data converter 3 or the output of the selector 25. Specifically, only when the data is first loaded from the input buffer 1 to the first memory 7, the output of the data conversion unit 3 is selected,
After that, the output of the selector 25 is selected.

The first memory 7 and the second memory 9 are
In order to avoid access contention for the same bank, it is divided into i banks according to the number i of data that is simultaneously input to the butterfly operation unit 21. In each of the memories 7 and 9, the read address and the write address of data for each memory bank are
It is controlled by the first address generator 11 and the second address generator 13.

The first memory 7 and the second memory 9 each store an operation result of the butterfly operation unit 21 when the FFT operation stage outputs data to the butterfly operation unit 21. There are times when it takes action. Specifically, in a certain FFT operation stage, when the first memory 7 is outputting data to the butterfly operation unit 21, the second memory 9 uses the swap result of the output result from the butterfly operation unit 21. 23 and the selector 25, and conversely, when the second memory 9 is outputting data to the butterfly computing unit 21, the first memory 7 swaps the output result from the butterfly computing unit 21. The operation of storing via the means 23 and the selector 25 is performed.

The first address generator 11 controls the read address when either the first memory 7 or the second memory 9 performs the read operation.

The reading procedure will be described with reference to FIG. FIG. 3 shows a bank configuration of the first memory 7 and the second memory 9. For the sake of convenience, the first memory 7 and the second memory 9 are abbreviated as “first memory 7 (second memory 9)”.

Banks of the first memory 7 (second memory 9) divided into i banks are bank0, b
If ank1, ..., bank (i-1) are set, the first address generation unit 11 determines that b banks, that is, ba
The first address of each bank of nk0, bank1, ..., Bank (b-1) is selected at once, and the first memory 7 (second memory 9) is selected.
The read operation is controlled to cause the butterfly operation unit 21 to output data in parallel from the first memory 7 (second memory 9). Then, the address to be read next is the remaining b (i = 2b) banks, that is, bank (b), ban.
It becomes the head address of each bank of k (b + 1), ..., Bank (i-1), data is read from the selected address, and the data is output in parallel to the butterfly operation unit 21. Then, when data is read up to bank (i-1), it returns to the highest bank again, and this time, bank0, bank1, ..., bank (b
The read address is controlled so that the data is read from the address that is incremented by 1 from the start address of (-1). Thereafter, similarly, the read address is controlled so that all the data is read from the first memory 7 (second memory 9).

In the second address generation unit 13, one of the first memory 7 and the second memory 9 is the swap means 2
The write address at the time of performing the write operation of the output result of 3 is controlled.

Here, the writing procedure will be described with reference to FIG. For the i physical banks that have been divided, b logical banks bank0-1 (bank0 and
area of bank1), bank2-3 (area of bank2 and bank3), ...
Consider bank (i-2)-(i-1) (area of bank (i-2) and bank (i-1)). In this case, the second address generation unit 13 outputs a total of b logical banks in order from the upper bank, that is, bank0-
1, bank2-3, ..., Bank (i-2)-(i-1) are selected at once for the start address of each bank, and b pieces of data output from the swap means 23 are stored in the first memory 7 (Second memory 9)
The write address is controlled so that the write addresses are simultaneously written to. Then, the next write address is controlled so that the b pieces of data output from the swap means 23 are written to the address incremented by 1 from the head address of each logical bank. Thereafter, similarly, the address is incremented each time data is written, and all the calculation results in the FFT calculation stage are stored in the first memory 7 (second
The write address is controlled so as to be written in the memory 9).

The selector 15 selects the output of the first address generator 11 when the first memory 7 performs the read operation, and the second address when the first memory 7 performs the write operation. The output of the generation unit 13 is selected.

The selector 17 selects the output of the first address generator 11 when the second memory 9 performs the read operation, and the second address when the second memory 9 performs the write operation. The output of the generation unit 11 is selected.

The selector 19 determines whether to select the first memory 7 or the second memory 9 according to the FFT operation stage.

The butterfly computing unit 21 is configured by arranging b two-input butterfly computing units in parallel. Figure 4
Shows the configuration of a two-input butterfly computing unit.

The swap means 23 is the butterfly computing unit 2
Data rearrangement (swap) is performed on the output result of 1.

The swap method will be described with reference to FIG. The data read simultaneously from the different b banks of the first memory 7 (second memory 9) are data0, data.
1, data2, ..., data (b-2), data (b-1), each data is divided into upper bits and lower bits (for example, 0_U and 0_L in the case of data0) (see FIG. 2). Reference), and is input to each of the b butterfly computing units constituting the butterfly computing unit 21. Then, the calculation result of each butterfly calculator is 0_U ', 0_L', 1_U ', 1_L', as shown in FIG.
..., (b-2) _U ', (b-2) _L', (b-1) _U ', (b-1) _L' are output. Therefore, four output results obtained by two adjacent butterfly computing units, for example, 0_U ', 0_L', 1_
For U'and 1_L ', the output results (for example, 0_U' and 1_U ') that are not multiplied by the rotor coefficient in each butterfly computing unit are the addresses of the data input to the butterfly computing unit. The output of the data having the higher order is used as the higher order bits to combine the data and output. Also, regarding the output results (for example, 0_L 'and 1_L') that are multiplied by the rotor coefficient in each butterfly computing unit, data is similarly combined and output. Then, in the same procedure, swap (sort) and combine data up to (b-2) _U ', (b-2) _L', (b-1) _U ', and (b-1) _L'. Output.

The selector 25 selects whether to output the output result from the swap means 23 to the first memory 7 or the second memory 9 according to the FFT operation stage.

The selector 27 selects the output to the outside only when the FFT operation stage is the final stage, and selects the swap means 23 side when the FFT operation stage is other than the final stage.

Next, the operation of the FFT operation device having the above configuration will be specifically described with reference to FIGS. FIG. 6 is a diagram showing a method of loading data from the input buffer 1 to the first memory 7, FIG. 7 is a diagram showing a processing procedure of 16-point FFT operation in the present embodiment, and FIG.
FIG. 9 is a diagram showing an FFT calculation process for each FFT calculation stage, and FIG. 9 is a diagram showing a swap method. here,
Taking as an example the case where the total number of FFT-processed data N = 16, the multiplier k = 4, the number b of butterfly computing units included in the butterfly computing unit 21 = 2, and the number i of data simultaneously input to the butterfly computing unit 21 = 4 explain.

First, in step 1, the data conversion unit 3
And the data is loaded from the input buffer 1 to the first memory 7 via the selector 5. At this time, as shown in FIG. 6, x (0), x (8), x
(1) and x (9), x (2) and x (10), x (3) and x (11), x (4) and x (12), x (5) and x (13), x (6) and x (14), x (7) and x (1
The data is read by the combination of 5), the two read data are combined and sequentially stored in the first memory 7. If the input buffer 1 has, for example, a two-bank configuration, two data can be read in the same cycle, and the processing speed is improved.

In the data sequentially combined in the above processing, the number i of input data to the butterfly operation unit 21 is 4
Therefore, the data is written in the first memory 7 every four addresses.

Next, in step 2, for example, 16-point FFT processing by the frequency thinning method is performed. As shown in FIG. 7, the 16-point FFT processing is performed by four stages of F
The FFT of the present invention is composed of an FT operation stage.
The arithmetic unit performs FFT processing in units of FFT arithmetic stages, and the first memory 7 and the second memory 9 are in units of FFT arithmetic stages, one of which is the butterfly arithmetic unit 2
While outputting data to 1, the other is swap means 2
The operation of storing the output of 3 is performed. At this time, the first memory 7 and the second memory 9 are each composed of four banks in order from the higher address.

First, in the FFT operation stage 1, as shown in FIG. 8, in the first cycle, the first memory 7 is
Data x (0), x (8), x from the start address of nk0 and bank1
(4) and x (12) are read out at the same time to calculate the butterfly operation unit 21.
It outputs to (two butterfly computing units 21-1).

Then, in the next cycle, a butterfly operation is performed on the data x (0), x (8), x (4), x (12) read one cycle before, and the operation result g1 (0) is obtained. , G1
Outputs (8), g1 (4), g1 (12). Further, in the same cycle, the data x (1), x (9), x (5),
x (13) is read at the same time and output to the butterfly computing unit 21 (two butterfly computing units 21-2).

Then, in the next cycle, as shown in FIG. 9, the butterfly computing unit 21 (the butterfly computing unit 2
1-1) Operation result g1 (0), g1 (8), g1 (4), g1 (12)
Is combined with g1 (4) by the swap means 23 so that g1 (0) is the upper bit, and is written to the head address of bank0 of the second memory 9, and g1 (8) is the upper bit. It is combined with g1 (12) so that it is written into the head address of bank2 of the second memory 9. In the same cycle, the data x (1), x (9), x (5), x read one cycle before
The butterfly operation for (13) is executed and the operation result g
While outputting 1 (1), g1 (9), g1 (5), g1 (13),
Data x (2), x (10), x (6), x (1) from the first memory 7
4) is read at the same time and output to the butterfly computing unit 21.

Then, the series of operations described above is executed for all the data stored in the first memory 7 to complete all the operations of the FFT operation stage 1.

At this time, the orientations of the selectors 15, 17, 19, 25 and 27 in the FFT operation stage 1 are as follows. The selector 15 selects the first address generator 11, the selector 17 selects the second address generator 13, the selector 19 selects the first memory 7, and the selector 25 selects the second memory. The memory 9 is selected as the output destination, and the selector 27 selects the swap means 23 as the output destination.

Next, in the FFT operation stage 2, the FFT
Contrary to the case of the operation stage 1, the butterfly operation unit 21
The data input to the first memory 7 is read from the second memory 9, and the calculation result of the butterfly calculation unit 21 is stored in the first memory 7. Other than this, for example, the control of the read address for the second memory 9 and the control of the write address for the first memory 7 are all the same as in the case of the FFT operation stage 1. Is omitted.

At this time, each selector 15, 17,
The directions of 19, 25, and 27 are as follows, respectively. The selector 15 selects the second address generation unit 13, the selector 17 selects the first address generation unit 11, the selector 19 selects the second memory 9, and the selector 25 selects the first address. The memory 7 is selected as the output destination, and the selector 27 selects the swap means 23 as the output destination.

Next, in the FFT calculation stage 3, the FFT
Since the same operation as in the case of the arithmetic stage 1 is performed, its explanation is omitted.

Finally, in the final stage FFT operation stage 4, unlike the operation in the case of the FFT operation stage 2, only in the final stage, the reading order from the second memory 9 is set to the second order.
The selection of the selector 17 is different from the normal operation only in the final stage FFT processing so as to follow the address control of the address generation unit 13. In this way, the second address generator 1
The second memory 9 according to the read address control by
The data output from is input to the butterfly computing unit 21. The data sequentially output from the butterfly operation unit 21 is the final FFT operation result X (0), X (8), X (4), for the data first stored in the input buffer 1.
X (12), X (2), X (10), X (6), X (14), X (1), X
(9), X (5), X (13), X (3), X (11), X (7), X (15). At this time, the selector 27 selects the output to the outside.

As described above, according to this embodiment, the first
With respect to memory access to the memory 7 and the second memory 9, the first address generation unit 11 and the second address generation unit 13 perform address control so that a plurality of accesses to the same bank are not performed at the same time. Therefore, F
Pipeline processing can be performed in units of FT operation stages, and FFT operations can be performed at high speed.

The FFT operation device according to the present embodiment is a receiving device (for example, a SUD (Single User Detection) receiving device) in a digital mobile communication system or the like, and a wireless communication terminal device (for example, a receiving device) having the receiving device. , TDD (Time Division Duplex) mobile station apparatus) and a base station apparatus.

[0069]

As described above, according to the present invention,
Pipeline processing can be performed in units of each FFT operation stage while avoiding access conflict for the same bank.
FFT calculation can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an FFT operation device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an arrangement of data stored in each memory of FIG.

FIG. 3 is a diagram showing a bank configuration of each memory in FIG.

FIG. 4 is a diagram showing a configuration of a two-input butterfly computing unit.

FIG. 5 is an explanatory diagram of a swap method.

FIG. 6 is a diagram showing a specific example of a method of loading data from the input buffer to the first memory.

FIG. 7 is a diagram showing a specific example of a processing procedure of 16-point FFT calculation according to the present embodiment.

FIG. 8 is a diagram showing a specific example of FFT calculation processing for each FFT calculation stage.

FIG. 9 is a diagram showing a specific example of a swap method.

FIG. 10 is a diagram showing an example of a processing procedure of a conventional 16-point FFT calculation.

FIG. 11 is a diagram showing another example of the processing procedure of the conventional 16-point FFT calculation.

[Explanation of symbols]

1 input buffer 3 data converter 5, 15, 17, 19, 25, 27 Selector 7 First memory 9 Second memory 11 First Address Generator 13 Second address generator 21 Butterfly operation unit 21-1, 21-2 Butterfly computing unit 23 Swap means

Claims (11)

[Claims] 1. A butterfly operation unit, a first storage unit configured by a plurality of banks for storing data processed by the butterfly operation unit, and access to the same bank for reading data from the first storage unit compete with each other. A first address generation unit that generates an address for reading data from the first storage unit so as not to do so, and a rearrangement unit that rearranges the calculation results output from the butterfly calculation unit.
A second storage unit configured of a plurality of banks for storing data output from the rearrangement unit and data for the second storage unit so that access to the same bank does not conflict when writing data to the second storage unit. An FFT operation device, comprising: a second address generation unit that generates a write address. 2. An input buffer for temporarily storing data to be FFT processed, and a data conversion unit for converting the data stored in the input buffer into a predetermined data array set in the first storage unit. The FFT operation device according to claim 1, further comprising: 3. The FFT operation device according to claim 1, wherein the butterfly operation unit is configured by arranging one or a plurality of two-input butterfly operation units in parallel. 4. The FFT according to claim 3, wherein each of the first storage unit and the second storage unit stores two pieces of data which are simultaneously input to the butterfly computing unit at each address. Arithmetic unit. 5. When the butterfly operation unit is configured by arranging one or a plurality of two-input butterfly operation units in parallel, the data conversion unit sets the address to the first storage unit at each address. 3. The FFT operation device according to claim 2, wherein the conversion processing is performed so that two pieces of data that are simultaneously input to the butterfly operation unit are stored. 6. The first storage unit and the second storage unit are each composed of the same number of banks as the number of data simultaneously input to the butterfly operation unit. FFT operation device. 7. The first storage section and the second storage section are composed of two memories, and one of the two memories functions as the first storage section according to an FFT operation stage, and the other of the two memories functions as the first storage section. So that it functions as a second storage unit.
2. The FFT operation device according to claim 1, further comprising switching means for selectively switching the function of each memory. 8. A receiver comprising the FFT operation device according to any one of claims 1 to 7. 9. A wireless communication terminal device comprising the receiving device according to claim 8. 10. A base station device comprising the receiving device according to claim 8. 11. A data read-out device for reading data from the first storage unit so that access to the same bank does not conflict when reading data from the first storage unit which stores data to be processed by a butterfly operation unit and which is composed of a plurality of banks. A first address generation step of generating an address, a rearrangement step of rearranging the operation results output from the butterfly operation unit, and a second memory configured of a plurality of banks and storing the data output in the rearrangement step. A second address generating step of generating an address for writing data to the second storage unit so that access to the same bank does not conflict when writing data to the unit.