JP2003150461A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2003150461A5 JP2003150461A5 JP2001351707A JP2001351707A JP2003150461A5 JP 2003150461 A5 JP2003150461 A5 JP 2003150461A5 JP 2001351707 A JP2001351707 A JP 2001351707A JP 2001351707 A JP2001351707 A JP 2001351707A JP 2003150461 A5 JP2003150461 A5 JP 2003150461A5
- Authority
- JP
- Japan
- Prior art keywords
- arbitration circuit
- verification method
- request signal
- output
- virtual master
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 claims 3
- 238000012795 verification Methods 0.000 claims 3
Claims (2)
前記調停回路に、前記複数のマスター回路に代えて、任意のタイミングで起動して設定された間隔で要求信号を出力する複数の仮想マスターモデルを接続し、
前記複数の仮想マスターモデルからそれぞれ所定のタイミングで要求信号を出力させ、
前記調停回路の動作を検証することを特徴とした調停回路検証手法。 In an arbitration circuit verification method for logically verifying the operation of an arbitration circuit that arbitrates a request signal output after processing input data from each of a plurality of master circuits,
In place of the plurality of master circuits, the arbitration circuit is connected to a plurality of virtual master models that start at arbitrary timing and output request signals at set intervals,
A request signal is output at a predetermined timing from each of the plurality of virtual master models,
An arbitration circuit verification method characterized by verifying the operation of the arbitration circuit.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001351707A JP2003150461A (en) | 2001-11-16 | 2001-11-16 | Arbitration circuit verifying procedure |
| US10/291,508 US7548841B2 (en) | 2001-11-16 | 2002-11-12 | Method for logic checking to check operation of circuit to be connected to bus |
| US12/432,394 US8112263B2 (en) | 2001-11-16 | 2009-04-29 | Method for logic checking to check operation of circuit to be connected to bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001351707A JP2003150461A (en) | 2001-11-16 | 2001-11-16 | Arbitration circuit verifying procedure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003150461A JP2003150461A (en) | 2003-05-23 |
| JP2003150461A5 true JP2003150461A5 (en) | 2005-07-14 |
Family
ID=19163984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001351707A Withdrawn JP2003150461A (en) | 2001-11-16 | 2001-11-16 | Arbitration circuit verifying procedure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003150461A (en) |
-
2001
- 2001-11-16 JP JP2001351707A patent/JP2003150461A/en not_active Withdrawn
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2004511026A5 (en) | ||
| KR19980032933A (en) | Method and apparatus for design verification using emulation and simulation | |
| US7296175B2 (en) | System on a chip bus with automatic pipeline stage insertion for timing closure | |
| JP2002123483A5 (en) | ||
| TW451126B (en) | Computer element integrated testing system with software simulation | |
| JP2008282314A (en) | Simulator and simulation method | |
| JP2003150461A5 (en) | ||
| JP5347482B2 (en) | Performance evaluation apparatus, performance evaluation method, and simulation program | |
| JP4988411B2 (en) | Method and apparatus for reading data from a serial data source in a parallel format | |
| JP5383159B2 (en) | Bus relay apparatus and control method | |
| JP2002049579A (en) | Device and method for managing processor local bus and computer program product | |
| Prasad et al. | Development of VIP for AMBA AXI-4.0 Protocol | |
| JP2007525114A5 (en) | ||
| JP2003281075A (en) | Direct memory access controller, direct memory access device and requesting device | |
| JP2006127381A (en) | Arbitration circuit verification method | |
| JP2000298638A5 (en) | ||
| JP2003150461A (en) | Arbitration circuit verifying procedure | |
| JP2921087B2 (en) | Real Chip Simulation Method for Hardware Accelerator | |
| JP2004157646A (en) | Verification device for integrated circuit, verification method, and generation method for interface model for verifying integrated circuit | |
| JPH10187595A (en) | Bus bridge | |
| JPH04336360A (en) | Circuit and method for access to dmac | |
| JP2007188214A (en) | Semiconductor integrated circuit device | |
| JP2739783B2 (en) | Data transfer method between packages | |
| JPS6267653A (en) | Bus control system | |
| JP2002197056A (en) | Interface circuit for chip for network and access timing adjustment method |