JP2002197056A - Interface circuit for chip for network and access timing adjustment method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interface circuit for a chip for a network and an access timing adjustment method which enable an external processor to securely access the chip for the network. SOLUTION: A LonWorks controller 5 is a chip which manages a communication through the network 1. A general purpose CPU 6 performs data communication between the LonWorks controller 5 to process data from electronic equipment 4 and also controls the electronic equipment 4 according to the data from server equipment. In such a case, the general purpose CPU 6 is unable to directly access the LonWorks controller 5 because of a different in the effective timing of a control signal, and hence a parallel interface circuit 7 adjusts the effective timing of the control signal. Consequently, the general purpose CPU 6 becomes able to access the LonWorks controller 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network chip interface circuit for connecting a network chip to an external processor and an access timing adjusting method.

[0002]

2. Description of the Related Art Conventionally, a centralized system has been used as, for example, a building automation system or a home network control system, and a host computer controls various actuators by monitoring operation states of various sensors through a network. I was

[0003]

In such a centralized system, a host computer and various devices have to be connected, enormous wiring is required, initial construction costs are extremely high, and system changes are required. Is difficult. Further, since the networks are constructed according to the standards unique to each company, the networks cannot be connected to each other and there is no scalability.

Therefore, in recent years, as a means for solving such a problem, LON (Local Operating Network) has been proposed.
) Technology is being provided. This LON technology is to construct an intelligent distributed network by using a network chip developed by Echelon of the United States. It is possible to construct a system at low cost and shorten the system development period. , And has an excellent feature of being excellent in expandability. In addition, since the network chip is equipped with communication firmware, the user can perform data communication through the network without being aware of the communication protocol in the application, and can easily develop the application. As well as high communication capability.

[0005] By the way, although the network chip is configured to be connectable to various electronic devices, the number of connectable electronic devices is small, the capacity of the application memory is small, and the operation speed is slow. Humans are considering connecting an external processor to the network chip, inputting the operating state of the sensor by an application mounted on the external processor, and controlling the actuator.

However, since the valid timing of the control signal including the address signal is defined in the network chip based on the chip select signal, the chip select signal for the network chip is generated based on the address signal. At the timing when the chip select signal ends, the address signal ends, and there is a problem that the external processor cannot access the network chip.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide an interface circuit and an access timing adjustment method for a network chip which enable an external processor to reliably access the network chip. Is to do.

[0008]

According to the present invention, the external processor outputs a control signal such as an address signal when accessing the network chip.
In this case, since the valid timing of the control signal including the address signal is defined based on the chip select signal, the network chip generates the chip select signal for the network chip based on the address signal from the external processor. However, the valid timing of the address signal has ended at the end timing of the chip select signal, and the external processor cannot access the network chip.

Here, the timing adjustment means supplies the control signal output from the external processor to the network chip in a state where the control signal is adjusted so that the chip select signal becomes a reference, so that the external processor accesses the network chip. Data can be written and data can be read.

According to the second aspect of the present invention, since the timing adjusting means is a delay circuit for delaying an input signal based on a clock signal from an external processor, it is possible to accurately adjust the timing of a control signal from the external processor. Can be.

According to the third aspect of the present invention, since the external processor can adjust the output timing of the control signal by the program, it is necessary to adjust the effective timing of the control signal output from the external processor by hardware. And can be easily implemented.

According to the fourth aspect of the present invention, the network chip adjusts the output timing of the control signal using the PCMCIA interface function, so that it can be programmed in the same manner as when accessing the PCMCIA interface of the network chip. It can be easily implemented.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment A first embodiment of the present invention will be described below with reference to FIGS. FIG. 2 shows the entire system. In FIG. 2, a network 1 is constructed in a building, and various devices 2 such as lighting or air conditioning equipment are connected to the network 1 via a network controller 3.

FIG. 1 schematically shows the configuration of the network controller 3. In FIG. 1, a network controller 3 processes data from electronic devices (corresponding to client devices) 4 such as sensors included in various devices 2 and transmits the processed data to a server device via the network 1 or a server device via the network 1. The electronic device 4 such as a motor is driven on the basis of the data from the computer.

The network controller 3 has an L
An onWorks (trade name) controller (corresponding to a network chip) 5 and a general-purpose CPU (corresponding to an external processor) 6.

The LonWorks controller 5 has firmware for executing communication with the network 1 and does not need to be aware of the communication protocol in the application, so that the application can be easily manufactured. In this case, the LonWorks controller 5 independently controls the electronic device 4 depending on the application.
Although it is possible to process data from and to control the electronic device 4, the number of connectable electronic devices is small, the capacity of the application memory is small, and the operation speed is slow.
The general-purpose CPU 6 is connected to the ks controller 5, and the general-purpose CPU 6 processes data from the electronic device 4 to obtain Lo.
nWorks controller 5 or LonWo
The electronic device 4 is controlled based on data from the rks controller 5.

As the general-purpose CPU 6, a general-purpose CPU 6 is used. Also, LonWor
The ks controller 5 is sold by Echelon Corporation of the United States, and by using this, the intelligent distributed network 1 can be constructed. In this case, the LonWorks controller 5 is a general-purpose CPU.
6 address spaces.

The general-purpose CPU 6 has terminals A15 to A0,
S (address strobe) terminal, CLK (clock) terminal, ~ RD (read) terminal, ~ WR (write) terminal, D
7 to D0 are provided. Note that ~ AS, ~ RD, ~ W
R indicates low active, and so on.

FIG. 3 shows the timing of the read / write cycle of the general-purpose CPU 6 described above. In FIG. 3, the general-purpose CPU 6 defines output timings of various signals based on the E clock as follows. (A) A15 to A0... Output in response to the rising timing of the E clock in the T1 state, and stop according to the elapse of a set time from the rising timing of the AS signal.

(B)-AS signal... AS signal is output after a lapse of a set time from the output timing of the address signal, and is stopped according to the falling timing of the E clock in the T3 state. (C) to RD signal (during reading): output after a lapse of a set time from the output timing of the address signal, and stop when the T3 state ends. (D) D7 to D0 (during read): output after a lapse of a set time from the output timing of the address signal, and stop when the T3 state ends.

(E) to WR signal (at the time of writing): output in response to the rising timing of the E clock in the T2 state, and stopped in response to the falling timing of the E clock in the T3 state. (F) D7 to D0 (during writing): output in accordance with the falling timing of the E clock in the T1 state.
It stops after the set time has passed since the stop of the WR signal.

FIG. 4 shows signal terminals of the LonWorks controller 5. In FIG. 4, LonWo
The rks controller 5 has a plurality of modes, and in the present embodiment, the general-purpose CPU 6 uses the LonWorks controller 5 in the slave B mode in which it accesses the memory in the same manner as a memory.

More specifically, the LonWorks controller 5 is provided with IO0 to IO10 pins.
Pin 0 is an input / output terminal that also serves as D0 (0 bit of the data bus) and HS (handshake), IO1 to IO7 are input / output terminals of D1 to D7, IO8 is an input terminal of a CS signal, and IO9 is an R / to Input terminal of W signal, IO10 is A0
Input terminal for signal (0 bit of address bus). Here, HS is the least significant bit of the control register of the LonWorks controller 5 and is used as a busy signal for notifying the general-purpose CPU 6 that the LonWorks controller 5 is in use. In this case, the LonWorks controller 5 executes input / output of data through the data bus. A0 functions as a signal for the general-purpose CPU 6 to instruct the LonWorks controller 5 to output either the data register or the control register of the LonWorks controller 5 to the data bus.

FIG. 5 shows the read / write timing (general purpose CPU) specified in the LonWorks controller 5.
6 of the data write / read timing). In FIG. 5, the timings of the signals defined by the LonWorks controller 5 are as follows.
It is defined based on the falling edge timing and the rising edge timing of the CS signal.

(A) The setup time of A0 before the falling edge of the CS signal is 10 ns or more. (B) The hold time of A0 after the rising edge of the CS signal is 0 ns or more. (C) The falling edge of the CS signal. The setup time of R / ~ W before is 0 ns or more. (D) The hold time of R / ~ W after the rising edge of the CS signal is 0 ns or more. (E) ~ The output data from the falling edge of the CS signal. Read data) is valid until 5
0 ns or less (f)-Hold time of output data from rising edge of CS signal is 0 ns or more (g)-Setup time of input data (write data of general-purpose CPU 6) before rising edge of CS signal is 25 n
(h)-Hold time of input data after rising edge of CS signal is 5 ns or more

As described above, the general-purpose CPU 6 defines the effective timing of various control signals (address signal / read / write signal, etc.) based on the output timing of the E clock, whereas the LonWorks controller 5 Since the timing is defined based on the signals CS to CS, the timings of the two are different in the following points.

(A) Since the time specified by the LonWorks controller 5 is not specified by the general-purpose CPU 6, the timings of the two cannot be directly matched. This means that the general-purpose CPU 6
This means that the rks controller 5 cannot be directly accessed.

(B) Since the general-purpose CPU 6 is not configured to output the CS signal, it is necessary to generate the CS signal based on the address signal of the general-purpose CPU 6; however, it is generated based on the address signal. When the valid timing of the CS signal ends, the valid period of the address signal has already ended, and the hold time of A0 after the rise of the CS signal defined by the LonWorks controller 5 cannot be secured.

Accordingly, the general-purpose CPU 6 sends the LonWork
Even if an attempt is made to access the s-controller 5, the general-purpose CPU 6 cannot be accessed due to the mismatch of the timing of the control signal.
An interface circuit for enabling access to the ks controller 5 is provided.

That is, as shown in FIG.
The onWorks controller 5 is connected via the parallel interface circuit 7. The parallel interface circuit 7 includes an address recorder 8, a first delay circuit (corresponding to timing adjustment means) 9, a NAND circuit 10, and a second delay circuit (corresponding to timing adjustment means) 1.
1, a chip select signal output switching circuit 12, a read / write state determination circuit 13, an inverter circuit 14, a NAND circuit 15, a transfer gate circuit 16, and a third delay circuit (corresponding to timing adjustment means) 17, The function of each circuit is as follows.

(A) Address recorder 8... The address signals A15 to A12 match the address data set therein, and output a high-level signal during the input of the AS signal. (B) First delay circuit 9...-Delays the AS signal by one period of the E clock.

(C) NAND circuit 10... Outputs a write-use CS signal when all of the inputs are at a high level. (D) Second delay circuit 11... The read-use CS signal is output by delaying the write-use CS signal by 周期 cycle of the E clock. (E) Chip select signal output switching circuit 12 ... R / ~
When the W input signal is at a low level,
A CS signal is output, and when the signal is at a high level, the input read CS signal is output.

(F) Read / write state determination circuit 13
.. Output a high-level signal when a RD signal is input, and output a low-level signal when a WR signal is input. (G) Inverter circuit 14... W obtained by inverting the WR signal
Outputs an R signal. (H) NAND circuit 15 Normally, a high-level signal is output, the output state of the high-level signal is maintained when the 〜RD signal is input, and the low-level signal is output when the WR signal is input. That is, from the general-purpose CPU 6 to ~ W
When the R signal is output, the .about.WR signal is output as it is, so that the R / .about.WR signal is eventually output.

(I) Transfer gate circuit 16... The R / .about.W signal from the NAND circuit 15 is passed only during the period when the high level signal is output from the address recorder 8. (J) Third delay circuit 17: A0 is set to 1 / E clock
Delay by two cycles.

Next, the operation of the above configuration will be described. FIG. 6 shows the timing at which the general-purpose CPU 6 writes data to the LonWorks controller 5. In FIG. 6, the general-purpose CPU 6 outputs an address signal for accessing the LonWorks controller 5 in response to the rising edge of the E clock in the T1 state, and then outputs an AS signal after a lapse of a set time. As a result, the address recorder 8 outputs a high-level signal synchronized with the signal AS as shown in FIG.

Subsequently, the general-purpose CPU 6 outputs data in response to the falling edge of the E clock in the T1 state, and then outputs the signal 信号 WR in response to the rising edge of the E clock in the T2 state.

The LonWorks by the general-purpose CPU 6
When writing data to the controller 5, A
Since 0 does not become a high level, A0 is not supplied to the LonWorks controller 5 from the third delay circuit 17.

Therefore, the LonWorks controller 5
In response to the falling edge of the WR signal, the / WE signal is input and the CS signal is input, so the LonWorks controller 5 sets the D7 to D at the rising timing of the CS signal.
Data can be input from 0.

On the other hand, FIG. 7 shows that the general-purpose CPU 6 is LonWor.
The timing at which data is read from the ks controller 5 is shown. In FIG. 7, the general-purpose CPU 6 outputs an address signal and an AS signal at a predetermined timing in the same manner as when writing data, and outputs the E signal in the T1 state.
After outputting the ~ RD signal in response to the falling edge of the clock,
After a lapse of a set time from the output timing of the address signal, D
7 to D0 are output.

Here, since the second delay circuit 11 outputs the read-use CS signal by delaying it by a half cycle of the E clock, the second delay circuit 11 outputs Lo signal compared to the above-described data write operation.
The -CS signal applied to the nWorks controller 5 is delayed. The third delay circuit 17 receives the input A0
Is delayed by a half cycle of the E clock.

By the above operation, the input state of A0 can be maintained at the timing when the input of the ~ CS signal to the LonWorks controller 5 is stopped, so that the general-purpose CPU 6 can read data from the LonWorks controller 5. .

According to such an embodiment, the general-purpose CP
When the U6 accesses the LonWorks controller 5, the parallel interface circuit 7 for adjusting the valid timing of the control signal output from the general-purpose CPU 6 to the valid timing of the control signal of the LonWorks controller 5 is provided.
By accessing the orks controller 5, data writing or reading can be performed reliably.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. 8 to 11. The same reference numerals are used for the same parts as the first embodiment. The description is omitted here, and different parts will be described. In the second embodiment, the timing adjustment of the control signal performed by the parallel interface circuit in the first embodiment is performed by P.
The present invention is characterized by being implemented by a program by a CPU having a CMCIA interface. The CPU used in the present embodiment has a PCMCIA interface function.

FIG. 8 shows the connection between the CPU and the LonWorks controller. In FIG. 8, the CPU
Reference numeral 21 has a built-in decoding circuit, and outputs a ~ CS signal from the ~ CS terminal when the address becomes a predetermined address. To CS terminals are connected to the input terminals of a negative logic AND circuit 22, and the output terminal of the AND circuit 22 is Lon
It is connected to the ~ CS terminals of the Works controller 5. The RD terminal and the WR terminal of the CPU 21 are connected to the input terminal of the OR circuit 23 of negative logic, and the output terminal is connected to the input terminal of the AND circuit 22. And C
The R / ~ W terminal, D7 ~ D0 terminal and A0 terminal of PU21 are the R / ~ W terminal of LonWorks controller 5, D7
ＤD0 terminal and A0 terminal.

Although not shown in FIG. 8, the CPU 2
1 and the LonWorks controller 5 have different operating voltages, so the CPU 21 and the LonWorks controller 5 have R / -W terminals, D7-D0 terminals, A0
A buffer is provided between the terminals.

Here, the CPU 21 does not have a PCM (not shown).
A CIA control register is provided. This P
The CCMIA control register is originally a CPU 21
~ R for PCMCIA interface connected to
The PCMC is provided for defining the assert / negative timing of the D signal and the WR signal.
By setting and resetting a specific bit of the IA control register, the delay time from when the address signal is effectively output to when the ~ RD signal or ~ WE signal is asserted and the ~ RD signal or ~ WE signal are negated. Address hold time can be set.

FIG. 9 shows a timing chart when the CPU 21 accesses the LonWorks controller 5. In FIG. 9, the CPU 21 asserts the RD signal or the WR signal when the CKIO is output at 1.5 clocks from the rising timing (output timing of the address signal) of the CKIO in the T1 state, and also asserts the CKIO in the T2 state. It is programmed to hold the address signal from the fall timing (the negation timing of the RD signal or the WE signal) until 2.5 clocks of CKIO are output.

In FIG. 9, the signal 〜RD or the signal ＷW
The reason why the CKIO waits for one clock output after the assertion of the R signal is that the assertion time of the CS signal is L
This is for extending the on-works controller 5 so as to satisfy the regulations.

FIG. 10 shows the timing at which the CPU 21 writes data to the LonWorks controller 5, and FIG.
Reference numeral 1 denotes a timing at which the CPU 21 reads data from the LonWorks controller 5, and the valid timing of a control signal given from the CPU 21 to the LonWorks controller 5 is
It is understood that the requirements of the above are satisfied.

According to such an embodiment, the CPU 2
1 can adjust the effective timing of the control signal when accessing the LonWorks controller 5 by a program so as to satisfy the regulations of the LonWorks controller 5, without providing an interface circuit unlike the first embodiment. It can be easily implemented and cost can be reduced.

The present invention is not limited to the above embodiments, and the parallel interface circuit in the first embodiment may be made into a custom IC. In this case, the embedded design of the LonWorks controller can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a parallel interface circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a network system.

FIG. 3 is a timing chart showing the operation of a CPU;

FIG. 4 is a diagram showing signal terminals of a LonWorks controller;

FIG. 5 is a timing chart showing the operation of the LonWorks controller.

FIG. 6 is a timing chart when the CPU writes data to the LonWorks controller;

FIG. 7 is a timing chart when the CPU reads data from the LonWorks controller;

FIG. 8 is a diagram corresponding to FIG. 1 in a second embodiment of the present invention.

FIG. 9 is a diagram corresponding to FIG. 3;

FIG. 10 is a diagram corresponding to FIG. 4;

FIG. 11 is a diagram corresponding to FIG. 5;

[Explanation of symbols]

1 is a network, 3 is a network controller,
4 is an electronic device (client device), 5 is LonWor
A ks controller (network chip), 6 is a general-purpose CPU (external processor), 7 is a parallel interface circuit, 9, 11, and 17 are delay circuits (timing adjusting means), and 21 is a CPU (external processor).

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideki Hokimoto 1-1-1, Showa-cho, Kariya-shi, Aichi Prefecture Inside Denso Co., Ltd. (72) Inventor Hiroyuki Tanaka 50 Kojiri, Hittsugi-cho, Kariya-shi, Aichi Denso Elex Co., Ltd. F-term (reference) 5B077 GG02 GG15 GG16 MM01 MM02

Claims (4)

[Claims] 1. A network chip connected to a network and in which the valid timing of a control signal including an address signal is defined based on a chip select signal, and a network chip connected to the network chip and accessing the network chip. And an external processor for executing control of the client device by the server device. The timing adjustment for adjusting the effective timing of the control signal output from the external processor and given to the network chip so that the chip select signal becomes a reference. An interface circuit for a network chip, characterized by comprising means. 2. The interface circuit according to claim 1, wherein said timing adjustment means is a delay circuit for delaying a control signal based on a clock signal from said external processor. 3. A network chip connected to a network and in which the valid timing of a control signal including an address signal is defined based on a chip select signal; and a network chip connected to the network chip and accessing the network chip. And an external processor that executes control of the client device by the server device, wherein the external processor is programmed to adjust the output timing of the control signal so as to access the network chip. For adjusting the access timing of the chip 4. The method according to claim 3, wherein the external processor adjusts the output timing of the control signal using a PCMCIA interface function.