JP2003142497A - Method for manufacturing thin film transistor array and method for manufacturing liquid crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance characteristics by compensating the unbonding hand of the polysilicon thin film of a thin film transistor constituting a thin film transistor array, and to enhance productivity by shortening a manufacturing. SOLUTION: An insulator polysilicon thin film 13 is formed on a glass substrate 11. After a gate insulation film 14 and a gate electrode 15 are formed, the polysilicon thin film 13 is implanted with phosphorous ions for forming a source-drain region. A large quantity of hydrogen ions is implanted into the gate electrode 15 becoming a mask and the gate insulation film 14 by acceleration implanting plasma decomposed ions of phosphorus diluted with hydrogen by a ion doping method without performing mass separation. Following to the formation of an interlayer insulation film 18 and respective electrodes, a silicon nitride film is formed as a protective insulation film 22. When annealing is performed subsequently in a hydrogen atmosphere, hydrogen in the gate electrode 15 and the gate insulation film 14 is diffused into the polysilicon thin film 13, thus compensating the unbonding hand.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor array and a method of manufacturing a liquid crystal display device, which are used in an active matrix type liquid crystal display device or the like and which use a polycrystalline silicon thin film as an active layer of a thin film transistor. .

[0002]

2. Description of the Related Art In recent years, in a liquid crystal display device and an image sensor in which thin film transistors are integrated, there is a strong demand for cost reduction as well as a trend of high density. From
The development of thin film transistors using a polycrystalline silicon thin film as an active layer has been activated. The polycrystalline silicon thin film transistor has an electron mobility higher than that of an amorphous silicon thin film transistor by two digits or more, and has advantages such as miniaturization of elements and integration of a driving circuit on the same substrate.

A conventional method of manufacturing a thin film transistor will be described below with reference to FIG. 4A to 4C are process sectional views showing a conventional method of manufacturing a thin film transistor, and here, a process sectional view of one pixel portion of a top gate type polycrystalline silicon thin film transistor array used in an active matrix type liquid crystal display device is shown.

First, as shown in FIG. 4A, a polycrystalline silicon thin film 13 is formed on a transparent substrate 11 such as a glass substrate, the polycrystalline silicon thin film 13 is processed into an island shape, and then silicon oxide is formed. A gate insulating film 14 made of a film is formed. Next, the gate electrode 15 is formed on the gate insulating film 14. After that, ion implantation of impurities is performed to form the source / drain regions, and the introduced impurities are activated.

Next, as shown in FIG. 4B, an interlayer insulating film 18 made of a silicon oxide film is formed, and the interlayer insulating film 18 on the source / drain regions is partially removed to form a contact hole 19. Open. Then, dangling bonds in the polycrystalline silicon thin film 13 of the active layer
Hydrogen plasma treatment is performed to compensate for the above and improve the characteristics of the thin film transistor.

After the hydrogen plasma treatment, as shown in FIG. 4C, the display electrode 2 made of an ITO (Indium Tin oxide) film is formed.
0a and drain electrode 20b are formed. Then T
The source electrode wiring 21 made of a laminated film of an i film and an Al film is formed.

Next, as shown in FIG. 4D, a protective insulating film 22 made of a silicon nitride film is formed to complete the thin film transistor. After that, although not shown, part of the protective insulating film 22 is removed so as to open on the pixel electrode 20a, and the thin film transistor array of the liquid crystal display device is completed.

In this conventional manufacturing method, when a large number of dangling bonds are included in the polycrystalline silicon thin film 13 of the active layer, the dangling bonds generate a level between the valence band and the conduction band of silicon. However, in order to deteriorate the characteristics of the thin film transistor, a general hydrogen plasma treatment is performed as a method of compensating dangling bonds in the polycrystalline silicon thin film 13.

The hydrogen in which the dangling bonds of the polycrystalline silicon thin film 13 are compensated by this hydrogen plasma treatment is desorbed again by the heat treatment at 400 ° C. or higher. Therefore, in the hydrogen plasma treatment step, the activation treatment after the impurity implantation is performed. It must be carried out after the high temperature process.

Further, since the silicon nitride film which is the protective insulating film 22 has a low hydrogen permeability, when hydrogen plasma treatment is performed after the protective insulating film 22 is formed, hydrogen radicals in the plasma are diffused in the silicon nitride. Since the coefficient is small and the hydrogen plasma treatment process takes a lot of time, the hydrogen plasma treatment must be performed before the formation of the protective insulating film 22.

Further, when used in a thin film transistor array of a liquid crystal display device as shown in FIG. 4, the display electrode 20a is used.
If the hydrogen plasma treatment is performed in a state where the ITO film to be formed is exposed, the surface of the ITO film is reduced and blackened. Therefore, the hydrogen plasma treatment process must be performed before the formation of the ITO film.

[0012]

In the above conventional manufacturing method, the polycrystalline silicon thin film 13 is formed by hydrogen plasma treatment.
Compensating the dangling bonds in the inside to improve the characteristics of the thin film transistor, but the hydrogen plasma treatment requires several hours to several tens of hours until the thin film transistor characteristics are stabilized,
In the manufacturing process of the thin film transistor, the processing time is extremely long, which is the biggest factor for lowering the throughput.

Further, in general, a parallel plate type plasma apparatus is often used for hydrogen plasma processing, but it is difficult for the parallel plate type plasma apparatus to cope with a batch system, and the processing time per sheet is shortened. Is difficult.

Thus, in the conventional manufacturing method for improving the characteristics of the thin film transistor by using the hydrogen plasma treatment,
There is a problem that the manufacturing time becomes long and the productivity is low.

An object of the present invention is to improve the characteristics by compensating for dangling bonds of a polycrystalline silicon thin film of a thin film transistor, shortening the manufacturing time, and improving the productivity, and a liquid crystal display. A method of manufacturing a display device is provided.

[0016]

A method of manufacturing a thin film transistor array according to claim 1, wherein a polycrystalline silicon thin film forming step of forming a polycrystalline silicon thin film on a transparent substrate, and a gate on the polycrystalline silicon thin film. Gate insulating film forming step of forming an insulating film, gate electrode forming step of forming a gate electrode on the gate insulating film, hydrogen introducing step of introducing hydrogen into the gate insulating film and the gate electrode, gate insulating film and gate electrode An interlayer insulating film forming step of forming an interlayer insulating film thereon, a display electrode forming step of forming a display electrode connected to the polycrystalline silicon thin film, and a protective insulating film forming step of forming a protective insulating film that covers at least the display electrode. And a heat treatment step of diffusing hydrogen introduced into the gate insulating film and the gate electrode into the polycrystalline silicon thin film after the protective insulating film forming step.

According to this manufacturing method, hydrogen is introduced into the gate insulating film and the gate electrode and is diffused into the polycrystalline silicon thin film by heat treatment to compensate dangling bonds in the channel region of the polycrystalline silicon thin film. The necessary hydrogen diffusion distance can be shortened and the hydrogenation efficiency can be improved.
In addition, the heat treatment for diffusing hydrogen takes only about 2 hours as compared with the conventional hydrogen plasma treatment which required several hours to ten and several hours, and the manufacturing time can be shortened and the productivity can be improved. In this way, the unbonded hands of the polycrystalline silicon thin film of the thin film transistor are compensated to improve the characteristics,
Manufacturing time can be shortened and productivity can be improved.

A method of manufacturing a thin film transistor array according to a second aspect is the method of manufacturing a thin film transistor array according to the first aspect, wherein the protective insulating film is a silicon nitride film. Since the silicon nitride film has a low hydrogen permeability, by using the silicon nitride film as the protective insulating film in this way, hydrogen hardly diffuses into the protective insulating film and diffuses toward the polycrystalline silicon thin film. The hydrogenation efficiency can be improved.

A method of manufacturing a thin film transistor array according to a third aspect is the method of manufacturing a thin film transistor array according to the second aspect, wherein the silicon nitride film is plasma CV using a mixed gas of hydrogen, nitrogen, ammonia and silane.
It is formed by the D method. Since the silicon nitride film formed by such a plasma CVD method contains a large amount of hydrogen in the film, it becomes more difficult for hydrogen to diffuse to the protective insulating film, and to the polycrystalline silicon thin film. Since it diffuses, the hydrogenation efficiency can be further improved.

A method of manufacturing a thin film transistor array according to a fourth aspect is the method of manufacturing a thin film transistor array according to any one of the first to third aspects, wherein the heat treatment temperature in the heat treatment step is 300 ° C. or higher and 500 ° C. or lower. This heat treatment temperature can further improve the hydrogenation efficiency.

A method of manufacturing a thin film transistor array according to a fifth aspect is the method of manufacturing a thin film transistor array according to any one of the first to fourth aspects, wherein the heat treatment step is performed in an atmosphere containing at least one of hydrogen and nitrogen.

The method of manufacturing a thin film transistor array according to claim 6 is the method of manufacturing a thin film transistor array according to any one of claims 1 to 5, further comprising an impurity introducing step of introducing an impurity into the polycrystalline silicon thin film. In the introducing step, the ions formed by plasma decomposition of the impurity hydrogen dilution gas are injected without mass separation.
Thereby, the impurity introduction step and the hydrogen introduction step to the gate insulating film and the gate electrode can be performed at the same time, and the manufacturing time can be further shortened and the productivity can be further improved.

The method of manufacturing a thin film transistor array according to claim 7 is the method of manufacturing a thin film transistor array according to any one of claims 1 to 6, wherein the step of introducing hydrogen comprises:
Hydrogen is introduced so that the hydrogen concentration of at least one of the gate insulating film and the gate electrode is 10 ¹⁹ cm ⁻³ or more. As a result, hydrogen sufficient to compensate dangling bonds in the polycrystalline silicon thin film is introduced into the gate insulating film and the gate electrode.

The method of manufacturing a thin film transistor array according to claim 8 is the method of manufacturing a thin film transistor array according to any one of claims 1 to 7, wherein the gate insulating film is
It is a laminated film in which a silicon oxide film formed by an atmospheric pressure CVD method or a plasma CVD method and a silicon nitride film formed by a plasma CVD method or a tantalum oxide film formed by a sputtering method are laminated. It is formed so as to be in contact with the polycrystalline silicon thin film. Since the silicon oxide film and the silicon nitride film thus formed by the plasma CVD method contain a large amount of hydrogen in the film, the dangling bonds of the polycrystalline silicon thin film are more effectively compensated and the hydrogenation efficiency is improved. can do.

A method of manufacturing a liquid crystal display device according to a ninth aspect comprises the method of manufacturing a thin film transistor array according to any one of the first to eighth aspects.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. FIG. 1 is a process cross-sectional view showing a method of manufacturing a thin film transistor according to an embodiment of the present invention. Here, as in the conventional example, one of a top gate type polycrystalline silicon thin film transistor array used in an active matrix type liquid crystal display device is shown. 7A to 7C are process cross-sectional views of a pixel portion.

First, as shown in FIG. 1A, a silicon oxide film serving as a buffer layer 12 is formed on a glass substrate 11 which is a translucent substrate in a thickness of 3000 liters. This buffer layer 12
Amorphous silicon (a-S
i) Deposit 850Å thin film. Then, in order to reduce hydrogen in the a-Si thin film, heat treatment is performed at 450 ° C. for 90 minutes in a reduced pressure nitrogen atmosphere of 133 Pa (1 Torr). After this heat treatment, the a-Si thin film is crystallized by excimer laser annealing to form a polycrystalline silicon thin film 13. The XeCl excimer laser having a wavelength of 308 nm is used for the excimer laser annealing, the irradiation is performed in a vacuum, and the energy density is 260 mJ / cm ² in the first step and 390 mJ / c in the second step.
Crystallization was performed by two-step irradiation of m ² . The average irradiation number is 16 shot / point in both the first and second steps.

After the a-Si thin film is crystallized to form the polycrystalline silicon thin film 13 in this manner, the polycrystalline silicon thin film 13 is processed into an island shape, and then a silicon oxide film to be the gate insulating film 14 is formed at 850 Å. Form. The silicon oxide film (gate insulating film 14) is formed at a substrate temperature of 4 by an atmospheric pressure CVD method using a mixed gas of silane (SiH ₄ ) and oxygen.
Formed at 50 ° C. The formation temperature of the gate insulating film 14 is the maximum temperature in this process. Gate insulating film 14
After the formation of Al, the Al-Zr alloy (Zr concentration 10%) is added to 300
0 Å is deposited and processed into the shape of the gate electrode 15.

After forming the gate electrode 15 with an Al--Zr alloy, phosphorus ions are implanted using the gate electrode 15 as a mask to form source / drain regions in the polycrystalline silicon thin film 13. An ion doping method is used for this phosphorus ion implantation, and phosphine (PH ₃ ) containing 10% hydrogen is used.
What was decomposed and ionized by high frequency plasma was injected at an acceleration voltage of 80 kV and a dose of 1 × 10 ¹⁵ cm ^-2 . In the ion doping method, ions obtained by decomposing phosphine (PH ₃ ) having a hydrogen content of 10% by high-frequency plasma are accelerated and injected without mass separation, so that hydrogen (H _x ; x = 1, 2) ions and hydrogenated phosphorus (PH _x ; x = 1 to 3) ions are simultaneously generated and injected. In addition to the source / drain regions of the thin film transistor, H _x (x = 1, 2) is similarly formed in the gate electrode 15 and the gate insulating film 14 serving as a mask.
Ions and PH _x (x = 0 to 3) ions are implanted, but since hydrogen ions have a smaller mass number than phosphorus ions, they are implanted to a deeper region when they are implanted at the same acceleration voltage. Then, a large amount of hydrogen ions are implanted into the lower portion of the gate electrode 15 and the gate insulating film 14.

After the impurity implantation, as shown in FIG.
An interlayer insulating film 18 made of a 4000 Å silicon oxide film is formed. The interlayer insulating film 18 is formed by atmospheric pressure CVD using a mixed gas of silane (SiH ₄ ) and oxygen at a substrate temperature of 40.
Formed at 0 ° C. When the interlayer insulating film 18 is formed, 4
Since a thermal history of about 30 minutes at 00 ° C. is added, the activation process of the phosphorus ions previously implanted is simultaneously performed by this thermal process. After the interlayer insulating film 18 is formed, the interlayer insulating film 18 on the source / drain regions is partially removed to open a contact hole 19.

Next, as shown in FIG. 1C, ITO
The pixel electrode 20a and the drain electrode 20b which are display electrodes made of a film are formed, and then the source electrode wiring 21 made of a laminated film of a Ti film of 1000 Å and an Al film of 7000 Å is formed.

Next, as shown in FIG. 1 (d), hydrogen,
A silicon nitride film is formed by a plasma CVD method using a mixed gas of nitrogen, ammonia, and silane to form the protective insulating film 22. After that, hydrogen atmosphere (133 Pa (1To
rr)) at 350 ° C. for 120 minutes,
The thin film transistor is completed. After that, although not shown, the protective insulating film 2 is formed so as to open above the pixel electrode 20a.
By removing a part of 2, the thin film transistor array of the liquid crystal display device is completed.

FIG. 2 shows the gate electrode 15 / after the phosphorus ions are implanted into the source / drain regions by the ion doping method.
It is the result of measuring the hydrogen concentration in the gate insulating film 14 / polycrystalline silicon thin film 13 by the secondary ion mass spectrometry (SIMS), and shows the hydrogen concentration on the line AB in FIG.

As in this embodiment, by ion-implanting a 10% hydrogen-based phosphine (PH ₃ ) plasma-decomposed ion without mass separation, as shown in FIG. The hydrogen concentration in the gate insulating film 14 or the gate electrode 15 after doping becomes 10 ²⁰ cm ⁻³ or more.

When the ion implantation method is used for the impurity implantation, the impurities other than the predetermined ions are not implanted into the gate electrode 15 and the gate insulating film 14 because the implanted impurities are separated by mass. When the ion doping method is used as in this embodiment, a large amount of hydrogen ions other than predetermined ions (phosphorus ions) can be simultaneously implanted into the gate electrode 15 and the gate insulating film 14 (FIG. 2). The hydrogen ions diffuse into the channel region of the polycrystalline silicon thin film 13 (the region of the polycrystalline silicon thin film 13 where the gate electrode 15 serves as a mask and phosphorus ions are not implanted) by the heat treatment after forming the protective insulating film 22. Effectively compensating for unbonded hands in this channel region. In addition,
In this embodiment, as shown in FIG. 2, the hydrogen concentration in the gate insulating film 14 or the gate electrode 15 is 10 ²⁰ cm.
^-3 or more, but if the hydrogen concentration in the gate insulating film 14 or the gate electrode 15 is 10 ¹⁹ cm ^-3 or more, dangling bonds in the channel region can be effectively compensated. .

FIG. 3A is a diagram showing the effect of heat treatment (annealing) in the hydrogen atmosphere after forming the protective insulating film 22 on the TFT characteristics, and the vertical axis represents the drain current Id of the TFT.
And the horizontal axis is the gate voltage Vg, showing the Id-Vg characteristics. Note that, for example, “1E-08” on the scale on the vertical axis of FIG. 3A indicates 1 × 10 ⁻⁸ . A schematic diagram of the measurement system is shown in FIG. The measured TFT size is channel width W = 12 μm and channel length L = 12 μm. The drain current Id was measured by keeping the drain voltage Vd constant at 10 V and changing the gate voltage Vg.

As shown by the broken line in FIG. 3A, the TFT characteristics are insufficient in the state before the heat treatment in which the protective insulating film 22 is formed, the slope of the rising region of the Id-Vg characteristics is small, and the mobility is high. Was 40 cm ² / V · sec and the threshold voltage was 12V. On the other hand, as shown by the solid line in FIG. 3A, in the state after the heat treatment, the slope of the rising region of the Id-Vg characteristic becomes steep and the mobility is 100 cm.
² / V · sec, the threshold voltage was 1.8 V, and the TFT characteristics were significantly improved.

As described above, according to this embodiment, the gate insulating film 14 is simultaneously doped with impurities by the ion doping method without performing the hydrogen plasma treatment as in the conventional case.
By introducing hydrogen into the gate electrode 15 and diffusing it into the channel region of the polycrystalline silicon thin film 13 by heat treatment, the diffusion distance of hydrogen required to compensate dangling bonds in the channel region is shortened, and the hydrogenation efficiency is reduced. Improve TF
In addition to improving the T characteristic, the time required for the heat treatment for diffusing hydrogen is about 2 hours in this embodiment, as compared with the conventional hydrogen plasma processing that required several hours to several tens of hours. Time can be shortened and productivity can be improved. As a result, the productivity of the liquid crystal display device as in this embodiment can be improved.

Further, since the silicon nitride film is used as the protective insulating film 22, the silicon nitride film has a low hydrogen permeability, and moreover, by forming the silicon nitride film by the plasma CVD method, a large amount of hydrogen is contained in the film. To include
Hydrogen in the gate insulating film 14 and the gate electrode 15 is less likely to diffuse toward the protective insulating film 22 and preferentially diffuse toward the polycrystalline silicon thin film 13, so that hydrogenation efficiency is further improved and The dangling bonds in the channel region of the crystalline silicon thin film 13 can be effectively compensated, and the characteristics of the thin film transistor can be further improved.

Further, an annealing apparatus may be used instead of the conventionally required hydrogen plasma processing apparatus, and the apparatus cost can be greatly reduced. Further, since the annealing apparatus can process a large number of sheets in the same manner, the processing time per sheet can be significantly shortened, and the throughput of the manufacturing process can be greatly increased.

In this embodiment, since hydrogen is introduced into the gate insulating film 14 and the gate electrode 15 at the same time as the introduction of impurities by the ion doping method without the mass separation step, the manufacturing time can be shortened. Although a large effect can be obtained with the above method, it is effective even if the introduction of impurities and the introduction of hydrogen are performed separately by an ion implantation method that includes a mass separation step and implants only specific ions.

In this embodiment, the protective insulating film 2
2 As the heat treatment after formation, annealing was carried out in a hydrogen atmosphere, but if annealing is carried out in a nitrogen atmosphere and normal pressure, the productivity can be further improved. By performing this under a nitrogen atmosphere and normal pressure, the vacuum exhaust system is not required for the annealing device, the apparatus cost is significantly reduced, and the vacuum exhaust / atmosphere opening cycle is not required, so that the productivity is further improved. Further, in a hydrogen atmosphere, an explosion-proof structure is required even if it is used at atmospheric pressure in terms of safety, but it is not necessary in a nitrogen atmosphere.

The heat treatment after forming the protective insulating film 22 is
It is performed in a heat treatment atmosphere containing at least one of hydrogen and nitrogen at a processing temperature of 300 ° C. or higher and 500 ° C. or lower. This is because a temperature of 300 ° C. or higher is required for hydrogen in the gate insulating film 14 or the gate electrode 15 to diffuse into the channel region, and if it exceeds 500 ° C., dangling bonds in the channel region are compensated. This is because hydrogen is desorbed again and the characteristics deteriorate.

Although the silicon oxide film formed by the atmospheric pressure CVD method is used as the gate insulating film 14 in this embodiment, a silicon oxide film formed by the plasma CVD method may be used. Further, a silicon oxide film formed by atmospheric pressure CVD method or plasma CVD method and a silicon nitride film formed by plasma CVD method or a tantalum oxide film formed by sputtering method are laminated on the polycrystalline silicon thin film 13. By using the laminated film as the gate insulating film 14, it becomes possible to more effectively compensate the dangling bonds of the polycrystalline silicon thin film 13. This is plasma C
This is because the silicon oxide film and the silicon nitride film formed by the VD method contain a large amount of hydrogen. In addition, as the insulating film arranged in contact with the polycrystalline silicon thin film 13,
The silicon oxide film has few interface states and exhibits good characteristics.

In the above embodiment, phosphorus is introduced as an impurity for forming the source / drain regions, but this may be any substance that acts as a donor such as arsenic when an n-channel thin film transistor is manufactured. In the case of manufacturing a thin film transistor for a channel, any material that acts as an acceptor such as boron may be used.

[0046]

According to the method of manufacturing the thin film transistor array of the present invention, the hydrogen diffusion distance required for compensating dangling bonds in the channel region of the polycrystalline silicon thin film is shortened to improve the hydrogenation efficiency. In addition to improving the characteristics of the thin film transistor, the heat treatment time for diffusing hydrogen can be shortened and productivity can be improved as compared with the processing time of the conventional hydrogen plasma processing.

Further, in the method of manufacturing the liquid crystal display device of the present invention, by using the method of manufacturing the thin film transistor array of the present invention, the unbonded hands of the polycrystalline silicon thin film of the thin film transistor are compensated, and the characteristics are improved. Manufacturing time can be shortened and productivity can be improved.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view showing a method of manufacturing a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a depth-direction profile of hydrogen under a gate electrode when phosphorus is implanted by ion doping in the embodiment of the present invention.

FIG. 3 is a diagram showing a current-voltage characteristic of a thin film transistor and its measurement system in an embodiment of the present invention.

4A to 4C are process cross-sectional views showing a method of manufacturing a conventional thin film transistor.

[Explanation of symbols]

11 glass substrate 12 buffer layers 13 Polycrystalline silicon thin film 14 Gate insulating film 15 Gate electrode 18 Interlayer insulation film 19 contact holes 20a pixel electrode 20b drain electrode 21 Source electrode wiring 22 Protective insulation film

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroshi Tsutsumi             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F-term (reference) 2H092 JA05 JA24 JA28 KA01 KA02                       KA04 MA07 MA08 MA22 NA21                       NA27                 5F052 AA02 BB07 DA02 DB03 EA15                       JA01                 5F110 AA17 AA19 BB01 CC02 DD02                       DD13 EE06 EE42 EE50 FF01                       FF02 FF03 FF07 FF09 FF28                       FF29 FF30 FF40 GG02 GG13                       GG25 GG28 GG29 GG45 HJ01                       HJ02 HJ04 HJ12 HJ23 HL03                       HL04 HL07 HL11 NN03 NN04                       NN23 NN24 NN35 NN72 PP03                       PP04 PP29 PP35 QQ11 QQ23

Claims (9)

[Claims] 1. A polycrystalline silicon thin film forming step of forming a polycrystalline silicon thin film on a transparent substrate; a gate insulating film forming step of forming a gate insulating film on the polycrystalline silicon thin film; A gate electrode forming step of forming a gate electrode on the film; a hydrogen introducing step of introducing hydrogen into the gate insulating film and the gate electrode; and an interlayer insulating film forming of forming an interlayer insulating film on the gate insulating film and the gate electrode. A step, a display electrode forming step of forming a display electrode connected to the polycrystalline silicon thin film, a protective insulating film forming step of forming a protective insulating film covering at least the display electrode, and the protective insulating film forming step, A heat treatment step of diffusing the hydrogen introduced into the gate insulating film and the gate electrode into the polycrystalline silicon thin film. The method of production. 2. The method of manufacturing a thin film transistor array according to claim 1, wherein the protective insulating film is a silicon nitride film. 3. A plasma CV for forming the silicon nitride film using a mixed gas of hydrogen, nitrogen, ammonia and silane.
The method of manufacturing a thin film transistor array according to claim 2, wherein the thin film transistor array is formed by the D method. 4. The heat treatment temperature in the heat treatment step is 30.
The method for manufacturing a thin film transistor array according to claim 1, wherein the temperature is 0 ° C. or higher and 500 ° C. or lower. 5. The method of manufacturing a thin film transistor array according to claim 1, wherein the heat treatment step is performed in an atmosphere containing at least one of hydrogen and nitrogen. 6. An impurity introducing step of introducing an impurity into a polycrystalline silicon thin film, wherein the impurity introducing step comprises:
The method of manufacturing a thin film transistor array according to claim 1, wherein ions formed by plasma decomposition of the impurity hydrogen dilution gas are injected without mass separation. 7. In the hydrogen introducing step, the hydrogen concentration of at least one of the gate insulating film and the gate electrode is 10 ¹⁹
7. The method of manufacturing a thin film transistor array according to claim 1, wherein hydrogen is introduced so as to have a cm ⁻³ or more. 8. The gate insulating film comprises a silicon oxide film formed by atmospheric pressure CVD method or plasma CVD method, and a silicon nitride film formed by plasma CVD method or tantalum oxide film formed by sputtering method. 8. The method of manufacturing a thin film transistor array according to claim 1, wherein the thin film is a laminated film and the silicon oxide film is formed so as to be in contact with the polycrystalline silicon thin film. 9. A method of manufacturing a liquid crystal display device, comprising the method of manufacturing a thin film transistor array according to claim 1.